ANALOG DEVICES ADM706P, ADM706R, ADM706S, ADM706T Service Manual

3 V, Voltage Monitoring

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

FEATURES

Precision supply voltage monitor

2.63 V (ADM706P, ADM706R, ADM708R)

2.93 V (ADM706S, ADM708S)

3.08 V (ADM706T, ADM708T) 100 μA quiescent current 200 ms reset pulse width Debounced manual reset input (

MR

)

Independent watchdog timer

1.6 second timeout (ADM706x) Reset output

Active high (ADM706P) Active low (ADM706R, ADM706S, ADM706T) Both active high and active low (ADM708R, ADM708S,

ADM708T) Voltage monitor for power-fail or low battery warning Guaranteed

RESET

valid with VCC = 1 V

Superior upgrade for MAX706P/R/S/T, MAX708R/S/T

APPLICATIONS

Microprocessor systems Computers Controllers Intelligent instruments Critical microprocessor monitoring Battery-operated systems Portable instruments

Microprocessor Supervisory Circuits

FUNCTIONAL BLOCK DIAGRAMS

WATCHDOG INPUT (WDI)

V

POWER-FAIL

INPUT (PFI)

V

POWER-FAIL

INPUT (PFI)

WATCHDOG TRANSITIO N

DETECTOR

V

CC

70μA

MR

CC

V

*

REF

1.25V

*

VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)

WATCHDOG

TIMER

RESET AND WATCHDOG

TIMEBASE

RESET

GENERATOR

ADM706P/ADM706R/

ADM706S/ADM706T

Figure 1. ADM706P/ADM706R/ADM706S/ADM706T

V

CC

70μA

MR

CC

V

*

REF

1.25V

* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3. 08V (T)

RESET

GENERATOR

ADM708R/ADM708S/

ADM708T

Figure 2. ADM708R/ADM708S/ADM708T

WATCHD OG OUTPUT (WDO)

RESET, (P = RESET)

POWER-FAIL OUTPUT (PFO)

RESET

POWER-FAIL OUTPUT (PFO)

06435-001

06435-002

GENERAL DESCRIPTION

The ADM706P/ADM706R/ADM706S/ADM706T and the ADM708R/ADM708S/ADM708T microprocessor supervisory circuits are suitable for monitoring either 3 V or 3.3 V power supplies.

The ADM706P/ADM706R/ADM706S/ADM706T provide power-supply monitoring circuitry that generate a reset output during power-up, power-down, and brownout conditions. The reset output remains operational with V Independent watchdog monitoring circuitry is also provided. This is activated if the watchdog input has not been toggled within 1.6 seconds.

In addition, there is a 1.25 V threshold detector for power-fail warning, low battery detection, or to monitor an additional power supply. An active low debounced

MR

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

as low as 1 V.

CC

input is also included.

The ADM706R, ADM706S, and ADM706T are identical except for the reset threshold monitor levels, which are 2.63 V, 2.93 V, and

3.08 V, respectively. The ADM706P is identical to the ADM706R in that the reset threshold is 2.63 V. It differs only in that it has an active high reset output.

The ADM708R/ADM708S/ADM708T provide similar functionality as the ADM706R/ADM706S/ADM706T and only differ in that a watchdog timer function is not available. Instead, an active high reset output (RESET) is provided in addition to the active low (

RESET

) output.

All parts are available in narrow 8-lead PDIP and 8-lead SOIC packages.

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

REVISION HISTORY

5/08—Rev. B to Rev. C

Changes to Applications Section .................................................... 1

Changes to Table 2 ............................................................................ 5

Changes to Table 3 ............................................................................ 6

Changes to Figure 8 .......................................................................... 7

Changes to Figure 16 ........................................................................ 9

Manual Reset ............................................................................... 10

Watchdog Timer (ADM706x) .................................................. 10

Power-Fail Comparator ............................................................. 11

Adding Hysteresis to the Power-Fail Comparator ................. 11

RESET

Va l id

Applications Information .............................................................. 12

Monitoring Additional Supply Levels ...................................... 12

Microprocessors with Bidirectional

Outline Dimensions ....................................................................... 13

Ordering Guide .......................................................................... 14

Below 1 V VCC ..................................................... 11

RESET

........................... 12

2/07—Rev. A to Rev. B

Updated Format .................................................................. Universal

Changes to Table 1 ............................................................................ 3

Updated Outline Dimensions ....................................................... 12

Changes to Ordering Guide .......................................................... 13

Rev. C | Page 2 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

SPECIFICATIONS

VCC = 2.70 V to 5.5 V (ADM706P/ADM70xR), VCC = 3.00 V to 5.5 V (ADM70xS), VCC = 3.15 V to 5.5 V (ADM70xT), TA = T unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

VCC Operating Voltage Range 1.0 5.5 V

Supply Current 100 200 μA VCC < 3.6 V

150 350 μA VCC < 5.5 V LOGIC OUTPUT

Reset Threshold (V

) 2.55 2.63 2.70 V ADM706P/ADM70xR

RST

2.85 2.93 3.00 V ADM70xS

3.00 3.08 3.15 V ADM70xT

Reset Threshold Hysteresis 20 mV

RESET PULSE WIDTH 160 200 280 ms ADM706P/ADM70xR, VCC = 3 V 160 200 280 ms ADM70xS/ADM70xT, VCC = 3.3 V 200 ms VCC = 5.0 V RESET OUTPUT VOLTAGE

(ADM70xR/ADM70xS/ADM70xT)

VOH 0.8 × VCC V V

VOL 0.3 V V

VOH V

− 1.5 V V 4.5 V < VCC < 5.5 V, I

CC

VOL 0.4 V 4.5 V < VCC < 5.5 V, I

VOL 0.3 V VCC = 1 V, I

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

= 100 μA

SINK

SOURCE

= 3.2 mA

SINK

SOURCE

= 1.2 mA

SINK

= 800 μA

RESET OUTPUT VOLTAGE (ADM706P)

VOH V

VOL 0.3 V V

VOH V

VOL 0.4 V 4.5 V < VCC < 5.5 V, I

− 0.6 V V V

CC

− 1.5 V V 4.5 V < VCC < 5.5 V, I

CC

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

SOURCE

= 3.2 mA

SINK

SOURCE

= 1.2 mA

SINK

= 800 μA

RESET OUTPUT VOLTAGE (ADM708x)

VOH 0.8 × VCC V V

VOL 0.3 V V

VOH V

− 1.5 V V 4.5 V < VCC < 5.5 V, I

CC

VOL 0.4 V 4.5 V < VCC < 5.5 V, I

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

SOURCE

= 1.2 mA

SINK

SOURCE

= 500 μA

SINK

= 800 μA

WATCHDOG INPUT (ADM706x)

Watchdog Timeout Period 1.00 1.60 2.25 sec

WDI Pulse Width 100 ns V

ADM706P/ADM706R: V ADM706S/ADM706T: V V

= 0.4 V, VIH = VCC × 0.8 V

IL

(max) < VCC < 3.6 V

RST

= 3 V;

CC

= 3.3 V;

CC

50 ns 4.5 V < VCC < 5.5 V

WDI Input Threshold

VIL 0.6 V V VIH 0.7 × VCC V V

(max) < VCC < 3.6 V

RST

(max) < VCC < 3.6 V

RST

VIL 0.8 V VCC = 5.0 V VIH 3.5 V VCC = 5.0 V

WDI Input Current −1.0 +0.02 +1.0 μA WDI = 0 V or VCC

WDO OUTPUT VOLTAGE

VOH 0.8 × VCC V V

V

VOL 0.3 V V

0.4 V 4.5 V < VCC < 5.5 V, I

(max) < VCC < 3.6 V, I

RST

− 1.5 V V 4.5 V < VCC < 5.5 V, I

CC

(max) < VCC < 3.6 V, I

RST

SOURCE

= 1.2 mA

SINK

SOURCE

= 800 μA

= 500 μA

SINK

to T

MIN

= 500 μA

= 215 μA

= 500 μA

MAX

Rev. C | Page 3 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

Parameter Min Typ Max Unit Test Conditions/Comments

MANUAL RESET INPUT

MR Pull-Up Current (MR = 0 V)

25 70 250 μA V 100 250 600 μA 4.5 V < VCC < 5.5 V MR Pulse Width

500 ns V

150 ns 4.5 V < VCC < 5.5 V MR INPUT THRESHOLD

VIL 0.6 V V VIH 0.7 × VCC V V VIL 0.8 V 4.5 V < VCC < 5.5 V VIH 2.0 V 4.5 V < VCC < 5.5 V

MR TO RESET OUTPUT DELAY

750 ns V

250 ns 4.5 V < VCC < 5.5 V POWER-FAIL INPUT

PFI Input Threshold 1.2 1.25 1.3 V

PFI Input Current −25 +0.01 +25 nA

PFO OUTPUT VOLTAGE

VOH 0.8 × VCC V V VOL 0.3 V V VOH V

− 1.5 V V 4.5 V < VCC < 5.5 V, I

CC

VOL 0.4 V 4.5 V < VCC < 5.5 V, I

(max) < VCC < 3.6 V

RST

(max) < VCC < 3.6 V

RST

(max) < VCC < 3.6 V

RST

(max) < VCC < 3.6 V

RST

(max) < VCC < 3.6 V

RST

ADM70xP/ADM70xR, V ADM70xS/ADM70xT, V

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

SOURCE

SINK

= 3 V

CC

= 3.3 V, PFI falling

CC

= 500 μA

SOURCE

= 1.2 mA

SINK

= 800 μA

= 3.2 mA

Rev. C | Page 4 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

ABSOLUTE MAXIMUM RATINGS

TA = 25°C unless otherwise noted.

Table 2.

Parameter Rating

VCC −0.3 V to +6 V All Other Inputs −0.3 V to VCC + 0.3 V Input Current

VCC 20 mA

GND 20 mA Digital Output Current 20 mA Power Dissipation, N-8 (PDIP) 727 mW

θJA Thermal Impedance 135°C/W Power Dissipation, R-8 (SOIC) 470 mW

θJA Thermal Impedance 110°C/W Operating Temperature Range

Industrial (Version A) −40°C to +85°C Lead Temperature (Soldering, 10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C Storage Temperature Range −65°C to +150°C ESD Rating >4.5 kV

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. C | Page 5 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

G

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

MR

V

CC

ND

PFI

1

2

ADM706P

3

TOP VIEW

(Not to Scale)

4

8

7

6

5

WDO

RESET

WDI

PFO

1

MR

ADM706R/

2

V

ADM706S/

CC

ADM706T

3

ND

TOP VIEW

4

PFI

(Not to Scale)

06435-003

Figure 3. ADM706P Figure 4. ADM706R/ADM706S/ADM706T

Table 3. Pin Function Descriptions ADM706P/ADM706R/ADM706S/ADM706T

Pin No. Mnemonic Description

1

Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven

MR

from TTL, CMOS logic, or from a manual reset switch because it is internally debounced. An

internal 70 μA pull-up current holds the input high when floating. 2 VCC Power Supply Input. 3 GND 4 PFI

5

PFO

Ground. Ground reference for all signals (0 V).

Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less

than 1.25 V, PFO

goes low. If unused, PFI should be connected to GND.

Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is

less than 1.25 V. 6 WDI

Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout

period, the watchdog output, WDO

, goes low. The timer resets with each transition at the WDI input. Either a high-to-low or a low-to-high transition clears the counter. The internal timer is also cleared whenever reset is asserted.

7 (ADM706R/ADM706S/ ADM706T Only)

RESET

Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset threshold or by a low signal on the MR is below the reset threshold. It remains low for 200 ms after VCC goes above the reset threshold

or MR

goes from low to high. A watchdog timeout does not trigger RESET unless WDO is

7 (ADM706P Only) RESET

8

WDO

connected to MR Logic Output. RESET is an active high output suitable for systems that use active high reset

logic. It is the inverse of RESET

Watchdog Output. WDO goes low if the internal watchdog timer times out as a result of

.

inactivity on the WDI input. It remains low until the watchdog timer is cleared. WDO low during low line conditions. Whenever VCC is below the reset threshold, WDO remains low. As soon as V

goes above the reset threshold, WDO goes high immediately.

CC

8

WDO

RESET

7

6

WDI

5

PFO

06435-004

input. RESET remains low whenever VCC

also goes

Rev. C | Page 6 of 16

G

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

1 8

MR

ADM708R/

V

2

ADM708S/

CC

ADM708T

ND

3

TOP VIEW

4

PFI

(Not to Scale)

NC = NO CONNECT

Figure 5. ADM708R/ADM708S/ADM708T

Table 4. Pin Function Descriptions ADM708R/ADM708S/ADM708T

Pin No. Mnemonic Description

1

Manual Reset Input. When taken below 0.6 V, a RESET/RESET is generated. MR can be driven from TTL, CMOS

MR

logic, or from a manual reset switch because it is internally debounced. An internal 70 μA pull-up current holds

the input high when floating. 2 VCC Power Supply Input. 3 GND 4 PFI

Ground. Ground reference for all signals (0 V).

Power-Fail Input. PFI is the noninverting input to the power-fail comparator. When PFI is less than 1.25 V, PFO

goes low. If unused, PFI should be connected to GND. 5

PFO

Power-Fail Output. PFO is the output from the power-fail comparator. It goes low when PFI is less than 1.25 V. 6 NC No Connect. 7

8 RESET

RESET Logic Output. RESET goes low for 200 ms when triggered. It is triggered either by VCC being below the reset

threshold or by a low signal on the MR

remains low for 200 ms after V

CC

timeout does not trigger RESET

input. RESET remains low whenever VCC is below the reset threshold. It

goes above the reset threshold or MR goes from low to high. A watchdog

unless WDO is connected to MR.

Logic Output. RESET is an active high output suitable for systems that use active high reset logic. It is the

inverse of RESET

.

7

6

5

RESET

NC

PFO

06435-005

Rev. C | Page 7 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

V

TYPICAL PERFORMANCE CHARACTERISTICS

VCC = 3.3V T

= 25°C

A

V

RESET

CC

400ms/DIV

Figure 6. ADM70xR/ADM70xS/ADM70xT RESET

Output Voltage vs. Supply Voltage

3

06435-01

1.2V

PFO

0V

500ns/DIV

Figure 9. PFI Deassertion Response Time

VCC = V TA = 25°C

RT

1.3V PFI

3V

06435-016

V

CC

RESET

400ms/DIV

Figure 7. RESET Output Voltage vs. Supply Voltage

1.3V PFI

3V

500ns/DIV

Figure 8. PFI Assertion Response Time

VCC = 3.3V T

= 25°C

A

1.2V

PFO

0V

RESET RESET

0

06435-014

Figure 10.

RESET RESET

0

06435-015

Figure 11.

100ns/DIV

RESET

, RESET Assertion

100ns/DIV

RESET

, RESET Deassertion

VCC = V TA = 25°C

3V3

0V

06435-017

RT

3V3

0V

06435-018

Rev. C | Page 8 of 1

6

706T, ADM708R/ADM708S/ADM708TADM706P/ADM706R/ADM706S/ADM

TA = 25°C

3V

V

CC

2V

3V

RESET

0V

Figure 12. ADM70xR/ADM70xS/ADM70xT

2µs/DIV

RESET

Response Time

06435-019

Rev. C | Page 9 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

CIRCUIT INFORMATION

MANUAL RESET

The MR input allows other reset sources, such as a manual reset switch, to generate a processor reset. The input is effectively debounced by the timeout period (200 ms typical). The input is TTL-/CMOS-compatible; it can also be driven by any logic reset output. If unused, the

MR

input can be tied high or

left floating.

V

RESET

WDO

MR

CC

V

NOTES RESET = COMPLEMENT OF RESET

RT

Figure 15.

V

RT

RESET

t

RS

, MR, and

WDO

MR EXTERNALLY DRIVEN LOW

Timing

t

RS

WATCHDOG TIMER (ADM706x)

The watchdog timer circuit is used to monitor the activity of the microprocessor to check that it is not stalled in an indefinite loop. An output line on the processor is used to toggle the watchdog input (WDI) line. If this line is not toggled within the timeout period (1.6 seconds), the watchdog output (

WDO

The

output is connected to a nonmaskable interrupt (NMI) on the processor. Therefore, if the watchdog timer times out, an interrupt is generated. The interrupt service routine is used to rectify the problem.

The watchdog timer is cleared either by a high-to-low or by a low-to-high transition on WDI. Pulses as narrow as 50 ns are detected. The timer is also cleared by RESET/ active. Therefore, the watchdog timeout period begins after reset goes inactive.

When V

falls below the reset threshold,

CC

whether or not the watchdog timer has timed out. Normally, this generates an interrupt, but it is overridden by RESET/ going active.

t

WDI

WDO

RESET

WP

t

WD

Figure 16. Watchdog Timing

RESET EXTERNALLY TRIG GERED BY MR

WDO

) is driven low.

RESET

WDO

t

WD

is forced low

t

RS

MR

WATCHDOG TRANSITIO N

DETECTOR

V

CC

70μA

CC

V

*

REF

WATCHDOG

TIMER

RESET AND WATCHDOG

TIMEBASE

RESET

GENERATOR

ADM706P/ADM706R/

ADM706S/ADM706T

1.25V

*

VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)

WATCHDOG OUTPUT (W DO)

RESET, (P = RESET)

POWER-FAIL OUTPUT (PFO)

WATCHD OG INPUT (WDI)

V

POWER-FAIL

INPUT (PFI)

Figure 13. ADM706 Functional Block Diagram

V

CC

V

POWER-FAIL

INPUT (PFI)

70μA

MR

CC

V

*

REF

1.25V

* VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3. 08V (T)

RESET

GENERATOR

ADM708R/ADM708S/

ADM708T

RESET

POWER-FAIL OUTPUT (PFO)

Figure 14. ADM708 Functional Block Diagram

POWER-FAIL RESET

The reset output provides a reset (RESET or signal to the microprocessor whenever the V the reset threshold. The actual reset threshold voltage is dependent on whether a P, R, S, or T suffix device is used. An internal timer holds the reset output active for 200 ms after the voltage on V rises above the threshold. This is intended as a power-on reset signal for the microprocessor. It allows time for both the power supply and the microprocessor to stabilize after power-up. If a power supply brownout or interruption occurs, the reset line is similarly activated and remains active for 200 ms after the supply recovers. If another interruption occurs during an active reset period, the reset timeout period continues for an additional 200 ms.

The reset output is guaranteed to remain valid with V as 1 V. This ensures that the microprocessor is held in a stable shutdown condition as the power supply starts up.

The ADM706P provides an active high RESET signal; the ADM706R/ADM706S/ADM706T provide an active low signal; and the ADM708R/ADM706S/ADM706T provide both RESET and

RESET

.

RESET

) output

input is below

CC

as low

RESET

00606435-

06435-007

MR

going

RESET

t

WD

06435-008

06435-009

Rev. C | Page 10 of 16

V

R

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

POWER-FAIL COMPARATOR

The power-fail comparator is an independent comparator that can be used to monitor the input power supply. The inverting input of the comparator is internally connected to a 1.25 V reference voltage. The noninverting input is available at the PFI input. This input is used to monitor the input power supply via a resistive divider network. When the voltage on the PFI input drops below 1.25 V, the comparator output ( indicating a power failure. For early warning of power failure, the comparator is used to monitor the preregulator input simply by choosing an appropriate resistive divider network. The output is used to interrupt the processor so that a shutdown procedure is implemented before the power is lost.

INPUT

POWE

R1

POWER-FAIL

R2

INPUT

Figure 17. Power-Fail Comparator

1.25V

PFI

ADM706P/ADM706R/ ADM706S/ADM706T/ ADM708R/ADM708S/

ADM708T

PFO

) goes low,

POWER-FAIL OUTPUT

PFO

06435-010

INPUT

POWER

ADM663A

R1

R2

3.3V

PFO

0V

Figure 18. Adding Hysteresis to the Power-Fail Comparator

V

H

25.1

L

3.3

1.25V

PFI

ADM706P/ADM706R/ ADM706S/ADM706T/ ADM708R/ADM708S/

ADM708T

V

H

L

V

IN

⎡

⎛

+

⎜

+= R1

125.1

⎢

⎜

⎢

⎣

×

⎝

25.1

⎛

R1V

⎜

R2

⎝

V

CC

–

+

R3

⎤

⎞

R3R2

⎟

⎥

⎟

R3R2

⎥

⎠

⎦

−

V

CC

−+=

R3

TO MICROPROCESSOR NMI

PFO

25.1

⎞ ⎟

⎠

6435-011

ADDING HYSTERESIS TO THE POWER-FAIL COMPARATOR

For increased noise immunity, hysteresis can be added to the power-fail comparator. Because the comparator circuit is noninverting, hysteresis is added simply by connecting a resistor between the When junction at the PFI pin. When current into the PFI summing junction. This results in differing trip levels for the comparator. Further noise immunity is achieved by connecting a capacitor between PFI and GND.

PFO

output and the PFI input as shown in .

PFO

is low, Resistor R3 sinks current from the summing

PFO

is high, Resistor R3 sources

Figure 18

+

R2R1

R2

⎞ ⎟

⎠

V

MID

⎜ ⎝

⎛

25.1

=

VALID RESET BELOW 1 V VCC

The ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ ADM708T are guaranteed to provide a valid reset level with V as low as 1 V. Refer to the Typical Performance Characteristics section. As V have sufficient drive to hold it on so the voltage on longer held at 0 V. A pull-down resistor, as shown in , can

drops below 1 V, the internal transistor does not

CC

RESET

Figure 19

be connected externally to hold the line low if it is required.

ADM706R/ADM706S/ ADM706T/ADM708R/

ADM708S/ADM708T

RESET

Figure 19.

GND

RESET

Valid Below 1 V

R1

06435-012

CC

is no

Rev. C | Page 11 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

APPLICATIONS INFORMATION

A typical operating circuit is shown in Figure 20. The unregulated dc input supply is monitored using the PFI input via the resistive divider network. Resistor R1 and Resistor R2 are to be selected so that when the supply voltage drops below the desired level (for example, 5 V), the voltage on PFI drops below the 1.25 V threshold, thereby generating an interrupt to the microprocessor. Monitoring the preregulator input gives additional time to execute an orderly shutdown procedure before power is lost.

UNREGULATED

DC

ADM666A

IN

GND

OUT

PFI

MR

3.3V

V

CC

ADM706R/ ADM706S/

ADM706T

GND

RESET

WDI

WDO

PFO

V

CC

RESET

I/O LINE

MICROPROCESSOR

NMI

INTERRUPT

GND

MONITORING ADDITIONAL SUPPLY LEVELS

It is possible to use the power-fail comparator to monitor a second supply as shown in Figure 22. The two sensing resistors, R1 and R2, are selected such that the voltage on PFI drops below 1.25 V at the minimum acceptable input supply. The connected to the

MR

input so that a reset is generated when the supply drops out of tolerance. In this case, if either supply drops out of tolerance, a reset i

V

+3V/+3.3V

X

V

R1

R2

Figure 22. Monitoring 3 V/3.3 V and an Additional Supply, V

CC

ADM706R/ ADM706S/

ADM706T

PFI

MR

GND

s generated.

RESET

WDI

PFO

output can be

RESET

MICROPROCESSOR

06435-022

X

MANUAL

RESET

Figure 20. Typical Application Circuit

Microprocessor activity is monitored using the WDI input. This is driven using an output line from the processor. The software routines toggle this line at least once every 1.6 seconds. If a problem occurs and this line is not toggled,

WDO

goes low and a nonmaskable interrupt is generated. This interrupt routine is to be used to clear the problem.

If, in the event of inactivity on the WDI line, a system reset is

WDO

required, the

output is to be connected to the input as

shown in . Figure 21

RESET

I/O LINE

MICROPROCESSOR

from WDO

06435-021

ADM706R/ ADM706S/

PFI

ADM706T

MR

GND

RESET

WDI

WDO

Figure 21.

RESET

MICROPROCESSORS WITH BIDIRECTIONAL RESET

06435-020

To prevent contention for microprocessors with a bidirectional reset line, a current limiting resistor is to be inserted between the ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ ADM708T

RESET

output pin and the microprocessor reset pin. This limits the current to a safe level if there are conflicting output reset levels. A suitable resistor value is 4.7 kΩ. If the reset output is required for other uses, it should be buffered as shown in . Figure 23

+3V/+3.3V

V

CC

ADM706R/ADM706S/ ADM706T/ADM708R/

ADM708S/ADM708T

RESET

GND

Figure 23. Bidirectional Input/Output

MICROPROCESSOR

RESET

BUFFERED RESET

GND

RESET

06435-023

Rev. C | Page 12 of

16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

OUTLINE DIMENSIONS

0.210 (5.33)

0.150 (3.81)

0.130 (3.30)

0.115 (2.92)

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

MAX

0.400 (10.16)

0.365 (9.27)

0.355 (9.02)

8

1

0.100 (2.54) BSC

0.070 (1.78)

0.060 (1.52)

0.045 (1.14)

5

4

0.280 (7.11)

0.250 (6.35)

0.240 (6.10)

0.015 (0.38) MIN

SEATING PLANE

0.005 (0.13) MIN

0.060 (1.52) MAX

0.015 (0.38) GAUGE

PLANE

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

0.430 (10.92) MAX

0.195 (4.95)

0.130 (3.30)

0.115 (2.92)

0.014 (0.36)

0.010 (0.25)

0.008 (0.20)

CONTROLL ING DIMENS IONS ARE IN INCHES; MILLIMETER DI MENSIONS (IN PARENTHESES) ARE ROUNDED-OF F INCH EQUI VALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOL E OR HALF LEADS.

COMPLIANT TO JEDEC STANDARDS MS-001

070606-A

Figure 24. 8-Lead Plastic Dual In-Line Package [PDIP]

Narrow Body

(N-8)

Dimension shown in inches and (millimeters)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

Figure 25. 8-Lead Standard Small Outline Package [SOIC_N]

Dimensions shown in millimeters and (inches)

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

Narrow Body

(R-8)

8° 0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Rev. C | Page 13 of 16

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADM706PAN −40°C to +85°C 8-Lead PDIP N-8 ADM706PANZ ADM706PAR −40°C to +85°C 8-Lead SOIC_N R-8 ADM706PAR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 ADM706PARZ ADM706PARZ-REEL ADM706RAN −40°C to +85°C 8-Lead PDIP N-8 ADM706RANZ1 −40°C to +85°C 8-Lead PDIP N-8 ADM706RAR −40°C to +85°C 8-Lead SOIC_N R-8 ADM706RAR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 ADM706RAR-REEL7 −40°C to +85°C 8-Lead SOIC_N R-8 ADM706RARZ ADM706RARZ-REEL ADM706RARZ-REEL7 ADM706SAN −40°C to +85°C 8-Lead PDIP N-8 ADM706SANZ1 −40°C to +85°C 8-Lead PDIP N-8 ADM706SAR −40°C to +85°C 8-Lead SOIC_N R-8 ADM706SAR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 ADM706SARZ ADM706SARZ-REEL ADM706TAN −40°C to +85°C 8-Lead PDIP N-8 ADM706TANZ1 −40°C to +85°C 8-Lead PDIP N-8 ADM706TAR −40°C to +85°C 8-Lead SOIC_N R-8 ADM706TAR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 ADM706TARZ ADM706TARZ-REEL ADM708RAN −40°C to +85°C 8-Lead PDIP N-8 ADM708RANZ1 −40°C to +85°C 8-Lead PDIP N-8 ADM708RAR −40°C to +85°C 8-Lead SOIC_N R-8 ADM708RAR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 ADM708RARZ1 −40°C to +85°C 8-Lead SOIC_N R-8 ADM708RARZ-REEL1 −40°C to +85°C 8-Lead SOIC_N R-8 ADM708SAN −40°C to +85°C 8-Lead PDIP N-8 ADM708SANZ1 −40°C to +85°C 8-Lead PDIP N-8 ADM708SAR −40°C to +85°C 8-Lead SOIC_N R-8 ADM708SAR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 ADM708SARZ1 −40°C to +85°C 8-Lead SOIC_N R-8 ADM708SARZ-REEL1 −40°C to +85°C 8-Lead SOIC_N R-8 ADM708TAN −40°C to +85°C 8-Lead PDIP N-8 ADM708TANZ1 −40°C to +85°C 8-Lead PDIP N-8 ADM708TAR −40°C to +85°C 8-Lead SOIC_N R-8 ADM708TAR-REEL −40°C to +85°C 8-Lead SOIC_N R-8 ADM708TARZ ADM708TARZ-REEL

1

Z = RoHS Compliant Part.

1

−40°C to +85°C 8-Lead SOIC_N R-8

1

−40°C to +85°C 8-Lead SOIC_N R-8

1

−40°C to +85°C 8-Lead SOIC_N R-8

1

−40°C to +85°C 8-Lead SOIC_N R-8

1

−40°C to +85°C 8-Lead SOIC_N R-8

1

−40°C to +85°C 8-Lead SOIC_N R-8

1

−40°C to +85°C 8-Lead SOIC_N R-8

−40°C to +85°C 8-Lead PDIP N-8

−40°C to +85°C 8-Lead SOIC_N R-8

Rev. C | Page 14 of 16

NOTES

ADM706P/ADM706R/ADM706S/ADM706T, ADM708R/ADM708S/ADM708T

Rev. C | Page 15 of 16

ADM706P/ADM706R/ADM706S/ADM706T , ADM708R/ADM708S/ADM708T

NOTES

Rev. C | Page 16 of 16

ANALOG DEVICES ADM706P, ADM706R, ADM706S, ADM706T Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

CIRCUIT INFORMATION

MANUAL RESET

WATCHDOG TIMER (ADM706x)

POWER-FAIL RESET

POWER-FAIL COMPARATOR

ADDING HYSTERESIS TO THE POWER-FAIL COMPARATOR

APPLICATIONS INFORMATION

MONITORING ADDITIONAL SUPPLY LEVELS

OUTLINE DIMENSIONS

ORDERING GUIDE