Datasheet ADM706 Datasheet (Analog Devices)

+3 V, Voltage Monitoring

WATCHDOG
TRANSITION

DETECTOR

WATCHDOG

TIMER

1.25V

V

REF

*

WATCHDOG

INPUT (WDI)

POWER FAIL

INPUT (PFI)

POWER FAIL
OUTPUT (PFO)

WATCHDOG
OUTPUT(WDO)

RESET,
(P = RESET)

*VOLTAGE REFERENCE = 2.63V (P/R), 2.93V (S), 3.08V (T)

ADM706

RESET &

WATCHDOG

TIMEBASE

RESET

GENERATOR

MR

V

CC

70mA

V

CC

1.25V

V

REF

*

POWER FAIL

INPUT (PFI)

POWER FAIL
OUTPUT (PFO)

RESET

*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)

ADM708

RESET

GENERATOR

MR

V

CC

70mA

V

CC

RESET

a

FEATURES
Precision Supply-Voltage Monitor

+2.63 V (ADM706P/R, ADM708R)
+2.93 V (ADM706S, ADM708S)

+3.08 V (ADM706T, ADM708T)
100 ␮A Quiescent Current
200 ms Reset Pulsewidth
Debounced Manual Reset Input (MR)
Independent Watchdog Timer—1.6 sec Timeout

(ADM706x)
Reset Output

Active High (ADM706P)

Active Low (ADM706R/S/T)

Both Active High and Active Low (ADM708R/S/T)
Voltage Monitor for Power-Fail or Low Battery Warning
Guaranteed RESET Valid with V
Superior Upgrade for MAX706P/R/S/T, MAX708R/S/T

APPLICATIONS
Microprocessor Systems
Computers
Controllers
Intelligent Instruments
Critical ␮P Monitoring
Automotive Systems
Battery Operated Systems
Portable Instruments

= 1 V

CC

␮P Supervisory Circuits

ADM706P/R/S/T, ADM708R/S/T

FUNCTIONAL BLOCK DIAGRAMS

GENERAL DESCRIPTION

The ADM706P/R/S/T and the ADM708R/S/T microprocessor
supervisory circuits are suitable for monitoring either 3 V or 3.3 V
power supplies.

The ADM706P/R/S/T provide the following functions:

1. Power-supply monitoring circuitry which generates a Reset
output during power-up, power-down and brownout condi­tions. The reset output remains operational with V

as low

CC

as 1 V.

2. Independent watchdog monitoring circuitry which is acti­vated if the watchdog input has not been toggled within

1.6 seconds.

3. A 1.25 V threshold detector for power fail warning, low bat­tery detection, or to monitor an additional power supply.

4. An active low debounced manual reset input (MR).

The ADM706R, ADM706S, ADM706T are identical except for
the reset threshold monitor levels which are 2.63 V, 2.93 V, and

3.08 V respectively. The ADM706P is identical to the ADM706R

in that the reset threshold is 2.63 V. It differs only in that it has
an active high reset output.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

The ADM708R/S/T provide the same functionality as the
ADM706R/S/T and only differ in that:

1. A watchdog timer function is not available.

2. An active high reset output (RESET) in addition to the

active low (RESET) output is available.

All parts are available in 8-lead DIP and narrow SOIC packages.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

(V

ADM706P/R/S/T, ADM708R/S/T–SPECIFICATIONS

V

= 3.00 V to 5.5 V (ADM70_S), V

CC

= 3.15 V to 5.5 V (ADM70_T), TA = T

CC

MIN

to T

unless otherwise noted.)

MAX

= 2.70 V to 5.5 V (ADM70_P/R),

CC

Parameter Min Typ Max Units Test Conditions/Comments

V

Operating Voltage Range 1.0 5.5 V

CC

Supply Current 100 200 µAV

150 350 µAV

Reset Threshold (V

) 2.55 2.63 2.70 V ADM70_P/R

RST

< 3.6 V

CC

< 5.5 V

CC

2.85 2.93 3.00 V ADM70_S

3.00 3.08 3.15 V ADM70_T

Reset Threshold Hysteresis 20 mV

Reset Pulsewidth 160 200 280 ms ADM70_P/R, V

160 200 280 ms ADM70_S/T, V

= 3 V

CC

= 3.3 V

CC

200 ms VCC = 5.0 V

RESET Output Voltage ADM70_R/S/T

V

OH

V

OL

V

OH

V

OL

V

OL

0.8 × V

CC

0.3 V V

VV

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

VCC–1.5 V V 4.5 V < VCC < 5.5 V, I

0.4 V 4.5 V < VCC < 5.5 V, I

0.3 V VCC = 1 V, I

SINK

= 100 µA

SOURCE

= 3.2 mA

SINK

SOURCE

SINK

= 800 µA

RESET Output Voltage ADM706P

V

OH

V

OL

V

OH

V

OL

VCC–0.6 V V V

0.3 V V

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

VCC–1.5 V V 4.5 V < VCC < 5.5 V, I

0.4 V 4.5 V < VCC < 5.5 V, I

SOURCE

= 3.2 mA

SINK

SOURCE

SINK

= 800 µA

RESET Output Voltage ADM708_

V

OH

V

OL

V

OH

V

OL

Watchdog Timeout Period 1.00 1.60 2.25 sec ADM70_P/R; V

WDI Pulsewidth V

0.8 × V

CC

0.3 V V

VV

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

VCC–1.5 V V 4.5 V < VCC < 5.5 V, I

0.4 V 4.5 V < VCC < 5.5 V, I

= 3 V. ADM70_S/T,

< 5.5 V

CC

CC

= 3.3 V

V

CC

= 0.4 V, VIH = (V

IL

100 ns V

(max) < VCC < 3.6 V

RST

50 ns 4.5 V < V

SOURCE

SINK

) × (0.8)

CC

SOURCE

SINK

= 800 µA

= 1.2 mA

WDI Input Threshold ADM706_

V

IL

V

IH

V

IL

V

IH

0.7 × V

CC

3.5 V VCC = 5.0 V

0.6 V V
VV

0.8 V VCC = 5.0 V

WDI Input Current –1.0 0.02 1.0 µA WDI = 0 V or V

(max) < VCC < 3.6 V

RST

(max) < VCC < 3.6 V

RST

CC

WDO Output Voltage

V

OH

V

OL

V

OH

V

OL

0.8 × V

CC

0.3 V V

VCC–1.5 V V 4.5 V < VCC < 5.5 V, I

0.4 V 4.5 V < VCC < 5.5 V, I

VV

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

SOURCE

= 1.2 mA

SINK

SOURCE

SINK

= 800 µA

MR Pull Up Current MR = 0 V

25 70 250 µAV
100 250 600 µA 4.5 V < V

(max) < VCC < 3.6 V

RST

< 5.5 V

CC

MR Pulsewidth

500 ns V

(max) < VCC < 3.6 V

RST

150 ns 4.5 V < VCC < 5.5 V

MR Input Threshold

V

IL

V

IH

V

IL

V

IH

0.7 × V

CC

2.0 V 4.5 V < VCC < 5.5 V

0.6 V V
VV

(max) < VCC < 3.6 V

RST

(max) < VCC < 3.6 V

RST

0.8 V 4.5 V < VCC < 5.5 V

= 500 µA

= 1.2 mA

= 215 µA

= 1.2 mA

= 500 µA

= 500 µA

= 500 µA

= 500 µA

REV. A–2–

ADM706P/R/S/T, ADM708R/S/T

Parameter Min Typ Max Units Test Conditions/Comments

MR to Reset Output Delay 750 ns V

250 ns 4.5 V < VCC < 5.5 V

PFI Input Threshold 1.2 1.25 1.3 V ADM70_P/R; V

PFI Input Current –25 0.01 25 nA
PFO Output Voltage

V

OH

V

OL

V

OH

V

OL

0.8 × V

CC

VV

0.3 V V

VCC–1.5 V V 4.5 V < VCC < 5.5 V, I

0.4 V 4.5 V < VCC < 5.5 V, I

(max) < VCC < 3.6 V

RST

= 3.3 V, PFI falling

V

CC

(max) < VCC < 3.6 V, I

RST

(max) < VCC < 3.6 V, I

RST

CC

= 3 V. ADM70_S/T,

SOURCE

SINK

= 800 µA

SOURCE

= 3.2 mA

SINK

= 500 µA

= 1.2 mA

ORDERING GUIDE

Temperature Package

Model Range Options

ADM706PAN –40°C to +85°C N-8
ADM706PAR –40°C to +85°C SO-8

ADM706RAN –40°C to +85°C N-8
ADM706RAR –40°C to +85°C SO-8

ADM706SAN –40°C to +85°C N-8
ADM706SAR –40°C to +85°C SO-8

ADM706TAN –40°C to +85°C N-8
ADM706TAR –40°C to +85°C SO-8

ADM708RAN –40°C to +85°C N-8
ADM708RAR –40°C to +85°C SO-8

ADM708SAN –40°C to +85°C N-8
ADM708SAR –40°C to +85°C SO-8

ADM708TAN –40°C to +85°C N-8
ADM708TAR –40°C to +85°C SO-8

ABSOLUTE MAXIMUM RATINGS*

(T

= +25°C unless otherwise noted)

A

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

All Other Inputs . . . . . . . . . . . . . . . . . . –0.3 V to V

+ 0.3 V

CC

Input Current

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

V

CC

GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

Power Dissipation, N-8 DIP . . . . . . . . . . . . . . . . . . . .727 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 135°C/W

θ

JA

Power Dissipation, SO-8 SOIC . . . . . . . . . . . . . . . . . . 470 mW

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 110°C/W

θ

JA

Operating Temperature Range

Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . +300°C

Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .>5 kV

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum
ratings for extended periods of time may affect device reliability.

REV. A –3–

ADM706P/R/S/T, ADM708R/S/T

PIN FUNCTION DESCRIPTIONS

Pin No. Pin No.

Mnemonic ADM706 ADM708 Function

MR 1 1 Manual Reset Input. When taken below 0.6 V a RESET is generated. MR can be

driven from TTL, CMOS logic or from a manual reset switch as it is internally

debounced. An internal 70 µA pull-up current holds the input high when floating.

V

CC

GND 3 3 0 V. Ground reference for all signals.
PFI 4 4 Power Fail Input. PFI is the noninverting input to the Power Fail Comparator.

PFO 5 5 Power Fail Output. PFO is the output from the Power Fail Comparator. It goes

WDI 6 N/A Watchdog Input. WDI is a three level input. If WDI remains either high or low

NC N/A 6 No Connect.
RESET 7 (R/S/T Only) 7 Logic Output. RESET goes low for 200 ms when triggered. It can be triggered

RESET 7 (P Only) 8 Logic Output. RESET is an active high output suitable for systems which use

WDO 8 N/A Logic Output. The Watchdog Output, WDO, goes low if the internal watchdog

2 2 Power Supply Input.

When PFI is less than 1.25 V, PFO goes low. If unused, PFI should be connected
to GND.

low when PFI is less than 1.25 V.

for longer than the watchdog timeout period, the watchdog output WDO goes
low. The timer resets with each transition at the WDI input. Either a high-to-low
or a low-to-high transition will clear the counter. The internal timer is also
cleared whenever reset is asserted. The Watchdog Timer is disabled when WDI is
left floating or connected to a three-state buffer.

either by V

being below the reset threshold or by a low signal on the manual

CC

reset (MR) input. RESET will remain low whenever V
threshold. It remains low for 200 ms after V

MR goes from low to high. A watchdog timeout will not trigger RESET unless
WDO is connected to MR.

active high RESET logic. It is the inverse of RESET.

timer times out as a result of inactivity on the WDI input. It remains low until
the watchdog timer is cleared. WDO also goes low during low line conditions.
Whenever V

is below the reset threshold, WDO remains low. As soon as V

CC

goes above the reset threshold, WDO goes high immediately.

is below the reset

CC

goes above the reset threshold or

CC

CC

MR

V

CC

GND

PFI

1
2

ADM706

3

TOP VIEW

4

(Not to Scale)

PIN CONFIGURATIONS

8

WDO

7

RESET

P

6

WDI

5

PFO

MR

V

GND

PFI

CC

1
2

ADM706

R/S/T

3

TOP VIEW

4

(Not to Scale)

8
7

6
5

WDO

RESET

WDI

PFO

1

MR

V

2

CC

3

GND

4

PFI

NC = NO CONNECT

ADM708

R/S/T

TOP VIEW

(Not to Scale)

8
7

6
5

RESET

RESET

NC

PFO

REV. A–4–

WATCHDOG

(

)

V

CC

RESET

MR

WDO

VRT VRT

t

RS

t

RS

MR EXTERNALLY
DRIVEN LOW

NOTE: RESET = COMPLEMENT OF RESET

INPUT (WDI)

MR

V

POWER FAIL

INPUT (PFI)

CC

WATCHDOG
TRANSITION

DETECTOR

V

CC

V

*

REF

1.25V

70mA

WATCHDOG

TIMER

RESET &

WATCHDOG

TIMEBASE

RESET

GENERATOR

ADM706

WATCHDOG
OUTPUT(WDO)

RESET,
(P = RESET)

POWER FAIL
OUTPUT (PFO)

ADM706P/R/S/T, ADM708R/S/T

Manual Reset

The manual reset input (MR) allows other reset sources such as
a manual reset switch to generate a processor reset. The input is
effectively debounced by the timeout period (200 ms typical).
The MR input is TTL/CMOS compatible so it may also be
driven by any logic reset output. If unused, the MR input may
be tied high or left floating.

*VOLTAGE REFERENCE = 2.63V

P/R), 2.93V (S), 3.08V (T

Figure 1. ADM706 Functional Block Diagram

V

CC

MR

70mA

RESET

GENERATOR

RESET

RESET

Watchdog Timer (ADM706)

The watchdog timer circuit may be used to monitor the activity

Figure 3.

RESET, MR

and

WDO

Timing

of the microprocessor in order to check that it is not stalled in

V

CC

V

*

POWER FAIL

INPUT (PFI)

REF

1.25V

*VOLTAGE REFERENCE = 2.63V (R), 2.93V (S), 3.08V (T)

ADM708

Figure 2. ADM708 Functional Block Diagram

POWER FAIL
OUTPUT (PFO)

an indefinite loop. An output line on the processor is used to
toggle the Watchdog Input (WDI) line. If this line is not toggled
within the timeout period (1.6 sec), the watchdog output
(WDO) is driven low. The WDO output may be connected to a
nonmaskable interrupt (NMI) on the processor. Therefore, if
the watchdog timer times out, an interrupt is generated. The in­terrupt service routine should then be used to rectify the
problem.

The watchdog timer is cleared by either a high-to-low or by a

CIRCUIT INFORMATION

Power Fail Reset

The reset output provides a reset (RESET or RESET) output
signal to the Microprocessor whenever the V

input is below

CC

the reset threshold. The actual reset threshold voltage is depen­dent on whether a P/R, S, or T suffix device is used. An internal
timer holds the reset output active for 200 ms after the voltage

rises above the threshold. This is intended as a power-on

on V

CC

reset signal for the microprocessor. It allows time for both the
power supply and the microprocessor to stabilize after power­up. If a power supply brownout or interruption occurs, the reset
line is similarly activated and remains active for 200 ms after the

low-to-high transition on WDI. Pulses as narrow as 50 ns are
detected. The timer is also cleared by RESET/RESET going
active. Therefore the watchdog timeout period begins after reset
goes inactive.

When V

falls below the reset threshold, WDO is forced low

CC

whether or not the watchdog timer has timed out. Normally
this would generate an interrupt but it is overridden by RESET/
RESET going active.

The watchdog monitor can be deactivated by floating the
Watchdog Input (WDI). The WDO output can now be used as
a low line output since it will only go low when V

falls below

CC

the reset threshold.

supply recovers. If another interruption occurs during an active
reset period, then the reset timeout period continues for an ad­ditional 200 ms.

The reset output is guaranteed to remain valid with V
as 1 V. This ensures that the microprocessor is held in a stable
shutdown condition as the power supply starts up.

The ADM706P provides an active high reset (RESET) signal;

as low

CC

the ADM706R/S/T provides an active low (RESET) signal;

WDI

WDO

RESET

t

WP

while the ADM708R/S/T provides both RESET and RESET.

t

WD

RESET EXTERNALLY
TRIGGERED BY MR

t

WD

Figure 4. Watchdog Timing

t

WD

t

RS

REV. A –5–

ADM706P/R/S/T, ADM708R/S/T

V

CC

RESET

400ms/DIV

V

CC

RESET

400ms/DIV

Power-Fail Comparator

The power-fail comparator is an independent comparator which
may be used to monitor the input power supply. The compara­tor’s inverting input is internally connected to a 1.25 V reference
voltage. The noninverting input is available at the PFI input.
This input may be used to monitor the input power supply via a
resistive divider network. When the voltage on the PFI input drops
below 1.25 V, the comparator output (PFO) goes low indicating
a power failure. For early warning of power failure the compara­tor may be used to monitor the preregulator input simply by
choosing an appropriate resistive divider network. The PFO output
can be used to interrupt the processor so that a shutdown proce­dure is implemented before the power is lost.

INPUT

POWER

R2

R1

POWER-FAIL

INPUT

1.25V

PFI

PFO

ADM70x

POWER-FAIL
OUTPUT

Figure 5. Power-Fail Comparator

Adding Hysteresis to the Power-Fail Comparator

For increased noise immunity, hysteresis may be added to the
power-fail comparator. Since the comparator circuit is nonin­verting, hysteresis can be added simply by connecting a resistor
between the PFO output and the PFI input as shown in Figure

6. When PFO is low, resistor R3 sinks current from the sum­ming junction at the PFI pin. When PFO is high, resistor R3
sources current into the PFI summing junction. This results in
differing trip levels for the comparator. Further noise immunity
may be achieved by connecting a capacitor between PFI and GND.

1. 2 5

V

=1. 2 5 + R1

L






V

1. 2 5

MID

Valid RESET Below 1 V V

CC

R2






R1 + R2

–1.25

V

CC

–

R2

R 3











The ADM70x family of products are guaranteed to provide a
valid reset level with V
cal Performance Characteristics. As V

as low as 1 V. Please refer to the Typi-

CC

drops below 1 V, the

CC

internal transistor will not have sufficient drive to hold it ON so
the voltage on RESET will no longer be held at 0 V. A pull­down resistor as shown in Figure 7 may be connected externally
to hold the line low if it is required.

ADM70x

RESET

R1

GND

Figure 7.

RESET

Valid Below 1 V

Typical Performance Characteristics

+3.3V

V

CC

1.25V

PFI

ADM70x

R3

0V

0V

V

V

L

H

V

IN

INPUT

POWER

ADM663A

R1

R2

3.3V

PFO

Figure 6. Adding Hysteresis to the Power-Fail
Comparator





V

H

= 1.25 1 +






R2 + R 3




R2 × R 3






PFO

R1

TO mP NMI








Figure 8. ADM706/ADM708

RESET

Output Voltage vs.

Supply Voltage

Figure 9. RESET Output Voltage vs. Supply Voltage

REV. A–6–

1.3V

ADM706

RESET

GND

mP

MR

PFI

WDI

PFO

RESET

V

CC

+3.3V

WDO

V

CC

UNREGULATED

DC

I/O LINE

INTERRUPT

NMI

MANUAL

RESET

GND

GND

IN

OUT

ADM666A

+3V

0V

0V

+3V

100ns/DIV

V

CC

= V

RT

TA = +258C

RESET

RESET

+2V

0V

V

CC

RESET

2ms/DIV

TA = +258C

+3V

+3V

PFI

+3V

500ns/DIV

V

= +5V

CC

TA = +258C

ADM706P/R/S/T, ADM708R/S/T

+1.2V

PFO

0V

Figure 10. PFI Assertion Response Time

V

= +5V

CC

TA = +258C

1.2V

PFO

0V

500ns/DIV

Figure 11. PFI Deassertion Response Time

V

= V

CC

RT

TA = +258C

+3V

RESET

RESET

+1.3V
PFI

+3V

+3V

0V0V

Figure 13.

Figure 14. ADM706/ADM708

RESET

, RESET Deassertion

RESET

Response Time

APPLICATIONS

A typical operating Circuit is shown in Figure 15. The unregu­lated dc input supply is monitored using the PFI input via the
resistive divider network. Resistors R1 and R2 should be selected
such that when the supply voltage drops below the desired level
(e.g., 5 V) the voltage on PFI drops below the 1.25 V threshold

thereby generating an interrupt to the µP. Monitoring the

preregulator input gives additional time to execute an orderly
shutdown procedure before power is lost.

100ns/DIV

Figure 12.

REV. A –7–

RESET

, RESET Assertion

Figure 15. Typical Application Circuit

ADM706P/R/S/T, ADM708R/S/T

ADM706

RESET

GND

mP

MR

PFI

WDI

PFO

RESET

V

CC

R1

R2

V

X

+3V/+3.3V

ADM70x

RESET

GND

mP

RESET

GND

BUFFERED

RESET

+3V/+3.3V

V

CC

Microprocessor activity is monitored using the WDI input. This
is driven using an output line from the processor. The software
routines should toggle this line at least once every 1.6 seconds.
If a problem occurs and this line is not toggled, then WDO goes
low and a nonmaskable interrupt is generated. This interrupt
routine may be used to clear the problem.

If, in the event of inactivity on the WDI line, a system reset is
required, then the WDO output should be connected to the
input as shown in Figure 16.

RESET

ADM706

PFI

MR

Figure 16.

WDI

WDO

GND

RESET

Monitoring Additional Supply Levels

It is possible to use the power-fail comparator to monitor a
second supply as shown in Figure 17. The two sensing resistors
R1 and R2 are selected such that the voltage on PFI drops below

1.25 V at the minimum acceptable input supply. The PFO output
may be connected to the MR input so that a RESET is gener­ated when the supply drops out of tolerance. In this case if
either supply drops out of tolerance, a RESET will be generated.

RESET

mP

I/O LINE

from WDO

Figure 17. Monitoring 3 V/3.3 V and an Additional
Supply, V

X

␮Ps with Bidirectional RESET

In order to prevent contention for microprocessors with a bidi­rectional reset line, a current limiting resistor should be inserted

between the ADM70x RESET output pin and the µP reset pin.

This will limit the current to a safe level if there are conflicting

output reset levels. A suitable resistor value is 4.7 kΩ. If the re-

set output is required for other uses, then it should be buffered
as shown in Figure 18.

Figure 18. Bidirectional I-O RESET

C1998a–0–12/99

PIN 1

0.210

(5.33)

MAX

0.160 (4.06)

0.115 (2.93)

0.022 (0.558)

0.014 (0.356)

8-Lead Plastic DIP

0.430 (10.92)

0.348 (8.84)

8

0.100 (2.54)

5

0.280 (7.11)

0.070 (1.77)

0.045 (1.15)

0.240 (6.10)

0.060 (1.52)

0.015 (0.38)

14

BSC

(N-8)

0.130
(3.30)
MIN

SEATING
PLANE

0.325 (8.25)

0.300 (7.62)

0.015 (0.381)

0.008 (0.204)

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.195 ( 4.95)

0.115 (2.93)

0.0098 (0.25)

0.0040 (0.10)
SEATING

PLANE

8-Lead SOIC

0.1 968 (5.00)

0.1 890 (4.80)

85

0.0500 (1.27)

0.2440 (6.20)

0.2284 (5.80)

41

BSC

0.0192 (0.49)

0.0138 (0.35)

(SO-8)

0.0688 (1.75)

0.0532 (1.35)

0.0098 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

88

0.0500 (1.27)

08

0.0160 (0.41)

3 458

PRINTED IN U.S.A.

REV. A–8–