ANALOG DEVICES ADM6820 Service Manual

V

V

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FET Drive Simple Sequencers

®

FEATURES

Single chip enables power supply sequencing of two

supplies
On-board charge pump fully enhances N-channel FET
Adjustable primary supply monitor to 0.618 V
Delay from primary supply to secondary supply enabled

Fixed 300 ms delay (ADM6819)

Capacitor adjustable delay (ADM6820)
Logic/analog driven enable input (ADM6819)

−40°C to +85°C operating range
Packaged in small 6-lead SOT-23 package
Pin-to-pin compatibility with MAX6819/MAX6820

APPLICATIONS

Multivoltage systems
Dual voltage microprocessors/FPGAs/ASICs/DSPs
Network processors
Telecom and datacom systems
PC/server applications

ADM6819/ADM6820

FUNCTIONAL BLOCK DIAGRAM

CC1

V

CC2

R1

SETV

R2

V

CC1

UVLO

0.618V

ADM6819/

ADM6820

GND

V

CC2

CHARGE

PUMP

LOGIC

0.618V

EN (ADM6819) - DIGITAL/ANALOG

SETD (ADM6820)

Figure 1.

V

DRIVER

TIMER

FET

FET

Q1

GATE

CC1

V

OUT

CC2

5133-001

GENERAL DESCRIPTION

The ADM6819 and ADM6820 are simple power supply sequencers
with FET drive capability for enhancing N-channel MOSFETs.
These devices can monitor a primary supply voltage and
enable/disable an external N-channel FET for a secondary
supply. The ADM6819 has the ability to monitor two supplies.
When more than two voltages require sequencing, multiple
ADM6819/ADM6820 devices can be cascaded to achieve this.
The devices operate over a supply range of 2.95 V to 5.5 V.

An internal comparator monitors the primary supply using the
V

SET pin. The input to this comparator is externally set via a
resistor divider from the primary supply. When the voltage at
the VSET pin rises above the comparator threshold, an internal
charge pump on the GATE output enhances the secondary
supply FET.

The ADM6819 features an enable (EN) pin that is fed to the
i

nput of an additional comparator and reference circuit. This
pin can be used as a digital enable or a secondary power good
comparator to monitor a second supply and enables the GATE
only if both supplies are valid. When both inputs of the internal
comparators are above the threshold, a fixed 300 ms timeout
occurs before the GATE is driven high and the secondary
supply is enabled.

The ADM6820 has only one comparator that is on the SETV
p

in. It also features a timeout period that is adjustable via a

single external capacitor on the SETD pin.

The ADM6819/ADM6820 are packaged in small 6-lead SOT-23

ckages.

pa

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADM6819/ADM6820

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TABLE OF CONTENTS

Features.............................................................................................. 1

Pin Configuration and Function Descriptions..............................7

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Diagrams.............................................................................. 4

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

REVISION HISTORY

7/06—Rev. 0: Initial Version

Typical Performance Characteristics..............................................8

Theory of Operation ...................................................................... 10

SETV Pin ..................................................................................... 10

EN Pin.......................................................................................... 10

GATE Pin .................................................................................... 10

SETD Pin..................................................................................... 10

Outline Dimensions....................................................................... 11

Ordering Guide .......................................................................... 11

Rev. 0 | Page 2 of 12

ADM6819/ADM6820

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SPECIFICATIONS

V

or V

CC1

= 2.95 V to 5.5 V, TA = −40°C to +85°C, unless otherwise noted. Typical values are at TA = 25°C.

CC2

Table 1.

Parameter Min Typ Max Units Conditions

V

, V

PINS V

CC1

CC2

Operating Voltage Range, V
V

or V

CC1

V

CC1

V

CC1

Supply Current, ICC 350 500 μA V

CC2

or V

Disable Mode Current 250 μA V

or V

CC2

Slew Rate

CC2

2

1.2/t
Undervoltage Lockout, V

UVLO

CC1

or V

0.9 5.5 V V

CC2

6 V/s ADM6819

V/s ADM6820

DELAY

2.4 2.525 2.65 V VCC falling

CC1

CC1

CC1

CC1

or V

CC2

or V

CC2

= V

= 3.3 V

CC2

= V

= 3.3 V, EN = GND

CC2

SETV PIN

SETV Threshold, VTH 0.602 0.618 0.634 V V
SETV Input Current
SETV Threshold Hysteresis
SETV to GATE Delay, t

2

240 300 350 ms V

DELAY

10 100 nA

−1 % V

rising, enables GATE

SETV

falling, disables GATE

SETV

> V

SETV

TH

SETD PIN ADM6820

SETD Ramp Current, I

SETD

300 500 730 nA
400 500 600 nA TA = 25°C
SETD Voltage, V

1.295 1.326 1.357 V

SETD

GATE PIN

GATE Turn-On Time, tON 0.5 1.5 10 ms C
GATE Turn-Off Time, t
GATE Voltage, V

GATE

30 μs C

OFF

4.5 5.5 6.0 V With respect to V

= 1500 pF, V

GATE

= 1500 pF, V

GATE

4.0 5.0 6 V With respect to V

8.9 9.4 9.9 V With respect to V

8.2 8.6 9.1 V With respect to V
ENABLE PIN

EN Input Voltage Low, VIL 0.4 V V
EN Input Voltage High, VIH 2.0 V V

1

100% production tested at TA = +25°C. Specifications over temperature limit are guaranteed by design.

2

Guaranteed by design, not production tested.

3

t

(s) = 2.65 × 106 × C

DELAY

4

Highest supply pin is represented by V

5

Highest supply pin is represented by V

.

SET

= 2.95 V.

CCx

= 5.5 V.

CCx

CC1

CC1

or V
or V

CC2

CC2

1

must be > 2.95 V
must be > 2.95 V

3

; VEN > VTH (ADM6819)

= 3.3 V, V

CC2

= 3.3 V, V

CC2

, R

CCx

, R

CCx

, R

CCx

, R

CCx

GATE

GATE

> 50 MΩ to V

GATE

> 5 MΩ to V

GATE

> 50 MΩ to V

GATE

> 5 MΩ to V

GATE

must be > 2.95 V
must be > 2.95 V

= 7.8 V
= 0.5 V

CCx

CCx

CCx

CCx

4

4

5

5

Rev. 0 | Page 3 of 12

ADM6819/ADM6820

V

V

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TIMING DIAGRAMS

V

CC2

CC1

Q1

V

CC1

V

CC2

CC1

V

OUT

CC2

CHARGE

PUMP

UVLO

R1

R3

R4

SETV

R2

0.618V

ADM6819

GND

LOGIC

0.618V

EN

V

FET

FET

DRIVER

GATE

05133-014

Figure 2. ADM6819 Solution for Validating Two Supplies Before Sequencing

V

SETV

V

GATE

Figure 3. ADM6819/ADM6820 Timing Diagram Using SETV for Sequencing

0.618V

t

DELAY

(ADM6819 = 300ms,

ADM6820 = ADJ)

t

ON

90%

10% 10%

V

CC2

+ 5.5V (typ)

t

OFF

05133-015

V

V

SETV

V

GATE

0.618V

EN

0.618V

t

DELAY

(300ms)

t

ON

90%

10% 10%

V

CC2

+ 5.5V (typ)

t

Figure 4. ADM6819 Timing Diagram Using EN and SETV for Sequencing

OFF

5133-016

Rev. 0 | Page 4 of 12