Analog Devices ADM488, ADM489 Datasheet
Full-Duplex, Low Power,
a
FEATURES
Meets EIA RS-485 Standard
250 kbps Data Rate
Single +5 V 6 10% Supply
–7 V to +12 V Bus Common-Mode Range
12 kV Input Impedance
2 kV EFT Protection Meets IEC1000-4-4
High EM Immunity Meets IEC1000-4-3
Reduced Slew Rate for Low EM Interference
Short Circuit Protection
Excellent Noise Immunity
30 mA Supply Current
APPLICATIONS
Low Power RS-485 Systems
DTE-DCE Interface
Packet Switching
Local Area Networks
Data Concentration
Data Multiplexers
Integrated Services Digital Network (ISDN)
Slew Rate Limited, EIA RS-485 Transceivers
ADM488/ADM489
FUNCTIONAL BLOCK DIAGRAMS
ADM488
RO
RO
RE
DE
R
DI
DI
D
ADM489
R
D
A
B
Z
Y
A
B
Z
Y
GENERAL DESCRIPTION
The ADM488 and ADM489 are low power differential line
transceiver suitable for communication on multipoint bus transmission lines.
They are intended for balanced data transmission and comply
with both EIA Standards RS-485 and RS-422. Both products
contains a single differential line driver and a single differential
line receiver making them suitable for full duplex data transfer.
The ADM489 contains an additional receiver and driver enable
control.
The input impedance is 12 kΩ, allowing 32 transceivers to be
connected on the bus.
The ADM488/ADM489 operates from a single +5 V ± 10%
power supply. Excessive power dissipation caused by bus contention or by output shorting is prevented by a thermal shutdown circuit. This feature forces the driver output into a high
impedance state if during fault conditions a significant temperature increase is detected in the internal driver circuitry.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM488/ADM489 is fabricated on BiCMOS, an advanced mixed technology process combining low power CMOS
with fast switching bipolar technology.
The ADM488/ADM489 is fully specified over the industrial
temperature range and is available in DIP, SOIC and TSSOP
packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703 © Analog Devices, Inc., 1997
ADM488/ADM489–SPECIFICA TIONS
(VCC = +5 V 6 10%. All specifications T
otherwise noted)
MIN
to T
MAX
unless
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Differential Output Voltage, V
OD
2.0 5.0 V V
5.0 V R = ∞, Figure 1
= 5 V, R = 50 Ω (RS-422), Figure 1
CC
1.5 5.0 V R = 27 Ω (RS-485), Figure 1
1.5 5.0 V V
∆|V
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 1
OD
Common-Mode Output Voltage V
| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω
∆|V
OC
Output Short Circuit Current (V
Output Short Circuit Current (V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
OC
= High) 250 mA –7 V ≤ VO ≤ +12 V
OUT
= Low) 250 mA –7 V ≤ VO ≤ +12 V
OUT
INL
INH
2.0 1.4 V
3 V R = 27 Ω or 50 Ω, Figure 1
1.4 0.8 V
= –7 V to +12 V, Figure 2, VCC = 5 V ± 5%
TST
Logic Input Current (DE, DI) ±1.0 µA
RECEIVER
Differential Input Threshold Voltage, V
Input Voltage Hysteresis, ∆V
TH
TH
Input Resistance 12 kΩ –7 V ≤ V
Input Current (A, B) +1 mA V
–0.2 +0.2 V –7 V ≤ VCM ≤ +12 V
70 mV VCM = 0 V
≤ +12 V
CM
= 12 V
IN
–0.8 mA V
= –7 V
IN
Logic Enable Input Current (RE) ±1 µA
CMOS Output Voltage Low, V
CMOS Output Voltage High, V
OL
OH
4.0 V I
Short Circuit Output Current 7 85 mA V
Three-State Output Leakage Current ±1.0 µA 0.4 V ≤ V
0.4 V I
= +4.0 mA
OUT
= –4.0 mA
OUT
= GND or V
OUT
≤ +2.4 V
OUT
CC
POWER SUPPLY CURRENT Outputs Unloaded, Receivers Enabled
I
CC
30 60 µA DE = 0 V (Disabled)
37 74 µA DE = 5 V (Enabled)
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(VCC = +5 V 6 10%. All specifications T
MIN
to T
unless otherwise noted)
MAX
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Propagation Delay Input to Output T
Driver O/P to O/P T
Driver Rise/Fall Time T
SKEW
R
, T
F
PLH
, T
Driver Enable to Output Valid 250 2000 ns R
Driver Disable Timing 300 3000 ns R
250 2000 ns RL Diff = 54 Ω, CL1 = CL2 = 100 pF, Figure 5
PHL
100 800 ns RL Diff = 54 Ω, CL1 = CL2 = 100 pF, Figure 5
250 2000 ns RL Diff = 54 Ω, CL1 = CL2 = 100 pF, Figure 5
= 500 Ω, CL = 100 pF, Figure 2
L
= 500 Ω, CL = 15 pF, Figure 2
L
Data Rate 250 kbps
RECEIVER
Propagation Delay Input to Output T
Skew |T
PLH–TPHL
Receiver Enable T
Receiver Disable T
| 100 ns
EN1
EN2
PLH
, T
250 2000 ns CL = 15 pF, Figure 5
PHL
10 50 ns RL = 1 kΩ, CL = 15 pF, Figure 4
10 50 ns RL = 1 kΩ, CL = 15 pF, Figure 4
Data Rate 250 kbps
Specifications subject to change without notice.
–2–
REV. 0
ADM488/ADM489
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Inputs
Driver Input (DI) . . . . . . . . . . . . . . . –0.3 V to V
Control Inputs (DE, RE) . . . . . . . . . –0.3 V to V
+ 0.3 V
CC
+ 0.3 V
CC
Receiver Inputs (A, B) . . . . . . . . . . . . . . . . –14 V to +14 V
Outputs
Driver Outputs . . . . . . . . . . . . . . . . . . . . . –14 V to +12.5 V
Receiver Output . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Power Dissipation 8-Lead DIP . . . . . . . . . . . . . . . . . 700 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . 120°C/W
JA
Power Dissipation 8-Lead SOIC . . . . . . . . . . . . . . . . 520 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . 110°C/W
JA
Power Dissipation 14-Lead DIP . . . . . . . . . . . . . . . . 800 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . 140°C/W
JA
Power Dissipation 16-Lead TSSOP . . . . . . . . . . . . . . 800 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . 150°C/W
JA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +300°C
Vapor Phase (60 secs) . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 secs) . . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
ESD Rating, MIL-STD-883B . . . . . . . . . . . . . . . . . . . . . 4 kV
EFT Rating, IEC1000-4-4 . . . . . . . . . . . . . . . . . . . . . . . 2 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.
Power Dissipation 14-Lead SOIC . . . . . . . . . . . . . . . 800 mW
θ
, Thermal Impedance . . . . . . . . . . . . . . . . . . . 120°C/W
JA
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADM488AR –40°C to +85°C 8-Lead Narrow Body (SOIC) SO-8
ADM488AN –40°C to +85°C 8-Lead Plastic DIP N-8
ADM489AN –40°C to +85°C 14-Lead Plastic DIP (Narrow) N-14
ADM489AR –40°C to +85°C 14-Lead Narrow Body (SOIC) R-14
ADM489ARU –40°C to +85°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16
–3–REV. 0
ADM488/ADM489
ADM488 PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Function
1V
CC
Power Supply, 5 V ± 10%.
2 RO Receiver Output. When A > B by 200 mV,
RO = high. If A < B by 200 mV, RO = low.
3 DI Driver Input. A logic Low on DI forces Y low
and Z high while a logic High on DI forces Y
high and Z low.
4 GND Ground Connection, 0 V
5 Y Noninverting Driver, Output Y
6 Z Inverting Driver, Output Z
7 B Inverting Receiver Input B
8 A Noninverting Receiver Input A
ADM489 PIN FUNCTION DESCRIPTIONS
DIP/SOIC TSSOP
Pin Pin Mnemonic Function
1, 8, 13 2, 9, 10, NC No Connect. No connections
13, 16 are required to this pin.
2 3 RO Receiver Output. When
enabled if A > B by 200 mV
then RO = high. If A < B by
200 mV then RO = low.
34RE Receiver Output Enable. A
low level enables the receiver
output, RO. A high level
places it in a high impedance
state.
4 5 DE Driver Output Enable. A
high level enables the driver
differential outputs, Y and Z.
A low level places it in a high
impedance state.
5 6 DI Driver Input. When the
driver is enabled, a logic Low
on DI forces Y low and Z
high, while a logic High on
DI forces Y high and Z low.
6, 7 7, 8 GND Ground Connection, 0 V
9 11 Y Noninverting Driver
Output Y
10 12 Z Inverting Driver Output Z
11 14 B Inverting Receiver Input B
12 15 A Noninverting Receiver
Input A
14 1 V
CC
Power Supply, 5 V ± 10%.
PIN CONFIGURATIONS
8-Lead DIP/SO
V
RO
GND
CC
DI
1
ADM488
2
TOP VIEW
(Not to Scale)
3
4
8
A
7
B
6
Z
5
Y
14-Lead DIP/SO
1
NC
2
RO
3
RE
DE
4
(Not to Scale)
DI
5
6
GND
GND
7
NC = NO CONNECT
ADM489
TOP VIEW
14
V
CC
13
NC
12
A
11
B
Z
10
Y
9
NC
8
16-Lead TSSOP
1
V
CC
2
NC
3
RO
4
RE
5
(Not to Scale)
6
DI
7
GND
8
GND
NC = NO CONNECT
ADM489
TOP VIEW
16
NC
15
A
14
B
13
NC
ZDE
12
Y
11
NC
10
NC
9
–4–
REV. 0
Loading...