ANALOG DEVICES ADM487E Service Manual
5 V, ±15 kV ESD Protected
V
www.BDTIC.com/ADI
Half-Duplex, RS-485/RS-422 Transceivers
FEATURES
TIA/EIA RS-485/RS-422 compliant
ESD protection on RS-485 I/O pins
±15 kV human body model (HBM)
Data rates
ADM487E: 250 kbps
ADM485E/ADM1487E: 2.5 Mbps
Half-duplex
Reduced slew rates for low EMI
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
8-lead SOIC packages
APPLICATIONS
Energy/power metering
Lighting systems
Industrial control
Telecommunications
Security systems
Instrumentation
GENERAL DESCRIPTION
The ADM485E/ADM487E/ADM1487E are 5 V, low power
data transceivers with ±15 kV ESD protection suitable for halfduplex communication on multipoint bus transmission lines.
They are designed for balanced data transmission and comply
with Telecommunication Industry Association/Electronics
Industries Association (TIA/EIA) standards RS-485 and RS-422.
The ADM487E and ADM1487E have a 1/4 unit load receiver
input impedance that allows up to 128 transceivers on a bus,
whereas the ADM485E allows up to 32 transceivers on a bus.
Because only one driver is enabled at any time, the output of a
disabled or power-down driver is three-stated to avoid overloading
the bus.
ADM485E/ADM487E/ADM1487E
FUNCTIONAL BLOCK DIAGRAM
CC
ADM485E/
ADM487E/
ADM1487E
RO
RE
DE
DI
The driver outputs are slew rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or output
shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the industrial temperature
ranges and are available in 8-lead SOIC packages.
R
D
GND
Figure 1.
A
B
06356-001
Table 1. Selection Table
Guaranteed
Part
Number
ADM485E Half 2.5 No No Yes 300 32 8
ADM487E Half 0.25 Yes Yes Yes 120 128 8
ADM1487E Half 2.5 No No Yes 230 128 8
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Half-/FullDuplex
Data Rate
(Mbps)
Slew Rate
Limited
Low Power
Shutdown
Driver/Receiver
Enable
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2007–2008 Analog Devices, Inc. All rights reserved.
Quiescent
Current (μA)
Number of
Nodes on Bus
Pin
Count
ADM485E/ADM487E/ADM1487E
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
REVISION HISTORY
3/08—Rev. 0 to Rev. A
Changes to Supply Voltage Range .................................... Universal
Added Endnote 1 .............................................................................. 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 5
Changes to Figure 12 ........................................................................ 9
Changes to Figure 27 and Table 9 ................................................. 14
Changes to Figure 29 ...................................................................... 15
Updated Outline Dimensions ....................................................... 16
1/07—Revision 0: Initial Version
Typical Performance Characteristics ..............................................8
Test Circuits and Switching Characteristics ................................ 11
Theory of Operation ...................................................................... 13
Circuit Description .................................................................... 13
Applications Information .............................................................. 15
Differential Data Transmission ................................................ 15
Cable and Data Rate ................................................................... 15
Outline Dimensions ....................................................................... 16
Ordering Guide .......................................................................... 16
Rev. A | Page 2 of 16
ADM485E/ADM487E/ADM1487E
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SPECIFICATIONS
VCC = 5 V ± 10%, TA = T
Table 2. ADM485E/ADM487E/ADM1487E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage (No Load) V
Differential Output Voltage (with Load) V
Δ |VOD| for Complementary Output States 0.2 V RL = 27 Ω or 50 Ω (see Figure 18)
Common-Mode Output Voltage VOC 3 V RL = 27 Ω or 50 Ω (see Figure 18)
Δ |VOC| for Complementary Output States 0.2 V RL = 27 Ω or 50 Ω (see Figure 18)
Logic Inputs
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Logic Input Current1 I
RECEIVER
Input Current (A, B) I
Differential Inputs
Differential Input Threshold Voltage VTH −0.2 +0.2 V −7 V < V
Input Hysteresis ΔVTH 70 mV VCM = 0 V
Receiver Output Logic
Output Voltage High VOH 3.5 V I
Output Voltage Low VOL 0.4 V I
Three-State Output Leakage Current I
Receiver Input Resistance RIN 12 kΩ −7 V < VCM < +12 V (ADM485E)
POWER SUPPLY
No Load Supply Current ICC 500 900 μA
Supply Current in Shutdown I
Driver Short-Circuit Current, VO High I
Driver Short-Circuit Current, VO Low I
Receiver Short-Circuit Current I
ESD PROTECTION
A, B ±15 kV Human body model
1
Supply voltage is 5 V ± 5%.
MIN
to T
, unless otherwise noted.
MAX
OD1
OD2
1.5 5 V RL = 27 Ω (RS-485) (see Figure 18)
±2 μA
IN1
1.0 mA DE = 0 V, VIN = 12 V
IN2
−0.8 mA VCC = 0 V or 5.25 V, VIN = −7 V (ADM485E)
0.25 mA DE = 0 V, VIN = 12 V
−0.2 mA
±1 μA 0.4 V < VO < 2.4 V
OZR
48 kΩ −7 V < VCM < +12 V (ADM487E/ADM1487E)
300 500 μA
300 500 μA
230 400 μA
250 400 μA
120 250 μA
SHDN
OSD1
OSD2
7 95 mA 0 V ≤ VO ≤ VCC
OSR
5 V
2 V RL = 50 Ω (RS-422)
DE, DI, RE
DE, DI, RE
DE, DI, RE
V
CC
= 0 V or 5.25 V, VIN = −7 V
(ADM487E/ADM1487E)
< +12 V
CM
= −4 mA, VID = +200 mV
OUT
= +4 mA, VID = −200 mV
OUT
= 0 V or VCC, DE = VCC (ADM485E)
RE
= 0 V or VCC, DE = 0 V (ADM485E)
RE
= 0 V or VCC, DE = VCC (ADM1487E)
RE
= 0 V or VCC, DE = 0 V (ADM1487E)
RE
= 0 V or VCC, DE = VCC (ADM487E)
RE
= 0 V, DE = 0 V (ADM487E)
RE
0.5 10 μA
DE = 0 V, RE
= VCC (ADM487E)
35 250 mA −7 V ≤ VO ≤ +12 V, applies to peak current
35 250 mA −7 V ≤ VO ≤ +12 V, applies to peak current
Rev. A | Page 3 of 16
ADM485E/ADM487E/ADM1487E
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TIMING SPECIFICATIONS
VCC = 5 V ± 10%, TA = T
Table 3. ADM485E/ADM1487E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Driver Propagation Delay Input to Output, Low to High t
Driver Propagation Delay Input to Output, High to Low
Output Skew to Output t
Rise/Fall Time tDR, tDF 3 20 40 ns R
Enable Time to High Level t
Enable Time to Low Level t
Disable Time from Low Level t
Disable Time from High Level t
RECEIVER
Receiver Propagation Delay Input to Output, Low to High t
Receiver Propagation Delay Input to Output, High to Low t
|t
− t
| Differential Receiver Skew t
PLH
PHL
Enable Time to Low Level t
Enable Time to High Level t
Disable Time from Low Level t
Disable Time from High Level t
MAXIMUM DATA RATE f
MIN
to T
, unless otherwise noted.
MAX
10 40 60 ns R
DPLH
t
10 40 60 ns R
DPHL
5 10 ns R
SKEW
45 70 ns
DZH
45 70 ns
DZL
45 70 ns
DLZ
45 70 ns
DHZ
20 60 200 ns
RPLH
20 60 200 ns
RPHL
5 ns
SKEW
25 50 ns
RZL
20 50 ns
RZH
20 50 ns
RLZ
20 50 ns t
RHZ
2.5 Mbps
MAX
= 54 Ω, CL1 = CL2 = 100 pF
DIFF
(see
Figure 19 and Figure 20)
= 54 Ω, CL1 = CL2 = 100 pF
DIFF
(see
Figure 19 and Figure 20)
= 54 Ω, CL1 = CL2 = 100 pF
DIFF
(see
Figure 19 and Figure 20)
= 54 Ω, CL1 = CL2 = 100 pF
DIFF
(see
Figure 19 and Figure 20)
C
= 100 pF, S1 closed (see Figure 21)
L
C
= 100 pF, S1 closed (see Figure 22)
L
C
= 15 pF, S1 closed (see Figure 22)
L
C
= 15 pF, S1 closed (see Figure 21)
L
See
Figure 23 and Figure 24
See
Figure 23 and Figure 24
See
Figure 23 and Figure 24
C
= 15 pF, S2 closed (see Figure 25)
L
C
= 15 pF, S1 closed (see Figure 25)
L
C
= 15 pF, S2 closed (see Figure 25)
L
, t
< 50% of data period
PLH
PHL
Rev. A | Page 4 of 16
ADM485E/ADM487E/ADM1487E
www.BDTIC.com/ADI
VCC = 5 V ± 10%, TA = T
Table 4. ADM487E
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Driver Propagation Delay Input to Output, Low to High t
Driver Propagation Delay Input to Output, High to Low
Output Skew to Output t
Rise/Fall Time tDR, tDF 250 2000 ns R
Enable Time to High Level t
Enable Time to Low Level t
Disable Time from Low Level t
Disable Time from High Level t
RECEIVER
Receiver Propagation Delay Input to Output, Low to High t
Receiver Propagation Delay Input to Output, High to Low t
|t
− t
| Differential Receiver Skew t
PLH
PHL
Enable Time to Low Level t
Enable Time to High Level t
Disable Time from Low Level t
Disable Time from High Level t
Maximum Data Rate f
Time to Shutdown1 t
Driver Enable from Shutdown to Output High t
Driver Enable from Shutdown to Output Low t
Receiver Enable from Shutdown to Output High t
Receiver Enable from Shutdown to Output Low t
1
The ADM487E is put into shutdown mode by bringing RE high and DE low. If the inputs are in this state for less than 50 ns, the parts are guaranteed not to enter
shutdown. If the inputs are in this state for at least 600 ns, the ADM487E is guaranteed to enter shutdown.
MIN
to T
, unless otherwise noted.
MAX
250 800 2000 ns R
DPLH
t
250 800 2000 ns R
DPHL
250 20 800 ns R
SKEW
250 2000 ns
DZH
2000 ns
DZL
300 3000 ns
DLZ
300 3000 ns
DHZ
250 2000 ns
RPLH
250 2000 ns
RPHL
100 ns
SKEW
25 50 ns
RZL
25 50 ns
RZH
25 50 ns
RLZ
25 50 ns t
RHZ
250 kbps
MAX
50 200 600 ns
SHDN
5000 ns
DZH(SHDN)
5000 ns
DZL(SHDN)
5000 ns
RZH(SHDN)
5000 ns
RZL(SHDN)
= 54 Ω, CL1 = CL2 = 100 pF
DIFF
(see
Figure 19 and Figure 20)
= 54 Ω, CL1 = CL2 = 100 pF
DIFF
(see
Figure 19 and Figure 20)
= 54 Ω, CL1 = CL2 = 100 pF
DIFF
(see
Figure 19 and Figure 20)
= 54 Ω, CL1 = CL2 = 100 pF
DIFF
(see
Figure 19 and Figure 20)
C
= 100 pF, S1 closed (see Figure 21)
L
C
= 100 pF, S1 closed (see Figure 22)
L
C
= 15 pF, S1 closed (see Figure 22)
L
C
= 15 pF, S1 closed (see Figure 21)
L
See
Figure 23 and Figure 24
See
Figure 23 and Figure 24
See
Figure 23 and Figure 24
C
= 15 pF, S2 closed (see Figure 25)
L
C
= 15 pF, S1 closed (see Figure 25)
L
C
= 15 pF, S2 closed (see Figure 25)
L
, t
< 50% of data period
PLH
PHL
C
= 100 pF, S1 closed (see Figure 21)
L
C
= 100 pF, S1 closed (see Figure 22)
L
C
= 15 pF, S2 closed (see Figure 25)
L
C
= 15 pF, S1 closed (see Figure 25)
L
Rev. A | Page 5 of 16
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