Analog Devices ADM485 e Datasheet

5 V Low Power

a

FEATURES
Meets EIA RS-485 Standard
5 Mbps Data Rate
Single 5 V Supply
–7 V to +12 V Bus Common-Mode Range
High Speed, Low Power BiCMOS
Thermal Shutdown Protection
Short-Circuit Protection
Driver Propagation Delay: 10 ns
Receiver Propagation Delay: 15 ns
High Z Outputs with Power Off
Superior Upgrade for LTC485

APPLICATIONS
Low Power RS-485 Systems
DTE-DCE Interface
Packet Switching
Local Area Networks
Data Concentration
Data Multiplexers
Integrated Services Digital Network (ISDN)

EIA RS-485 Transceiver

ADM485

FUNCTIONAL BLOCK DIAGRAM

ADM485

RO

RE

DE

R

DI

D

V

CC

B

A

GND

GENERAL DESCRIPTION

The ADM485 is a differential line transceiver suitable for high
speed bidirectional data communication on multipoint bus trans­mission lines. It is designed for balanced data transmission and
complies with EIA Standards RS-485 and RS-422. The part
contains a differential line driver and a differential line receiver.
Both the driver and the receiver may be enabled independently.
When disabled, the outputs are three-stated.

The ADM485 operates from a single 5 V power supply. Excessive
power dissipation caused by bus contention or by output shorting
is prevented by a thermal shutdown circuit. This feature forces
the driver output into a high impedance state if during fault condi­tions a significant temperature increase is detected in the internal
driver circuitry.

Up to 32 transceivers may be connected simultaneously on a bus,
but only one driver should be enabled at any time. It is important,
therefore, that the remaining disabled drivers do not load the bus.
To ensure this, the ADM485 driver features high output imped­ance when disabled and when powered down.

This minimizes the loading effect when the transceiver is not being
used. The high impedance driver output is maintained over the
entire common-mode voltage range from –7 V to +12 V.

The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).

The ADM485 is fabricated on BiCMOS, an advanced mixed
technology process combining low power CMOS with fast switching
bipolar technology. All inputs and outputs contain protection
against ESD; all driver outputs feature high source and sink current
capability. An epitaxial layer is used to guard against latch-up.

The ADM485 features extremely fast switching speeds. Minimal
driver propagation delays permit transmission at data rates up to
5 Mbps while low skew minimizes EMI interference.

The part is fully specified over the commercial and industrial
temperature range and is available in PDIP, SOIC, and small
footprint MSOP packages.

REV. E

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Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

ADM485–SPECIFICATIONS

(VCC = 5 V ⴞ 5%. All specifications T

MIN

to T

, unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Differential Output Voltage, V

OD

2.0 5.0 V V

5.0 V R = ∞, Test Circuit 1
= 5 V, R = 50 Ω (RS-422), Test Circuit 1

CC

1.5 5.0 V R = 27 Ω (RS-485), Test Circuit 1

V

OD3

| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Test Circuit 1

∆|V

OD

Common-Mode Output Voltage, V

| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω

∆|V

OD

Output Short-Circuit Current (V
Output Short-Circuit Current (V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V

OC

= High) 35 250 mA –7 V ≤ VO ≤ +12 V

OUT

= Low) 35 250 mA –7 V ≤ VO ≤ +12 V

OUT

INL

INH

1.5 5.0 V V

3VR = 27 Ω or 50 Ω, Test Circuit 1

0.8 V

2.0 V

= –7 V to +12 V, Test Circuit 2

TST

Logic Input Current (DE, DI) ± 1.0 µA

RECEIVER

Differential Input Threshold Voltage, V
Input Voltage Hysteresis, ∆V

TH

TH

Input Resistance 12 kΩ –7 V
Input Current (A, B) 1 mA V

CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V

INL

INH

–0.2 +0.2 V –7 V ≤ VCM ≤ +12 V

70 mV VCM = 0 V

≤

VCM ≤ +12 V

= 12 V

IN

–0.8 mA V

= –7 V

IN

0.8 V

2.0 V

Logic Enable Input Current (RE) ± 1 µA
CMOS Output Voltage Low, V
CMOS Output Voltage High, V

OL

OH

4.0 V I

0.4 V I

Short-Circuit Output Current 7 85 mA V
Three-State Output Leakage Current ± 1.0 µA 0.4 V ≤ V

= +4.0 mA

OUT

= –4.0 mA

OUT

= GND or V

OUT

OUT

CC

≤ 2.4 V

POWER SUPPLY CURRENT

ICC (Outputs Enabled) 1.0 2.2 mA Digital Inputs = GND or V
ICC (Outputs Disabled) 0.6 1 mA Digital Inputs = GND or V

Specifications subject to change without notice.

CC

CC

TIMING SPECIFICATIONS

(VCC = 5 V ⴞ 5%. All specifications T

MIN

to T

, unless otherwise noted.)

MAX

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Propagation Delay Input to Output t
Driver O/P to O/P, t
Driver Rise/Fall Time, t

SKEW

, t

R

F

Driver Enable to Output Valid 10 25 ns R
Driver Disable Timing 10 25 ns R
Matched Enable Switching 0 2 ns R

|t

– t

AZH

BZL

|, |t

BZH

– t

AZL

|

Matched Disable Switching 0 2 ns R

|t

– t

AHZ

BLZ

|, |t

BHZ

– t

ALZ

|

PLH

, t

PHL

21015nsR

15nsR
815nsR

= 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3

LDIFF

= 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3

LDIFF

= 54 Ω, CL1 = CL2 = 100 pF, Test Circuit 3

LDIFF

= 110 Ω, CL = 50 pF, Test Circuit 4

L

= 110 Ω, CL = 50 pF, Test Circuit 4

L

= 110 Ω, CL = 50 pF, Test Circuit 4*

L

= 110 Ω, CL = 50 pF, Test Circuit 4*

L

RECEIVER

Propagation Delay Input to Output, t

– t

Skew |t

PLH

Receiver Enable, t
Receiver Disable, t

|5nsC

PHL

EN1

EN2

PLH

, t

PHL

81530nsC

520nsC
520nsC

= 15 pF, Test Circuit 5

L

= 15 pF, Test Circuit 5

L

= 15 pF, RL = 1 kΩ, Test Circuit 6

L

= 15 pF, RL = 1 kΩ, Test Circuit 6

L

Tx Pulse Width Distortion 1 ns
Rx Pulse Width Distortion 1 ns

*Guaranteed by characterization.

Specifications subject to change without notice.

–2–

REV. E

ADM485

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C, unless otherwise noted.)

VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Inputs

Driver Input (DI) . . . . . . . . . . . . . . . . –0.3 V to V

Control Inputs (DE, RE). . . . . . . . . . –0.3 V to V

+ 0.3 V

CC

+ 0.3 V

CC

Receiver Inputs (A, B) . . . . . . . . . . . . . . . . . . –9 V to +14 V

Outputs

Driver Outputs (A, B) . . . . . . . . . . . . . . . . . . –9 V to +14 V

Receiver Output . . . . . . . . . . . . . . . . . –0.5 V to V

+ 0.5 V

CC

Power Dissipation 8-Lead MSOP . . . . . . . . . . . . . . . . 900 mW

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W

θ

JA

Power Dissipation 8-Lead PDIP . . . . . . . . . . . . . . . . . 500 mW

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 130°C/W

θ

JA

Power Dissipation 8-Lead SOIC . . . . . . . . . . . . . . . . . 450 mW

, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 170°C/W

θ

JA

Operating Temperature Range

Commercial (J Version) . . . . . . . . . . . . . . . . . . . 0°C to 70°C

Industrial (A Version) . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods of time may affect device reliability.

Table I. Transmitting

Inputs Outputs

DE DI B A

1101
1010
0XZZ

Table II. Receiving

Inputs Output

RE A–B RO

0

≥

+0.2 V 1

0

≤

–0.2 V 0
0Inputs Open 1
1X Z

ORDERING GUIDE

Model Temperature Range Package Option Branding

ADM485AN –40°C to +85°C N-8
ADM485AR –40°C to +85°CR-8
ADM485AR-REEL –40°C to +85°CR-8
ADM485ARZ* –40°C to +85°CR-8
ADM485ARZ-REEL* –40°C to +85°CR-8
ADM485ARM –40°C to +85°CRM-8 M41
ADM485ARM-REEL –40°C to +85°CRM-8 M41
ADM485ARM-REEL7 –40°C to +85°CRM-8 M41
ADM485JN 0°C to 70°C N-8
ADM485JR 0°C to 70°CR-8
ADM485JR-REEL 0°C to 70°CR-8
ADM485JR-REEL7 0°C to 70°CR-8
ADM485JRZ* 0°C to 70°CR-8
ADM485JRZ-REEL* 0°C to 70°CR-8
ADM485JRZ-REEL7* 0°C to 70°CR-8

*Z = Lead Free.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
ADM485 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. E

–3–

ADM485

PIN CONFIGURATION

RO

RE

DE

1

2

ADM485

TOP VIEW

3

(Not to Scale)

4

8

V

CC

7

B

6

A

5

GNDDI

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1ROReceiver Output. When enabled, if A > B by 200 mV, then RO = High. If A < B by 200 mV, then

RO = Low.

2 RE Receiver Output Enable. A low level enables the receiver output, RO. A high level places it in a high

impedance state.

3DEDriver Output Enable. A high level enables the driver differential outputs, A and B. A low level places it in a

high impedance state.

4DIDriver Input. When the driver is enabled, a Logic Low on DI forces A low and B high while a Logic High

on DI forces A high and B low.
5 GND Ground Connection, 0 V.
6A Noninverting Receiver Input A/Driver Output A.
7B

Inverting Receiver Input B/Driver Output B.
8VCCPower Supply, 5 V ± 5%.

–4–

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