Analog Devices ADM4850 7 Datasheet
5 V Slew-Rate Limited Half- and Full-Duplex
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854—115 kbps
ADM4851/ADM4855—500 kbps
ADM4852/ADM4856—2.5 Mbps
ADM4853/ADM4857—10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI
True fail-safe receiver inputs
5 µA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-z when disabled or powered off
−7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with MAX308x
Specified over the −40°C to +85°C temperature range
Available in 8-lead SOIC and LFCSP packages
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
RS-485/RS-422 Transceivers
ADM4850–ADM4857
FUNCTIONAL BLOCK DIAGRAM
ADM4850/ADM4851/
ADM4852/ADM4853
RO
RE
DE
DI
V
CC
ADM4854/ADM4855/
ADM4856/ADM4857
R
D
GND
RO
A
B
DI
Figure 1.
V
CC
R
D
GND
A
B
Z
Y
04931-001
GENERAL DESCRIPTION
The ADM4850−ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication
on multipoint bus transmission lines. They are designed for
balanced data transmission and comply with EIA Standards
RS-485 and RS-422. The ADM4850−ADM4853 are half-duplex
transceivers, which share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854−ADM4857 transceivers have dedicated differential
line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Since only one driver
should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures a
logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
before communication begins and when communication ends.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges, and are available in 8-lead SOIC and LFCSP
packages.
Table 1. Selection Table
Part No Half-/Full-Duplex Data Rate
ADM4850 Half 115 kbps
ADM4851 Half 500 kbps
ADM4852 Half 2.5 Mbps
ADM4853 Half 10 Mbps
ADM4854 Full 115 kbp
ADM4855 Full 500 kbps
ADM4856 Full 2.5 Mbps
ADM4857 Full 10 Mbps
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
ADM4850–ADM4857
TABLE OF CONTENTS
Specifications..................................................................................... 3
Circuit Description......................................................................... 12
ADM4850/ADM4854 Timing Specifications........................... 4
ADM4851/ADM4855 Timing Specifications........................... 4
ADM4852/ADM4856 Timing Specifications........................... 5
ADM4853/ADM4857 Timing Specifications........................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Test C ir c uit s ....................................................................................... 8
Switching Characteristics ................................................................ 9
Typical Performance Characteristics ........................................... 10
REVISION HISTORY
10/04—Revision 0: Initial Version
Slew-Rate Control ...................................................................... 12
Receiver Input Filtering............................................................. 12
Half-/Full-Duplex Operation ................................................... 12
High Receiver Input Impedance .............................................. 13
Three-State Bus Connection..................................................... 13
Shutdown Mode ......................................................................... 13
Fail-Safe Operation .................................................................... 13
Current Limit and Thermal Shutdown ................................... 13
Outline Dimensions ....................................................................... 14
Ordering Guide .......................................................................... 15
Rev. 0 | Page 2 of 16
ADM4850–ADM4857
SPECIFICATIONS
V = 5 V ± 5%, TA = T
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, V
2.0 5 V R = 50 Ω (RS-422), Figure 4
1.5 5 V R = 27 Ω (RS-485), Figure 4
1.5 5 V V
∆|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 4
Common-Mode Output Voltage, VO 3 V R = 27 Ω or 50 Ω, Figure 4
∆|VO | for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 4
Output Short-Circuit Current, V
Output Short-Circuit Current, V
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low 1.4 0.8 V
CMOS Input Logic Threshold High 2.0 1.4 V
CMOS Logic Input Current (DI) ±1 µA
DE Input Resistance to GND 220 kΩ
RECEIVER
Differential Input Threshold Voltage, V
Input Hysteresis 20 mV −7 V < VM < +12 V
Input Resistance (A, B) 96 150 kΩ −7 V < VM < +12 V
Input Current (A, B) 0.125 mA VIN = +12 V
−0.1 mA V
CMOS Logic Input Current (RE)
CMOS Output Voltage Low 0.4 V I
CMOS Output Voltage High 4.0 V I
Output Short Circuit Current 7 85 mA V
Three-State Output Leakage Current ±2 µA 0.4 V ≤ V
POWER SUPPLY CURRENT
I (115 kbps Options) 5 µA
36 60 µA
100 160 µA DE = VCC
I (500 kbps Options) 5 µA
80 120 µA
120 200 µA DE = V
I (2.5 Mbps Options) 5 µA
250 400 µA
320 500 µA DE = VCC
I (10 Mbps Options) 5 µA
250 400 µA
320 500 µA DE = VCC
1
Guaranteed by design.
MIN
to T
, unless otherwise noted.
MAX
OD
= High −200 +200 mA −7 V < V
OUT
= Low −200 +200 mA −7 V < V
OUT
TH
VCCV
−200 −125 −30 mV −7 V < VM < +12 V
±1 µA
R = ∞, Figure 4
= −7 V to 12 V, Figure 5
TST
= −7 V
IN
= +4 mA
OUT
= −4 mA
OUT
= GND or V
OUT
DE = 0 V,
DE = 0 V,
DE = 0 V,
DE = 0 V,
CC
DE = 0 V,
DE = 0 V,
DE = 0 V,
DE = 0 V,
1
< +12 V
OUT
< +12 V
OUT
CC
≤ 2.4 V
OUT
RE = VCC (shutdown)
RE = 0 V
RE = VCC (shutdown)
RE = 0 V
RE = VCC (shutdown)
RE = 0 V
RE = VCC (shutdown)
RE = 0 V
Rev. 0 | Page 3 of 16
ADM4850–ADM4857
ADM4850/ADM4854 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = T
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 115 kbps
Propagation Delay t
Skew t
SKEW
Rise/Fall Time tR, t
Enable Time 2000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850
Disable Time 2000 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4850
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4850
RECEIVER
Propagation Delay t
Differential Skew t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4850
Time to Shut Down 50 330 3000 ns ADM4850
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4851/ADM4855 TIMING SPECIFICATIONS
F
SKEW
MIN
PLH
PLH
to T
, t
PHL
, t
PH
, unless otherwise noted.
MAX
600 2500 ns R
70 ns R
600 2400 ns R
400 1000 ns CL = 15 pF, Figure 8
255 ns CL = 15 pF, Figure 8
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
= 54 Ω, C
LDIFF
= CL2 = 100 pF, Figure 6
L1
1
V = 5 V ± 5%, TA = T
MIN
to T
, unless otherwise noted.
MAX
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 500 kbps
Propagation Delay t
Skew t
SKEW
Rise/Fall Time tR, t
, t
PLH
PHL
F
250 600 ns R
40 ns R
200 600 ns R
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
= 54 Ω, CL1 = C
LDIFF
= 100 pF, Figure 6
L2
Enable Time 1000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851
Disable Time 1000 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4851
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4851
RECEIVER
Propagation Delay t
Differential Skew t
SKEW
PLH
, t
PHL
400 1000 ns CL = 15 pF, Figure 8
250 ns CL = 15 pF, Figure 8
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4851
Disable Time 20 50 ns RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851
Enable Time from Shutdown 4000 ns RL =1 kΩ, CL = 15 pF, Figure 9, ADM4851
Time to Shut Down 50 330 3000 ns ADM4851
1
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
Rev. 0 | Page 4 of 16
ADM4850–ADM4857
ADM4852/ADM4856 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = T
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 2.5 Mbps
Propagation Delay t
Skew t
SKEW
Rise/Fall Time tR, t
Enable Time 180 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4852
Disable Time 180 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4852
Enable Time from Shutdown 4000 ns RL =500 Ω, CL = 100 pF, Figure 7, ADM4852
RECEIVER
Propagation Delay t
Differential Skew t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4852
Time to Shut Down 50 330 3000 ns ADM4852
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
ADM4853/ADM4857 TIMING SPECIFICATIONS
V = 5 V ± 5%, TA = T
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 10 Mbps
Propagation Delay t
Skew t
SKEW
Rise/Fall Time tR, t
Enable Time 35 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4853
Disable Time 35 ns RL = 500 Ω, CL = 15 pF, Figure 7, ADM4853
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, Figure 7, ADM4853
RECEIVER
Propagation Delay t
Differential Skew t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, Figure 9, ADM4853
Time to Shut Down 50 330 3000 ns ADM48531
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
F
SKEW
F
SKEW
MIN
PLH
PLH
MIN
PLH
PLH
to T
, t
PHL
, t
PHL
to T
, t
PHL
, t
PHL
, unless otherwise noted.
MAX
50 180 ns R
50 ns R
140 ns R
55 190 ns CL = 15 pF, Figure 8
50 ns CL = 15 pF, Figure 8
, unless otherwise noted.
MAX
0 30 ns R
10 ns R
30 ns R
55 190 ns CL = 15 pF, Figure 8
30 ns CL = 15 pF, Figure 8
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
1
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, Figure 6
LDIFF
Rev. 0 | Page 5 of 16
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