ANALOG DEVICES ADM4850 Service Manual
5 V, Slew-Rate Limited, Half-Duplex and
V
V
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
FEATURES
EIA RS-485-/RS-422-compliant
Data rate options
ADM4850/ADM4854: 115 kbps
ADM4851/ADM4855: 500 kbps
ADM4852/ADM4856: 2.5 Mbps
ADM4853/ADM4857: 10 Mbps
Half- and full-duplex options
Full-Duplex RS-485/RS-422 Transceivers
FUNCTIONAL BLOCK DIAGRAMS
CC
ADM4850/ADM4851/
ADM4852/ADM4853
RO
RE
DE
R
A
B
Reduced slew rates for low EMI
True fail-safe receiver inputs
DI
D
5 μA (maximum) supply current in shutdown mode
Up to 256 transceivers on one bus
Outputs high-Z when disabled or powered off
−7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with the MAX308x
Specified over the −40°C to +85°C temperature range
Available in 8-lead SOIC, LFCSP, and MSOP packages
Qualified for automotive applications
RO
GND
Figure 1.
CC
ADM4854/ADM4855/
ADM4856/ADM4857
R
04931-001
A
B
APPLICATIONS
Low power RS-485 applications
EMI-sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
DI
D
GND
Figure 2.
Z
Y
04931-028
GENERAL DESCRIPTION
The ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/
ADM4855/ADM4856/ADM4857 are differential line transceivers
suitable for high speed half- and full-duplex data communication on
multipoint bus transmission lines. They are designed for balanced
data transmission and comply with EIA Standards RS-485 and
RS-422. The ADM4850/ADM4851/ADM4852/ADM4853 are halfduplex transceivers that share differential lines and have separate
enable inputs for the driver and receiver. The full-duplex
ADM4854/ADM4855/ADM4856/ADM4857 transceivers have
dedicated differential line driver outputs and receiver inputs.
The parts have a 1/8-unit-load receiver input impedance, which
allows up to 256 transceivers on one bus. Because only one driver
should be enabled at any time, the output of a disabled or powered-down driver is three-stated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which ensures
a logic high output level when the inputs are open or shorted.
This guarantees that the receiver outputs are in a known state
Rev. D
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
before communication begins and when communication ends.
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by output
shorting is prevented with a thermal shutdown circuit.
The parts are fully specified over the commercial and industrial
temperature ranges and are available in 8-lead SOIC, LFCSP
(ADM4850/ADM4851/ADM4852/ADM4853), and MSOP
(ADM4850 only) packages.
Table 1. Selection Table
Part No. Half-/Full-Duplex Data Rate
ADM4850 Half 115 kbps
ADM4851 Half 500 kbps
ADM4852 Half 2.5 Mbps
ADM4853 Half 10 Mbps
ADM4854 Full 115 kbps
ADM4855 Full 500 kbps
ADM4856 Full 2.5 Mbps
ADM4857 Full 10 Mbps
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2012 Analog Devices, Inc. All rights reserved.
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagrams............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADM4850/ADM4854 Timing Specifications........................... 4
ADM4851/ADM4855 Timing Specifications........................... 4
ADM4852/ADM4856 Timing Specifications........................... 5
ADM4853/ADM4857 Timing Specifications........................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 11
Switching Characteristics .............................................................. 12
Circuit Description......................................................................... 13
Slew-Rate Control ...................................................................... 13
Receiver Input Filtering............................................................. 13
Half-/Full-Duplex Operation ................................................... 13
High Receiver Input Impedance .............................................. 14
Three-State Bus Connection..................................................... 14
Shutdown Mode ......................................................................... 14
Fail-Safe Operation .................................................................... 14
Current Limit and Thermal Shutdown ................................... 14
Outline Dimensions....................................................................... 15
Ordering Guide .......................................................................... 16
Automotive Product................................................................... 16
REVISION HISTORY
1/12—Rev. C to Rev. D
Change to Features Section............................................................. 1
Changes to Ordering Guide.......................................................... 15
Added Automotive Products Section .......................................... 15
1/11—Rev. B to Rev. C
Change to Table 8, Pin 3 Description ............................................ 7
Changes to Figure 29...................................................................... 12
Changes to Ordering Guide.......................................................... 15
7/09—Rev. A to Rev. B
Added MSOP Package.................................................. Throughout
Changes to Table 2............................................................................ 3
Changes to Table 7............................................................................ 6
Added Figure 4; Renumbered Figures Sequentially..................... 7
Moved Typical Performance Characteristics Section .................. 8
Changes to Figure 24, Figure 27 ................................................... 11
Changes to Figure 29...................................................................... 12
Change to Shutdown Mode Section............................................. 13
Updated Outline Dimensions....................................................... 14
Changes to Ordering Guide.......................................................... 15
4/09—Rev. 0 to Rev. A
Changes to Ordering Guide.......................................................... 15
10/04—Revision 0: Initial Version
Rev. D | Page 2 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD V
2.0 5 V R = 50 Ω (RS-422), see Figure 18
1.5 5 V R = 27 Ω (RS-485), see Figure 18
|V
| 1.5 5 V V
OD3
∆|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 18
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 18
∆|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 18
Output Short-Circuit Current, V
Output Short-Circuit Current, V
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low 0.8 V
CMOS Input Logic Threshold High 2.0 V
CMOS Logic Input Current (DI) ±1 μA
DE Input Resistance to GND 220 kΩ
RECEIVER
Differential Input Threshold Voltage, VTH −200 −125 −30 mV −7 V < VOC < +12 V
Input Hysteresis 20 mV −7 V < VOC < +12 V
Input Resistance (A, B) 96 150 kΩ −7 V < VOC < +12 V
Input Current (A, B) 0.125 mA VIN = +12 V
−0.1 mA V
CMOS Logic Input Current (RE)
CMOS Output Voltage Low 0.4 V I
CMOS Output Voltage High 4.0 V I
Output Short-Circuit Current 7 85 mA V
Three-State Output Leakage Current ±2 μA 0.4 V ≤ V
POWER SUPPLY CURRENT
115 kbps Options (ADM4850/ADM4854) 5 μA
36 60 μA
100 160 μA DE = VCC
500 kbps Options (ADM4851/ADM4855) 5 μA
80 120 μA
120 200 μA DE = VCC
2.5 Mbps Options (ADM4852/ADM4856) 5 μA
250 400 μA
320 500 μA DE = VCC
10 Mbps Options (ADM4853/ADM4857) 5 μA
250 400 μA
320 500 μA DE = VCC
1
Guaranteed by design.
MIN
to T
, unless otherwise noted.
MAX
V R = ∞, see Figure 181
CC
= High −200 +200 mA −7 V < V
OUT
= Low −200 +200 mA −7 V < V
OUT
±1 μA
= −7 V to 12 V, see Figure 19
TST
< +12 V
OUT
< +12 V
OUT
= −7 V
IN
= +4 mA
OUT
= −4 mA
OUT
= GND or VCC
OUT
≤ 2.4 V
OUT
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
DE = 0 V, RE
= VCC (shutdown)
= 0 V
= VCC (shutdown)
= 0 V
= VCC (shutdown)
= 0 V
= VCC (shutdown)
= 0 V
Rev. D | Page 3 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ADM4850/ADM4854 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 115 kbps
Propagation Delay, t
Skew, t
70 ns R
SKEW
Rise/Fall Times, tR, tF 600 2400 ns R
Enable Time, tZH 2000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
Disable Time, tZL 2000 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4850
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4850
RECEIVER
Propagation Delay, t
Differential Skew, t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4850
Time to Shutdown 50 330 3000 ns ADM48501
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
to T
MIN
, t
PLH
, t
PLH
255 ns CL = 15 pF, see Figure 22
SKEW
, unless otherwise noted.
MAX
600 2500 ns R
PHL
400 1000 ns CL = 15 pF, see Figure 22
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, C
LDIFF
L1
= CL2 = 100 pF, see Figure 20
ADM4851/ADM4855 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 500 kbps
Propagation Delay, t
Skew, t
40 ns R
SKEW
Rise/Fall Times, tR, tF 200 600 ns R
Enable Time, tZH 1000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
Disable Time, tZL 1000 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4851
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4851
RECEIVER
Propagation Delay, t
Differential Skew, t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4851
Time to Shutdown 50 330 3000 ns ADM48511
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
to T
MIN
, t
PLH
, t
PLH
250 ns CL = 15 pF, see Figure 22
SKEW
, unless otherwise noted.
MAX
250 600 ns R
PHL
400 1000 ns CL = 15 pF, see Figure 22
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = C
LDIFF
= 100 pF, see Figure 20
L2
Rev. D | Page 4 of 16
ADM4850/ADM4851/ADM4852/ADM4853/ADM4854/ADM4855/ADM4856/ADM4857
ADM4852/ADM4856 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 2.5 Mbps
Propagation Delay, t
Skew, t
50 ns R
SKEW
Rise/Fall Times, tR, tF 140 ns R
Enable Time, tZH 180 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
Disable Time, tZL 180 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4852
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4852
RECEIVER
Propagation Delay, t
Differential Skew, t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4852
Time to Shutdown 50 330 3000 ns ADM48521
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
to T
MIN
, t
PLH
, t
PLH
50 ns CL = 15 pF, see Figure 22
SKEW
, unless otherwise noted.
MAX
50 180 ns R
PHL
55 190 ns CL = 15 pF, see Figure 22
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
ADM4853/ADM4857 TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 6.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 10 Mbps
Propagation Delay, t
Skew, t
10 ns R
SKEW
Rise/Fall Times, tR, tF 30 ns R
Enable Time, tZH 35 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
Disable Time, tZL 35 ns RL = 500 Ω, CL = 15 pF, see Figure 21, ADM4853
Enable Time from Shutdown 4000 ns RL = 500 Ω, CL = 100 pF, see Figure 21, ADM4853
RECEIVER
Propagation Delay, t
Differential Skew, t
Enable Time 5 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Enable Time from Shutdown 4000 ns RL = 1 kΩ, CL = 15 pF, see Figure 23, ADM4853
Time to Shutdown 50 330 3000 ns ADM48531
1
The half-duplex device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to
enter shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to enter shutdown mode.
to T
MIN
, t
PLH
, t
PLH
30 ns CL = 15 pF, see Figure 22
SKEW
, unless otherwise noted.
MAX
0 30 ns R
PHL
55 190 ns CL = 15 pF, see Figure 22
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 20
LDIFF
Rev. D | Page 5 of 16
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