ANALOG DEVICES ADM485 Service Manual
5 V Low Power
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FEATURES
Meets EIA RS-485 standard
5 Mbps data rate
Single 5 V supply
–7 V to +12 V bus common-mode range
High speed, low power BiCMOS
Thermal shutdown protection
Short-circuit protection
Driver propagation delay: 10 ns typical
Receiver propagation delay: 15 ns typical
High-Z outputs with power off
Superior upgrade for LTC485
APPLICATIONS
Low power RS-485 systems
DTE/DCE interface
Packet switching
Local area networks (LNAs)
Data concentration
Data multiplexers
Integrated services digital network (ISDN)
EIA RS-485 Transceiver
ADM485
FUNCTIONAL BLOCK DIAGRAM
ADM485
RO
RE
DE
1
2
3
4
DI
R
D
Figure 1.
8
V
CC
7
B
6
A
5
GND
00078-001
GENERAL DESCRIPTION
The ADM485 is a differential line transceiver suitable for high
speed bidirectional data communication on multipoint bus
transmission lines. It is designed for balanced data transmission
and complies with EIA standards RS-485 and RS-422. The part
contains a differential line driver and a differential line receiver.
Both the driver and the receiver can be enabled independently.
When disabled, the outputs are three-stated.
The ADM485 operates from a single 5 V power supply.
xcessive power dissipation caused by bus contention or by
E
output shorting is prevented by a thermal shutdown circuit. If
during fault conditions, a significant temperature increase is
detected in the internal driver circuitry, this feature forces the
driver output into a high impedance state.
Up to 32 transceivers can be connected simultaneously on a
bu
s, but only one driver should be enabled at any time. It is
important, therefore, that the remaining disabled drivers do not
load the bus. To ensure this, the ADM485 driver features high
output impedance when disabled and when powered down,
which minimizes the loading effect when the transceiver is not
being used. The high impedance driver output is maintained
over the common-mode voltage range of −7 V to +12 V.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The ADM485 is fabricated on BiCMOS, an advanced mixed
t
echnology process combining low power CMOS with fast
switching bipolar technology. All inputs and outputs contain
protection against ESD; all driver outputs feature high source
and sink current capability. An epitaxial layer is used to guard
against latch-up.
The ADM485 features extremely fast switching speeds. Minimal
dr
iver propagation delays permit transmission at data rates up
to 5 Mbps while low skew minimizes EMI interference.
The part is fully specified over the commercial and industrial
t
emperature range and is available in 8-lead PDIP, 8-lead SOIC,
and small footprint, 8-lead MSOP packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1993–2008 Analog Devices, Inc. All rights reserved.
ADM485
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TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
04/08—Rev. E to Rev. F
Updated Format..................................................................Universal
hanges to Table 2............................................................................ 4
C
Updated Outline Dimension......................................................... 13
Changes to Ordering Guide.......................................................... 14
10/03—Rev. D to Rev. E
Changes to Timing Specifications.................................................. 2
Updated Ordering Guide................................................................. 3
7/03—Rev. C to Rev. D
Changes to Absolute Maximum Ratings....................................... 3
Changes to Ordering Guide............................................................ 3
Update to Outline Dimensions....................................................... 9
Test Cir c ui t s ..................................................................................... 10
Switching Characteristics .............................................................. 11
Applications Information.............................................................. 12
Differential Data Transmission ................................................ 12
Cable and Data Rate................................................................... 12
Thermal Shutdown .................................................................... 12
Propagation Delay ...................................................................... 12
Receiver Open Circuit, Fail-Safe.............................................. 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 14
1/03—Rev. B to Rev. C.
Change to Specifications ..................................................................2
Change to Ordering Guide...............................................................3
12/02—Rev. A to Rev. B.
Deleted Q-8 Package..........................................................Universal
Edits to Features.................................................................................1
Edits to General Description ...........................................................1
Edits, additions to Specifications.....................................................2
Edits, additions to Absolute Maximum Ratings............................3
Additions to Ordering Guide...........................................................3
TPCs Updated and Reformatted .....................................................5
Addition of 8-Lead MSOP Package ................................................9
Update to Outline Dimensions........................................................9
Rev. F | Page 2 of 16
ADM485
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SPECIFICATIONS
VCC = 5 V ± 5%, all specifications T
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD 5.0 V R = ∞, see Figure 20
2.0 5.0 V VCC = 5 V, R = 50 Ω (RS-422), see Figure 20
1.5 5.0 V R = 27 Ω (RS-485), see Figure 20
V
1.5 5.0 V V
OD3
Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 20
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 20
Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω
Output Short-Circuit Current, V
Output Short-Circuit Current, V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
Logic Input Current (DE, DI) ±1.0 μA
RECEIVER
Differential Input Threshold Voltage, VTH −0.2 +0.2 V −7 V ≤ VCM ≤ +12 V
Input Voltage Hysteresis, ΔVTH 70 mV VCM = 0 V
Input Resistance 12 kΩ −7 V ≤ VCM ≤ +12 V
Input Current (A, B) 1 mA VIN = 12 V
–0.8 mA VIN = −7 V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL 0.4 V I
CMOS Output Voltage High, VOH 4.0 V I
Short-Circuit Output Current 7 85 mA V
Three-State Output Leakage Current ±1.0 μA 0.4 V ≤ V
POWER SUPPLY CURRENT
ICC, Outputs Enabled
ICC, Outputs Disabled
to T
MIN
= High 35 250 mA −7 V ≤ VO ≤ +12 V
OUT
= Low 35 250 mA −7 V ≤ VO ≤ +12 V
OUT
INL
INH
INL
INH
, unless otherwise noted.
MAX
0.8 V
2.0 V
0.8 V
2.0 V
±1
μA
= −7 V to +12 V, see Figure 21
TST
= 4.0 mA
OUT
= −4.0 mA
OUT
= GND or VCC
OUT
OUT
1.0 2.2 mA Digital inputs = GND or V
0.6 1 mA Digital inputs = GND or V
≤ 2.4 V
CC
CC
Rev. F | Page 3 of 16
ADM485
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TIMING SPECIFICATIONS
VCC = 5 V ± 5%, all specifications T
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output, t
Driver Output to OUTPUT, t
SKEW
Driver Rise/Fall Time, tR, tF 8 15 ns R
Driver Enable to Output Valid 10 25 ns RL = 110 Ω, CL = 50 pF, see Figure 23
Driver Disable Timing 10 25 ns RL = 110 Ω, CL = 50 pF, see Figure 23
Matched Enable Switching |tZH − tZL| 0 2 ns RL = 110 Ω, CL = 50 pF, see Figure 231
Matched Disable Switching |tHZ − tLZ| 0 2 ns RL = 110 Ω, CL = 50 pF, see Figure 231
RECEIVER
Propagation Delay Input to Output, t
Skew |t
Receiver Enable, tZH, t
PLH
− t
| 5 ns CL = 15 pF, see Figure 24
PHL
ZL
Receiver Disable, tHZ, tLZ 5 20 ns CL = 15 pF, RL = 1 kΩ, see Figure 25
Tx Pulse Width Distortion 1 ns
Rx Pulse Width Distortion 1 ns
1
Guaranteed by characterization.
to T
MIN
, unless otherwise noted.
MAX
, t
2 10 15 ns R
PLH
PHL
1 5 ns
, t
8 15 30 ns CL = 15 pF, see Figure 24
PLH
PHL
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
R
LDIFF
= 54 Ω, CL1 = CL2 = 100 pF, see Figure 22
LDIFF
5 20 ns CL = 15 pF, RL = 1 kΩ, see Figure 25
Rev. F | Page 4 of 16
ADM485
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ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
V
CC
Inputs
Driver Input (DI) −0.3 V to VCC + 0.3 V
Control Inputs (DE, RE)
Receiver Inputs (A, B) −9 V to +14 V
Outputs
Driver Outputs (A, B) −9 V to +14 V
Receiver Output −0.5 V to VCC + 0.5 V
Power Dissipation 8-Lead MSOP 900 mW
θJA, Thermal Impedance 206°C/W
Power Dissipation 8-Lead PDIP 500 mW
θJA, Thermal Impedance 130°C/W
Power Dissipation 8-Lead SOIC 450 mW
θJA, Thermal Impedance 170°C/W
Operating Temperature Range
Commercial Range (J Version) 0°C to 70°C
Industrial Range (A Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
−0.3 V to +7 V
−0.3 V to V
CC
+ 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 4. Transmitting
Inputs Outputs
DE DI B A
1 1 0 1
1 0 1 0
0 X
1
X = don’t care.
2
Z = high impedance.
1
Z2 Z2
Table 5. Receiving
RE
0 ≥ +0.2 V 1
0 ≤ −0.2 V 0
0 Inputs open 1
1
1
X = don’t care.
2
Z = high impedance.
Input A − Input B Output RO
1
X
Z2
ESD CAUTION
Rev. F | Page 5 of 16
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