±15 kV ESD protection
250 kbps data rate
Reduced slew rate for low EM interference
Single 5 V ± 10% supply
−7 V to +12 V bus common-mode range
Up to 32 nodes on the bus
Receiver open-circuit, fail-safe design
Short-circuit protection
36 μA supply current
0.1 μA shutdown current
APPLICATIONS
Low power RS-485 systems
Electrically harsh environments
EMI sensitive applications
DTE-DCE interface
Packet switching
Local area networks
Limited, 5 V, RS-485 Transceiver
ADM483E
FUNCTIONAL BLOCK DIAGRAM
ADM483E
RO
RE
DE
DI
R
D
Figure 1.
B
A
6012-001
GENERAL DESCRIPTION
The ADM483E is a 5 V, low power data transceiver with ±15 kV
ESD protection suitable for half-duplex communication on
multipoint bus transmission lines. The ADM483E is designed
for balanced data transmission and complies with TIA/EIA
Standards RS-485 and RS-422, which allow up to 32 transceivers
on a bus.
The ADM483E has a low current shutdown mode in which it
nsumes only 0.1 μA.
co
Because only one driver is enabled at any time, the output of a
dis
abled or power-down driver is three-stated to avoid
overloading the bus.
Drivers are short-circuit current-limited and are protected
a
gainst excessive power dissipation by thermal shutdown
circuitry that places their outputs into a high impedance state.
The receiver input has a fail-safe feature that guarantees a logic
high output if the input is open circuit.
The ADM483E is fully specified over the industrial temperature
nges and is available in 8-lead SOIC_N packages.
ra
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD 5.0 V VCC = 5.25 V; R = ∞, see Figure 15
2.0 5.0 V R = 50 Ω (RS-422), see Figure 15
1.5 5.0 V R = 27 Ω (RS-485), see Figure 15
1.5 5.0 V VIN = –7 V to +12 V
Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 15
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 15
Δ|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω
Output Short-Circuit Current (V
Output Short-Circuit Current (V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
Logic Input Current (DE, DI) ±1.0 μA
RECEIVER
Differential Input Threshold Voltage, VTH −0.2 +0.2 V −7 V ≤ VCM ≤ +12 V
Input Voltage Hysteresis, ΔVTH 70 mV VCM = 0 V
Input Resistance 12 kΩ −7 V ≤ VCM ≤ +12 V
Input Current (A, B) 1 mA VIN = 12 V
−0.8 mA VIN = –7 V
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL 0.4 V I
CMOS Output Voltage High, VOH 4.0 V I
Short-Circuit Output Current 7 85 mA V
Three-State Output Leakage Current ±2.0 μA 0.4 V ≤ V
POWER SUPPLY CURRENT Outputs unloaded, receivers enabled
ICC 36 120 μA
270 360 μA
Supply Current in Shutdown 0.1 10 μA
ESD IMMUNITY
ESD Protection ±15 kV HBM air discharge; Pin A, Pin B
to T
MIN
= High) 250 mA –7 V ≤ VO ≤ +12 V
OUT
= Low) 250 mA –7 V ≤ VO ≤ +12 V
OUT
1.4 0.8 V
INL
INH
, unless otherwise noted.
MAX
2.0 1.4 V
±1 μA
= 4.0 mA
OUT
= −4.0 mA
OUT
= GND or VCC
OUT
OUT
DE = 0 V (disabled), RE
DE = 5 V (enabled), RE
DE = 0 V, RE
≤ 2.4 V
= 0 V
= 0 V
= VCC
Rev. A | Page 3 of 16
ADM483E
www.BDTIC.com/ADI
TIMING SPECIFICATIONS
VCC = 5 V ± 10%. All specifications T
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Propagation Delay Input to Output (t
Driver Output to Output (t
SKEW
)
Driver Rise/Fall Time (tR, tF) 250 2000 ns
Driver Enable to Output Valid 250 2000 ns RL = 500 Ω, CL = 100 pF, see Figure 18 and Figure 19
Driver Enable from Shutdown 5000 ns RL = 500 Ω, CL = 100 pF, see Figure 18 and Figure 19
Receiver Enable from Shutdown 5000 ns RL = 1 kΩ, CL = 15 pF, see Figure 22
MIN
to T
PLH
, unless otherwise noted.
MAX
, t
) 250 2000 ns
PHL
Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and
R
L
Figure 17
100 800 ns
RL Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and
Figure 17
Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and
R
L
Figure 17
, t
) 250 2000 ns CL = 15 pF, see Figure 20
PLH
PHL
Rev. A | Page 4 of 16
ADM483E
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC to GND −0.5 V to +6 V
Digital I/O Voltage (DE, RE)
Driver Input Voltage (DI) −0.5 V to (VCC + 0.5 V)
Receiver Output Voltage (RO) −0.5 V to (VCC + 0.5 V)
Driver Output/Receiver Input Voltage
(Pin A, Pin B)
ESD Rating: Air (Human Body Model)
(Pin A, Pin B)
Power Dissipation 8-Lead SOIC_N 470 mW
θJA, Thermal Impedance 110°C/W
Operating Temperature Range
Industrial (A Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
−0.5 V to ( V
−9 V to +14 V
±15 kV
+ 0.5 V)
CC
Stresses above those listed under Absolute Maximum Ratings
ma
y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 16
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