Datasheet ADM483E Datasheet (ANALOG DEVICES)

±15 kV ESD Protected, Slew Rate

www.BDTIC.com/ADI

FEATURES

±15 kV ESD protection
250 kbps data rate
Reduced slew rate for low EM interference
Single 5 V ± 10% supply

−7 V to +12 V bus common-mode range
Up to 32 nodes on the bus
Receiver open-circuit, fail-safe design
Short-circuit protection
36 μA supply current

0.1 μA shutdown current

APPLICATIONS

Low power RS-485 systems
Electrically harsh environments
EMI sensitive applications
DTE-DCE interface
Packet switching
Local area networks

Limited, 5 V, RS-485 Transceiver

ADM483E

FUNCTIONAL BLOCK DIAGRAM

ADM483E

RO

RE

DE

DI

R

D

Figure 1.

B

A

6012-001

GENERAL DESCRIPTION

The ADM483E is a 5 V, low power data transceiver with ±15 kV
ESD protection suitable for half-duplex communication on
multipoint bus transmission lines. The ADM483E is designed
for balanced data transmission and complies with TIA/EIA
Standards RS-485 and RS-422, which allow up to 32 transceivers
on a bus.

The ADM483E has a low current shutdown mode in which it

nsumes only 0.1 μA.

co

Because only one driver is enabled at any time, the output of a
dis

abled or power-down driver is three-stated to avoid

overloading the bus.

Drivers are short-circuit current-limited and are protected
a

gainst excessive power dissipation by thermal shutdown
circuitry that places their outputs into a high impedance state.
The receiver input has a fail-safe feature that guarantees a logic
high output if the input is open circuit.

The ADM483E is fully specified over the industrial temperature

nges and is available in 8-lead SOIC_N packages.

ra

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©1997–2007 Analog Devices, Inc. All rights reserved.

ADM483E

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Timing Specifications .................................................................. 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

REVISION HISTORY

12/07—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Features ......................................................................... 1

Changes to General Description .................................................... 1

Changes to Table 1............................................................................ 3

Changes to Table 2............................................................................ 4

Changes to Table 3............................................................................ 5

Changes to Table 5............................................................................ 6

Changes to Typical Performance Characteristics Section........... 7

Changes to Test Circuits and Switching Characteristics Section...9

Changes to General Information Section.................................... 11

Updated Outline Dimensions....................................................... 14

Changes to Ordering Guide.......................................................... 14

1/97—Revision 0: Initial Version

Test Circuits and Switching Characteristics...................................9

General Information...................................................................... 11

ESD Transient Protection Scheme ........................................... 11

ESD Testing ................................................................................. 12

Applications Information.............................................................. 13

Differential Data Transmission ................................................ 13

Cable and Data Rate................................................................... 13

Outline Dimensions....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. A | Page 2 of 16

ADM483E

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SPECIFICATIONS

VCC = 5 V ± 10%. All specifications T

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Differential Output Voltage, VOD 5.0 V VCC = 5.25 V; R = ∞, see Figure 15

2.0 5.0 V R = 50 Ω (RS-422), see Figure 15

1.5 5.0 V R = 27 Ω (RS-485), see Figure 15

1.5 5.0 V VIN = –7 V to +12 V
Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 15
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 15
Δ|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω
Output Short-Circuit Current (V
Output Short-Circuit Current (V
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
Logic Input Current (DE, DI) ±1.0 μA

RECEIVER

Differential Input Threshold Voltage, VTH −0.2 +0.2 V −7 V ≤ VCM ≤ +12 V
Input Voltage Hysteresis, ΔVTH 70 mV VCM = 0 V
Input Resistance 12 kΩ −7 V ≤ VCM ≤ +12 V
Input Current (A, B) 1 mA VIN = 12 V

−0.8 mA VIN = –7 V
Logic Enable Input Current (RE)
CMOS Output Voltage Low, VOL 0.4 V I
CMOS Output Voltage High, VOH 4.0 V I
Short-Circuit Output Current 7 85 mA V
Three-State Output Leakage Current ±2.0 μA 0.4 V ≤ V

POWER SUPPLY CURRENT Outputs unloaded, receivers enabled

ICC 36 120 μA
270 360 μA
Supply Current in Shutdown 0.1 10 μA

ESD IMMUNITY

ESD Protection ±15 kV HBM air discharge; Pin A, Pin B

to T

MIN

= High) 250 mA –7 V ≤ VO ≤ +12 V

OUT

= Low) 250 mA –7 V ≤ VO ≤ +12 V

OUT

1.4 0.8 V

INL

INH

, unless otherwise noted.

MAX

2.0 1.4 V

±1 μA

= 4.0 mA

OUT

= −4.0 mA

OUT

= GND or VCC

OUT

OUT

DE = 0 V (disabled), RE
DE = 5 V (enabled), RE
DE = 0 V, RE

≤ 2.4 V

= 0 V

= 0 V

= VCC

Rev. A | Page 3 of 16

ADM483E

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TIMING SPECIFICATIONS

VCC = 5 V ± 10%. All specifications T

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Propagation Delay Input to Output (t

Driver Output to Output (t

SKEW

)

Driver Rise/Fall Time (tR, tF) 250 2000 ns

Driver Enable to Output Valid 250 2000 ns RL = 500 Ω, CL = 100 pF, see Figure 18 and Figure 19

Driver Disable Timing 300 3000 ns RL = 500 Ω, CL = 15 pF, see Figure 18 and Figure 19
RECEIVER

Propagation Delay Input to Output (t

Skew (|t

Receiver Enable (t

Receiver Disable (t

– t

|) 200 ns

PLH

PHL

) 10 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 22

EN1

) 10 50 ns RL = 1 kΩ, CL = 15 pF, see Figure 22

EN2

SHUTDOWN

Time to Shutdown 50 200 3000 ns

Driver Enable from Shutdown 5000 ns RL = 500 Ω, CL = 100 pF, see Figure 18 and Figure 19

Receiver Enable from Shutdown 5000 ns RL = 1 kΩ, CL = 15 pF, see Figure 22

MIN

to T

PLH

, unless otherwise noted.

MAX

, t

) 250 2000 ns

PHL

Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and

R

L

Figure 17

100 800 ns

RL Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and
Figure 17

Diff = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and

R

L

Figure 17

, t

) 250 2000 ns CL = 15 pF, see Figure 20

PLH

PHL

Rev. A | Page 4 of 16

ADM483E

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VCC to GND −0.5 V to +6 V
Digital I/O Voltage (DE, RE)
Driver Input Voltage (DI) −0.5 V to (VCC + 0.5 V)
Receiver Output Voltage (RO) −0.5 V to (VCC + 0.5 V)
Driver Output/Receiver Input Voltage

(Pin A, Pin B)

ESD Rating: Air (Human Body Model)

(Pin A, Pin B)

Power Dissipation 8-Lead SOIC_N 470 mW

θJA, Thermal Impedance 110°C/W

Operating Temperature Range

Industrial (A Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−0.5 V to ( V

−9 V to +14 V

±15 kV

+ 0.5 V)

CC

Stresses above those listed under Absolute Maximum Ratings
ma

y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 5 of 16

ADM483E

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

RO

ADM483E

RE

2

DE

3

TOP VIEW

(Not to Scale)

DI

4

Figure 2. Pin Configuration

8

V

CC

B

7

A

6

GND

5

6012-002

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 RO Receiver Output. When enabled, if A > B by 200 mV, then RO = high. If A < B by 200 mV, then RO = low.
2

RE

Receiver Output Enable. A low level enables the receiver output, RO. A high level places the receiver output in a high
impedance state.

3 DE

Driver Output Enable. A high level enables the driver differential outputs, A and

B. A low level places the driver

differential outputs in a high impedance state.

4 DI

Driver Input. When the driver is enabled, a logic low on DI f

orces A low and B high. A logic high on DI forces

A high and B low.
5 GND Ground Connection, 0 V.
6 A Noninverting Receiver Input A/Driver Output A.
7 B Inverting Receiver Input B/Driver Output B.
8 VCC Power Supply, 5 V ± 10%.

Table 5. Selection Table

Part No. Duplex Data Rate (kbps) Low Power Shutdown Tx/Rx Enable ICC (μA) No. of Tx/Rx on Bus ESD kV

ADM483E Half 250 Yes Yes 36 32 ±15

Rev. A | Page 6 of 16

ADM483E

–

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TYPICAL PERFORMANCE CHARACTERISTICS

50

45

40

35

30

25

20

15

OUTPUT CURRENT (mA)

10

5

0

0 0.5 1. 0 1.5 2. 0 2.5

OUTPUT LOW VOLTAGE (V)

Figure 3. Output Current vs. R

eceiver Output Low Voltage

06012-003

0.9

0.8

0.7

0.6

0.5

0.4

0.3

OUTPUT LOW VOLTAGE (V)

0.2

0.1

0

–40 –20 0 20 40 60 80

TEMPERATURE (° C)

Figure 6. Receiver Output Low Voltage vs. Temperature

06012-006

30

–25

–20

–15

–10

OUTPUT CURRENT (mA)

–5

0

1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

OUTPUT HIGH VOLT AGE (V)

Figure 4. Output Current vs. Receiver Output High Voltage

4.5

4.4

4.3

4.2

4.1

OUTPUT HIGH VOLTAGE (V)

4.0

45

40

35

)
A
m

30

(
T

N
E

25

R
R
U
C

20

T
U
P

15

T
U
O

10

5

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5

6012-004

Figure 7. Driver Output Current v

2.3

2.2

2.1

2.0

1.9

1.8

1.7

DIFFERENTIAL OUTPUT VOLTAGE (V)

1.6

DIFFERENTIAL OUTPUT VOLTAGE (V)

s. Differential Output Voltage

06012-007

3.9
–40 –20 0 20 40 60 80

TEMPERATURE (° C)

06012-005

Figure 5. Receiver Output High Voltage vs. Temperature

Rev. A | Page 7 of 16

1.5
–40–200 20406080

TEMPERATURE ( °C)

Figure 8. Driver Differential Output Voltage vs. Temperature

06012-008

ADM483E

–

www.BDTIC.com/ADI

140

120

100

80

60

40

OUTPUT CURRENT (mA)

20

0

024681012

OUTPUT LOW VOLTAGE (V)

Figure 9. Output Current vs. Driv

140

–120

–100

er Output Low Voltage

06012-009

10

9

8

7

6

5

4

3

SHUTDOWN CURRENT (µA)

2

1

0

–60 –40 –20 0 20 40 60 80 100

TEMPERATURE (° C)

Figure 12. Shutdown Current vs. Temperature

06012-012

–80

–60

–40

OUTPUT CURRENT (mA)

–20

0

–8 –6 –4 –2 0 2 4 6

OUTPUT HIGH VOLT AGE (V)

Figure 10. Output Current vs. Driv

600

500

400

300

200

DE = VCC AND RE = x

SUPPLY CURRENT ( µA)

DE = 0 AND RE = 0
DE = 0 AND RE = V

100

0

–40 –20 0 20 40 60 80

CC

TEMPERATURE ( °C)

er Output High Voltage

Figure 11. ADM483E Supply Current vs. Temperature

2

1

06012-010

2

1

06012-011

A

CH1 5.00V
CH3 500mV

CH1 5.00V
CH3 500mV

B

RO

CH2 500mV M200n s A CH1 2. 80V

Figure 13. ADM483E Receiver t

CH2 500mV M200n s A CH1 2. 80V

Figure 14. ADM483E Receiver t

T 57.60%

T 60.80%

AB

RO

PHL

PLH

6012-013

06012-014

Driven by External RS-485 Device

Rev. A | Page 8 of 16

ADM483E

Y

V

V

V

V

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TEST CIRCUITS AND SWITCHING CHARACTERISTICS

CC

L

DZL

R

RL = 500Ω

VCC/2

, t

, t

DLZ

DZL(SHDN)

RECEIVER
OUTPUT

06012-020

t

OUT

5V

0V

0.5V

)

RPHL

+1V

–1V

DIFF

R

L

V

OD

V

R

L

Z

OC

6012-015

0V OR 5V

GENERATOR

D

50Ω

S1

C

Figure 15. Driver DC Test Load

5

DE

C

DI

A

V

OD

B

R

L

L

C

L

06012-016

Figure 16. Driver Timing Test Circuit

5

DI

1.5V

0V

B

V

O

A

1/2V

O

+V

O

0V

–V

10%

O

t

DR

Figure 17. Driver Propagation Delays

t

DPLH

V

DIFF

90% 90%

t

SKEW

t

DPHL

= V (A) – V (B)

=

t

– t

DPLH

DPHL

1/2 V

O

10%

t

DF

06012-017

DE

t

DZL,

t

DZL(SHDN)

V

CC

OUT

V

OL

2.3V

Figure 19. Driver Enable and Disable Times (t

ATE

V

Figure 20. Receiver Propagation Delay Test Circuit

A

RO

B

V

OH

V

OL

1.5V

THE RISE TIME AND FALL TIME OF INPUT A AND INPUT B < 4ns

t

RPLH

Figure 21. Receiver Propagation Delays

t

DLZ

B

ID

A

6012-019

06012-021

0 OR 5V

GENERATOR

DE

t

DZH(SHDN)

t

D

50Ω

DZH,

2.3VOUT

Figure 18. Driver Enable and Disable Times (t

S1

C

L

1.5V

t

DHZ

, t

DHZ

DZH

RL = 500Ω

0.5V

, t

DZH(SHDN)

OUT

5V

0V

V

0V

OH

06012-018

)

Rev. A | Page 9 of 16

ADM483E

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S3

0V OR 5V

GENERATOR

V

ID

+1.5V

50Ω

+5V

0V

V

0V

OH

+5V

0V

V

0V

1kΩ

C

L

15pF

RE

RO

RE

OH

RO

RE

RO

RE

RO

t

RZH,tRZH(SHDN)

+0.5V

+1.5V

–1.5V

S2 CLOSED

S1 OPEN

S2 CLOSED

S3 = +1.5V

+1.5V

t

S1 OPEN

S3 = +1.5V

RHZ

S1

S2

S1 CLOSED

S2 OPEN

S3 = –1.5V

t

RZL,tRZL(SHDN)

S1 CLOSED

S2 OPEN

S3 = +1.5V

+1.5V

t

RLZ

+0.5V

V

CC

+5V

+1.5V

0V

V

CC

+1.5V

V

OL

+5V

0V

V

CC

V

OL

06012-022

Figure 22. Receiver Enable and Disable Times

Rev. A | Page 10 of 16

ADM483E

V+5V

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GENERAL INFORMATION

The ADM483E is a robust RS-485 transceiver that operates
from a single 5 V supply.

It is ideally suited for operation in electrically harsh environ­m

ents or where cables may be plugged and unplugged. It is also
immune to high RF field strengths without special shielding
precautions. The ADM483E is intended for balanced data
transmission and complies with both EIA Standards RS-485 and
RS-422. It contains a differential line driver and a differential
line receiver; it is suitable for half-duplex data transmission
because the driver and receiver share the same differential pins.

The input impedance on the ADM483E is 12 kΩ, allowing up to
32 t

ransceivers on the differential bus.

The ADM483E operates from a single 5 V ± 10% power supply.
E

xcessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit.
This feature forces the driver output into a high impedance state
if, during fault conditions, a significant temperature increase is
detected in the internal driver circuitry.

The receiver has a fail-safe feature that results in a logic high
o

utput state if the inputs are unconnected (floating).

A high level of robustness is achieved using internal protection
ci

rcuitry, eliminating the need for external protection components

such as transorbs or surge suppressors.

Low electromagnetic emissions are achieved using slew limited

ivers, minimizing interference both conducted and radiated.

dr

The ADM483E can transmit at data rates up to 250 kbps.

A typical application for the ADM483E is illustrated in

igure shows a half-duplex link where data may be

This f
transferred at rates up to 250 kbps. A terminating resistor is
shown at both ends of the link. This termination is not critical
because the slew rate is controlled by the ADM483E and
reflections are minimized.

The communications network can be extended to include
m

ultipoint connections as shown in Figure 26. Up to 32

tra

nsceivers can be connected to the bus.

Figure 23.

+5

0.1µF0.1µF

V

GND

DE

CC

DI

E384MDAE384MDA

RO

RE

RE

RO

DI

DE

V

CC

B

A

RS-485/RS-422 LINK

GND

Figure 23. Typical Half-Duplex Link Application

B

A

Tabl e 6 and Ta b le 7 show the truth tables for transmitting and
receiving.

Table 6. Transmitting Truth Table

Inputs Outputs

DE DI B A

RE

X1 1 1 0 1
X1 1 0 1 0
0 0 X
1 0 X

1

X = don’t care.

1

High-Z High-Z

1

High-Z High-Z

Table 7. Receiving Truth Table

Inputs Outputs

RE

DE A − B RO

0 0 ≥ +0.2 V 1
0 0 ≤ −0.2 V 0
0 0 Inputs O/C
1 0 X

1

X = don’t care.

1

High-Z

1

ESD TRANSIENT PROTECTION SCHEME

The ADM483E uses protective clamping structures on its inputs
and outputs that clamp the voltage to a safe level and dissipate
the energy present in ESD (electrostatic discharge).

The protection structure achieves ESD protection up to ±15 kV

rding to the Human Body Model.

acco

06012-023

Rev. A | Page 11 of 16

ADM483E

www.BDTIC.com/ADI

ESD TESTING

Two coupling me t hods are us e d for ESD test i ng : contact
discharge and air-gap discharge. Contact discharge calls for a
direct connection to the unit being tested. Air-gap discharge
uses a higher test voltage but does not make direct contact with
the unit under test. With air-gap discharge, the discharge gun is
moved toward the unit under test, developing an arc across the
air gap. This method is influenced by humidity, temperature,
barometric pressure, distance, and rate of closure of the discharge
gun. The contact discharge method, though less realistic, is
more repeatable and is gaining acceptance and preference over
the air-gap method.

Although very little energy is contained within an ESD pulse,
t

he extremely fast rise time, coupled with high voltages, can
cause failures in unprotected semiconductors. Catastrophic
destruction may occur immediately as a result of arcing or
heating. Even if catastrophic failure does not occur immediately,
the device may suffer from parametric degradation, which can
result in degraded performance. The cumulative effects of
continuous exposure may eventually lead to complete failure.

HIGH

VOLTAGE

GENERATOR

ESD TEST METHOD

HUMAN BODY MO DELR21.5kΩ

Figure 24. ESD Generator

I/O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I/O cable can result in a static
discharge that may damage or completely destroy the interface
product connected to the I/O port.

R2

C1

DEVICE

UNDER TEST

C1

100pF

06012-024

It is, therefore, extremely important to have high levels of ESD
prote

ction on the I/O lines.

It is possible that the ESD discharge could induce latch-up in
t

he device under test. Therefore, it is important that ESD testing
on the I/O pins be carried out while device power is applied.
This type of testing is more representative of a real-world I/O
discharge where the equipment is operating normally when the
discharge occurs.

100%

90%

PEAK

I

36.8%

10%

TIME (

t

t

RL

Figure 25. Human Body Model ESD Current Waveform

t

DL

)

06012-025

Table 8. ADM483E ESD Test Results

ESD Test Method I/O Pins

Human Body Model: Air ±15 kV
Human Body Model: Contact ±8 kV

Rev. A | Page 12 of 16

ADM483E

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

DIFFERENTIAL DATA TRANSMISSION

Differential data transmission is used to reliably transmit data at
high rates over long distances and through noisy environments.
Differential transmission nullifies the effects of ground shifts
and noise signals that appear as common-mode voltages on the
line. There are two main standards approved by the Electronics
Industries Association (EIA) that specify the electrical character­istics of transceivers used in differential data transmission.

The RS-422 standard specifies data rates up to 10 MBaud and
l

ine lengths up to 4000 feet. A single driver can drive a transmission

line with up to 10 receivers.

To accommodate true multipoint communications, the RS-485

andard was defined. This standard meets or exceeds all the

st
requirements of RS-422 and also allows for up to 32 drivers and
32 receivers to be connected to a single bus. An extended
common-mode range of −7 V to +12 V is defined. The most
significant difference between RS-422 and RS-485 is the fact
that the drivers can be disabled, thereby allowing more than one
(32, in fact) to be connected to a single line. Only one driver
should be enabled at a time, but the RS-485 standard contains
additional specifications to guarantee device safety in the event
of line contention.

CABLE AND DATA RATE

The transmission line of choice for RS-485 communications is a
twisted pair. Twisted pair cable tends to cancel common-mode
noise and also cancels the magnetic fields generated by the
current flowing through each wire, thereby reducing the
effective inductance of the pair.

A typical application showing a multipoint transmission

twork is shown in Figure 26. An RS-485 transmission line can

ne

ve as many as 32 transceivers on the bus. Only one driver can

ha
transmit at a particular time, but multiple receivers can be
enabled simultaneously.

RT RT

D

R

D

Figure 26. Typical RS-485 Network

RR

D

D

R

06012-026

Rev. A | Page 13 of 16

ADM483E

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DES IGN.

85

1

1.27 (0.0500)

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012-A A

BSC

6.20 (0.2441)

5.80 (0.2284)

4

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.31 (0.0122)

8°
0°

0.25 (0.0098)

0.17 (0.0067)

0.50 (0.0196)

0.25 (0.0099)

1.27 (0.0500)

0.40 (0.0157)

45°

012407-A

Figure 27. 8-Lead Standard Small Outline Package [SOIC_N]

Nar

row Body

(R-8)

ensions shown in millimeters and (inches)

Dim

ORDERING GUIDE

Model Temperature Range Package Description Package Option Ordering Quantity

ADM483EAR –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8
ADM483EAR-REEL –40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 2500
ADM483EARZ
ADM483EARZ-REEL

1

Z = RoHS Compliant Part.

1

–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8

1

–40°C to +85°C 8-Lead Standard Small Outline Package (SOIC_N) R-8 2500

Rev. A | Page 14 of 16

ADM483E

www.BDTIC.com/ADI

NOTES

Rev. A | Page 15 of 16

ADM483E

www.BDTIC.com/ADI

NOTES

©1997–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06012-0-12/07(A)

Rev. A | Page 16 of 16