Analog Devices ADM483 Datasheet
5 V Low Power, Slew-Rate Limited
FEATURES
EIA RS-485/RS-422-compliant
Data rates up to 250 kbps
Slew-rate limited for low EMI
100 nA supply current in shutdown mode
Low power consumption (120 µA)
Up to 32 transceivers on one bus
Outputs high-z when disabled or powered off
–7 V to +12 V bus common-mode range
Thermal shutdown and short-circuit protection
Pin-compatible with MAX483
Specified over –40°C to +85°C temperature range
Available in 8-lead SOIC package
APPLICATIONS
Low power RS-485 applications
EMI sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
RS-485/RS-422 Transceiver
ADM483
FUNCTIONAL BLOCK DIAGRAM
V
CC
ADM483
RO
RE
DE
DI
R
D
GND
Figure 1.
A
B
05079-001
GENERAL DESCRIPTION
The ADM483 is a low power differential line transceiver suitable
for half-duplex data communication on multipoint bus transmission lines. It is designed for balanced data transmission, and
complies with EIA Standards RS-485 and RS-422.The part
contains a differential line driver and a differential line receiver.
Both share the same differential pins, with either the driver or
the receiver being enabled at any given time.
The device has an input impedance of 12 kΩ, allowing up to
32 transceivers on one bus. Since only one driver should be
enabled at any time, the output of a disabled or powered-down
driver is three-stated to avoid overloading the bus. This high
impedance driver output is maintained over the entire
common-mode voltage range from –7 V to +12 V.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
The receiver contains a fail-safe feature that results in a logic
high output state if the inputs are unconnected (floating).
The driver outputs are slew-rate limited to reduce EMI and data
errors caused by reflections from improperly terminated buses.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit.
The part is fully specified over the industrial temperature range,
and is available in an 8-lead SOIC package.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
www.analog.com
ADM483
TABLE OF CONTENTS
Specifications..................................................................................... 3
Timing Specifications....................................................................... 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configuration and Function Descriptions............................. 6
Test C ir c uit s ....................................................................................... 7
Switching Characteristics ................................................................ 8
Typical Performance Characteristics............................................. 9
REVISION HISTORY
10/04—Revision 0: Initial Version
Applications..................................................................................... 11
Differential Data Transmission ................................................ 11
Cable and Data Rate................................................................... 11
Thermal Shutdown .................................................................... 12
Receiver Open-Circuit Fail-Safe............................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
Rev. 0 | Page 2 of 16
ADM483
SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage, V
2.0 V R = 50 Ω (RS-422), Figure 3
1.5 5 V R = 27 Ω (RS-485), Figure 3
1.5 5 V V
∆ |VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 3
Common-Mode Output Voltage, V
∆ |VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, Figure 3
Output Short-Circuit Current, V
Output Short-Circuit Current, V
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low 0.8 V
CMOS Input Logic Threshold High 2.0 V
CMOS Logic Input Current (DI) ±2 µA
DE Input Resistance to GND
RECEIVER
Differential Input Threshold Voltage, V
Input Hysteresis 70 mV VCM = 0V
Input Resistance (A, B) 12 kΩ –7 V < VCM < +12 V
Input Current (A, B)
CMOS Logic Input Current (RE)
CMOS Output Voltage Low 0.4 V I
CMOS Output Voltage High 3.5 V I
Output Short-Circuit Current 7 95 mA 0 V < V
Three-State Output Leakage Current ±2 µA 0.4 ≤ V
POWER SUPPLY CURRENT 0.1 10 µA
120 250 µA
350 650 µA DE = VCC
MIN
to T
, unless otherwise noted.
MAX
OD
OC
= High 35 250 mA –7 V < V
OUT
= Low 35 250 mA –7 V < V
OUT
5 V
3 V R = 27 Ω or 50 Ω, Figure 3
220 kΩ
R = ∞, Figure 3
= –7 V to 12 V, Figure 4
TST
< +12 V
OUT
< +12 V
OUT
TH
–200 +200 mV –7 V < VCM < +12 V
1 mA VIN = +12 V
–0.8 mA VIN = –7 V
±2 µA
= 4 mA
OUT
= –4 mA
OUT
< V
OUT
≤ 2.4 V
OUT
DE = 0 V,
DE = 0 V,
RE = VCC (shutdown)
RE = 0 V
CC
Rev. 0 | Page 3 of 16
ADM483
TIMING SPECIFICATIONS
VCC = 5 V ± 5%, TA = T
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 250 kbps
Propagation Delay t
Skew t
SKEW
Rise/Fall Time tR, tF 200 2000 ns R
Enable Time 125 2000 ns RL = 500 Ω, CL = 100 pF, Figure 6
Disable Time 125 3000 ns RL = 500 Ω, CL = 15 pF, Figure 6
Enable Time from Shutdown 5000 ns RL = 500 Ω, CL = 100 pF, Figure 6
RECEIVER
Propagation Delay t
Differential Skew t
Enable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 8
Disable Time 20 50 ns RL = 1 kΩ, CL = 15 pF, Figure 8
Enable Time from Shutdown 5000 ns RL = 1 kΩ, CL = 15 pF, Figure 8
Time to Shutdown
1
The device is put into shutdown mode by driving RE high and DE low. If these inputs are in this state for less than 50 ns, the device is guaranteed not to enter
shutdown mode. If the enable inputs are in this state for at least 3000 ns, the device is guaranteed to have entered shutdown mode.
SKEW
1
PLH
PLH
MIN
to T
, t
, t
, unless otherwise noted.
MAX
250 800 2000 ns R
PHL
100 800 ns R
250 2000 ns CL = 15 pF, Figure 7
PHL
LDIFF
LDIFF
LDIFF
100 ns CL = 15 pF, Figure 7
50 330 3000 ns
= 54 Ω, CL1 = CL2 = 100 pF, Figure 5
= 54 Ω, CL1 = CL2 = 100 pF, Figure 5
= 54 Ω, CL1 = CL2 = 100 pF, Figure 5
Rev. 0 | Page 4 of 16
ADM483
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC to GND 6 V
Digital I/O Voltage (DE, RE, DI, ROUT)
Driver Output/Receiver Input Voltage –9 V to +14 V
Operating Temperature Range –40°C to +85°C
Storage Temperature Range –65°C to +125°C
θJA Thermal Impedance (SOIC) 110°C/W
Lead Temperature
Soldering (10 s) 300°C
Vapor Phase (60 s) 215°C
Infrared (15 s) 220°C
–0.3 V to V
+ 0.3 V
CC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 16
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