ANALOG DEVICES ADM3493 Service Manual
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V
3.3 V Slew Rate Limited,
Half Duplex RS-485/RS-422 Transceiver
FEATURES
Operates with 3.3 V supply
Interoperable with 5 V logic
EIA RS-422 and RS-485 compliant over full CM range
Data rate: 250 kbps
Half duplex transceiver
Reduced slew rates for low EMI
2 nA supply current in shutdown mode
Up to 256 transceivers on a bus
−7 V to +12 V bus common-mode range
Specified over −40°C to +85°C temperature range
8 ns skew
Available in 8-lead SOIC
APPLICATIONS
Low power RS-485 applications
EMI sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
ADM3493
FUNCTIONAL BLOCK DIAGRAM
CC
ADM3493
RO
RE
DE
DI
R
D
GND
Figure 1.
A
B
05715-001
GENERAL DESCRIPTION
The ADM3493 is a low power, differential line transceiver
designed to operate using a single 3.3 V power supply. Low
power consumption, coupled with a shutdown mode, makes it
ideal for power-sensitive applications. The ADM3493 is suitable
for communication on multipoint bus transmission lines.
The device contains one driver and one receiver. Designed for
half-duplex communication, the ADM3493 features a slew rate
limited driver that minimizes EMI and reduces reflections
caused by improperly terminated cables, allowing error-free
data transmission at data rates up to 250 kbps.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The receiver input impedance is 96 kΩ, allowing up to 256
transceivers to be connected on the bus. A thermal shutdown
circuit prevents excessive power dissipation caused by bus
contention or by output shorting. If a significant temperature
increase is detected in the internal driver circuitry during fault
conditions then the thermal shutdown circuit forces the driver
output into a high impedance state. The receiver contains a failsafe feature that results in a logic high output state, if the inputs
are unconnected (floating).
The ADM3493 is fully specified over the commercial and
industrial temperature ranges and is available in an 8-lead SOIC.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
ADM3493
TABLE OF CONTENTS
Features.............................................................................................. 1
Switching Characteristics .................................................................8
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Test Circuits....................................................................................... 7
REVISION HISTORY
10/05—Rev. 0: Initial Version
Typical Performance Characteristics..............................................9
Circuit Description......................................................................... 11
Reduced EMI and Reflections .................................................. 11
Low Power Shutdown Mode..................................................... 11
Driver Output Protection.......................................................... 11
Propagation Delay...................................................................... 11
Typical Applications................................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. 0 | Page 2 of 12
ADM3493
SPECIFICATIONS
VCC = 3.3 V ±0.3 V, TA = T
Table 1.
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD 2.0 V
1.5 V RL = 54 Ω (RS-485) (see Figure 3)
1.5 V
Δ |VOD| for Complementary Output States
Common-Mode Output Voltage, VOC 3 V RL = 54 Ω or 100 Ω (see Figure 3)
Δ |VOC| for Common-Mode Output Voltage1
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low, VIH 0.8 V
CMOS Input Logic Threshold High, VIL 2.0 V
CMOS Logic Input Current, IN1 ±2 µA
RECEIVER
Differential Input Threshold Voltage, VTH −0.2 0.2 V −7V < V
Input Hysteresis, Δ VTH
CMOS Output Voltage High, VOH V
CMOS Output Voltage Low, VOL 0.4 V
Three-State Output Leakage Current, I
Input Resistance, RIN 96 kΩ −7 V < V
POWER SUPPLY CURRENT
Supply Current
Supply Current in Shutdown Mode, I
Receiver Short-Circuit Output Current, I
1
ΔVOD and ΔV
are the changes in V
OC
to T
MIN
, unless otherwise noted.
MAX
1
cc
±1 µA
OZR
0.002 1 µA
SHDN
OSD
±8 ±60 mA 0 V < VRO < VCC
OSR
and VOC, respectively, when DI input changes state.
OD
= 100 Ω (RS-422), Vcc = 3.3 V
R
L
±5% (see
R
L
(see
Figure 3)
= 60 Ω (RS-485), Vcc = 3.3 V
Figure 4)
0.2 V RL = 54 Ω or 100 Ω (see Figure 3)
0.2 V R
60 µA VIN = 12 V Input Current (A, B), IN2
−60 µA VIN = −7 V
= 54 Ω or 100 Ω (see Figure 3)
L
RE
DE, DI,
RE
DE, DI,
RE
DE, DI,
DE = 0 V
V
= 0 V or 3.6 V
CC
< + 12 V
CM
50 mV VCM = 0 V
– 0.4 V
= −1.5 mA, VID = 200 mV
I
OUT
(see
Figure 5)
= 2.5mA, VID = 200mV
I
OUT
Figure 5)
(see
Vcc = 3.6 V, 0 V ≤ V
CM
OUT
< + 12 V
≤ Vcc
DE = VCC 1.1 2.2 mA
RE = 0 V or VCC
0.95 1.9 mA
DE = VCC
No load,
DI = 0 V or V
RE = 0 V
DE = 0 V, RE = VCC, DI = VCC or 0 V
−250 mA V
250 mA V
OUT
OUT
= −7 V Driver Short-Circuit Output Current, I
= 12 V
CC
Rev. 0 | Page 3 of 12
ADM3493
TIMING SPECIFICATIONS
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Differential Output Delay, tDD 600 900 1400 ns
Differential Output Transition Time, tTD 400 700 1200 ns
Propagation Delay, Low-to-High Level, t
Propagation Delay, High-to-Low Level, t
|t
– t
| Propagation Delay Skew1, t
PLH
PHL
700 1000 1500 ns
PLH
700 1000 1500 ns
PHL
100 ns RL = 27 Ω (see Figure 7 and Figure 13)
PDS
DRIVER OUTPUT ENABLE/DISABLE TIMES
Output Enable Time to Low Level, t
Output Enable Time to High Level, t
Output Disable Time from High Level, t
Output Disable Time from Low Level, t
Output Enable Time from Shutdown to
Low Level, t
PSL
Output Enable Time from Shutdown to
High Level, t
PSH
900 1300 ns
PZL
600 800 ns
PZH
50 80 ns
PHZ
50 80 ns
PLZ
1.9 2.7 s
2.2 3.0 s
RECEIVER
Time to Shutdown2, t
Propagation Delay, Low-to-High Level, t
Propagation Delay, High-to-Low Level, t
|t
– t
| Propagation Delay Skew, t
PLH
PHL
80 190 300 ns
SHDN
25 75 180 ns
RPLH
25 75 180 ns
RPHL
50 ns
RPDS
RECEIVER OUTPUT ENABLE/DISABLE TIMES
Output Enable Time to Low Level, t
Output Enable Time to High Level, t
Output Disable Time from High Level, t
Output Disable Time from Low Level, t
Output Enable Time from Shutdown to
Low Level, t
PRSL
Output Enable Time from Shutdown to
PLH
PRSH
(A) − t
(A)| and |t
PHL
PLH
High Level, t
1
Measured on |t
2
The transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to enter
shutdown. If the inputs are in this state for at least 300 ns, the parts are guaranteed to enter shutdown.
25 50 ns CL = 15 pF (see Figure 11 and Figure 17)
PRZL
25 50 ns CL = 15 pF (see Figure 11 and Figure 17)
PRZH
25 45 ns CL = 15 pF (see Figure 11 and Figure 17)
PRHZ
25 45 ns CL = 15 pF (see Figure 11 and Figure 17)
PRLZ
720 1400 ns C
720 1400 ns C
(B) − t
(B)|.
PHL
RL = 60 Ω (see Figure 6 and Figure 12)
RL = 60 Ω (see Figure 6 and Figure 12)
RL = 27 Ω (see Figure 7 and Figure 13)
RL = 27 Ω (see Figure 7 and Figure 13)
RL = 110 Ω (see Figure 9 and Figure 15)
RL = 110 Ω (see Figure 8 and Figure 14)
R
= 110 Ω (see Figure 8 and Figure 14)
L
RL = 110 Ω (see Figure 9 and Figure 15)
= 110 Ω (see Figure 9 and Figure 15)
R
L
= 110 Ω (see Figure 8 and Figure 14)
R
L
= 0 V to 3.0 V, CL = 15 pF (see Figure 10
V
ID
Figure 16)
and
= 0 V to 3.0 V, CL = 15 pF (see Figure 10
V
ID
and
Figure 16)
= 0 V to 3.0 V, CL = 15 pF (see Figure 10
V
ID
Figure 16)
and
= 15 pF (see Figure 11 and Figure 17)
L
= 15 pF (see Figure 11 and Figure 17)
L
Rev. 0 | Page 4 of 12
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