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V
3.3 V Slew Rate Limited,
Half Duplex RS-485/RS-422 Transceiver
FEATURES
Operates with 3.3 V supply
Interoperable with 5 V logic
EIA RS-422 and RS-485 compliant over full CM range
Data rate: 250 kbps
Half duplex transceiver
Reduced slew rates for low EMI
2 nA supply current in shutdown mode
Up to 256 transceivers on a bus
−7 V to +12 V bus common-mode range
Specified over −40°C to +85°C temperature range
8 ns skew
Available in 8-lead SOIC
APPLICATIONS
Low power RS-485 applications
EMI sensitive systems
DTE-DCE interfaces
Industrial control
Packet switching
Local area networks
Level translators
ADM3493
FUNCTIONAL BLOCK DIAGRAM
CC
ADM3493
RO
RE
DE
DI
R
D
GND
Figure 1.
A
B
05715-001
GENERAL DESCRIPTION
The ADM3493 is a low power, differential line transceiver
designed to operate using a single 3.3 V power supply. Low
power consumption, coupled with a shutdown mode, makes it
ideal for power-sensitive applications. The ADM3493 is suitable
for communication on multipoint bus transmission lines.
The device contains one driver and one receiver. Designed for
half-duplex communication, the ADM3493 features a slew rate
limited driver that minimizes EMI and reduces reflections
caused by improperly terminated cables, allowing error-free
data transmission at data rates up to 250 kbps.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The receiver input impedance is 96 kΩ, allowing up to 256
transceivers to be connected on the bus. A thermal shutdown
circuit prevents excessive power dissipation caused by bus
contention or by output shorting. If a significant temperature
increase is detected in the internal driver circuitry during fault
conditions then the thermal shutdown circuit forces the driver
output into a high impedance state. The receiver contains a failsafe feature that results in a logic high output state, if the inputs
are unconnected (floating).
The ADM3493 is fully specified over the commercial and
industrial temperature ranges and is available in an 8-lead SOIC.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005 Analog Devices, Inc. All rights reserved.
ADM3493
TABLE OF CONTENTS
Features.............................................................................................. 1
Switching Characteristics .................................................................8
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 4
Absolute Maximum Ratings............................................................ 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
Test Circuits....................................................................................... 7
REVISION HISTORY
10/05—Rev. 0: Initial Version
Typical Performance Characteristics..............................................9
Circuit Description......................................................................... 11
Reduced EMI and Reflections .................................................. 11
Low Power Shutdown Mode..................................................... 11
Driver Output Protection.......................................................... 11
Propagation Delay...................................................................... 11
Typical Applications................................................................... 11
Outline Dimensions....................................................................... 12
Ordering Guide .......................................................................... 12
Rev. 0 | Page 2 of 12
ADM3493
SPECIFICATIONS
VCC = 3.3 V ±0.3 V, TA = T
Table 1.
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Differential Output Voltage, VOD 2.0 V
1.5 V RL = 54 Ω (RS-485) (see Figure 3)
1.5 V
Δ |VOD| for Complementary Output States
Common-Mode Output Voltage, VOC 3 V RL = 54 Ω or 100 Ω (see Figure 3)
Δ |VOC| for Common-Mode Output Voltage1
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low, VIH 0.8 V
CMOS Input Logic Threshold High, VIL 2.0 V
CMOS Logic Input Current, IN1 ±2 µA
RECEIVER
Differential Input Threshold Voltage, VTH −0.2 0.2 V −7V < V
Input Hysteresis, Δ VTH
CMOS Output Voltage High, VOH V
CMOS Output Voltage Low, VOL 0.4 V
Three-State Output Leakage Current, I
Input Resistance, RIN 96 kΩ −7 V < V
POWER SUPPLY CURRENT
Supply Current
Supply Current in Shutdown Mode, I
Receiver Short-Circuit Output Current, I
1
ΔVOD and ΔV
are the changes in V
OC
to T
MIN
, unless otherwise noted.
MAX
1
cc
±1 µA
OZR
0.002 1 µA
SHDN
OSD
±8 ±60 mA 0 V < VRO < VCC
OSR
and VOC, respectively, when DI input changes state.
OD
= 100 Ω (RS-422), Vcc = 3.3 V
R
L
±5% (see
R
L
(see
Figure 3)
= 60 Ω (RS-485), Vcc = 3.3 V
Figure 4)
0.2 V RL = 54 Ω or 100 Ω (see Figure 3)
0.2 V R
60 µA VIN = 12 V Input Current (A, B), IN2
−60 µA VIN = −7 V
= 54 Ω or 100 Ω (see Figure 3)
L
RE
DE, DI,
RE
DE, DI,
RE
DE, DI,
DE = 0 V
V
= 0 V or 3.6 V
CC
< + 12 V
CM
50 mV VCM = 0 V
– 0.4 V
= −1.5 mA, VID = 200 mV
I
OUT
(see
Figure 5)
= 2.5mA, VID = 200mV
I
OUT
Figure 5)
(see
Vcc = 3.6 V, 0 V ≤ V
CM
OUT
< + 12 V
≤ Vcc
DE = VCC 1.1 2.2 mA
RE = 0 V or VCC
0.95 1.9 mA
DE = VCC
No load,
DI = 0 V or V
RE = 0 V
DE = 0 V, RE = VCC, DI = VCC or 0 V
−250 mA V
250 mA V
OUT
OUT
= −7 V Driver Short-Circuit Output Current, I
= 12 V
CC
Rev. 0 | Page 3 of 12
ADM3493
TIMING SPECIFICATIONS
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 2.
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Differential Output Delay, tDD 600 900 1400 ns
Differential Output Transition Time, tTD 400 700 1200 ns
Propagation Delay, Low-to-High Level, t
Propagation Delay, High-to-Low Level, t
|t
– t
| Propagation Delay Skew1, t
PLH
PHL
700 1000 1500 ns
PLH
700 1000 1500 ns
PHL
100 ns RL = 27 Ω (see Figure 7 and Figure 13)
PDS
DRIVER OUTPUT ENABLE/DISABLE TIMES
Output Enable Time to Low Level, t
Output Enable Time to High Level, t
Output Disable Time from High Level, t
Output Disable Time from Low Level, t
Output Enable Time from Shutdown to
Low Level, t
PSL
Output Enable Time from Shutdown to
High Level, t
PSH
900 1300 ns
PZL
600 800 ns
PZH
50 80 ns
PHZ
50 80 ns
PLZ
1.9 2.7 s
2.2 3.0 s
RECEIVER
Time to Shutdown2, t
Propagation Delay, Low-to-High Level, t
Propagation Delay, High-to-Low Level, t
|t
– t
| Propagation Delay Skew, t
PLH
PHL
80 190 300 ns
SHDN
25 75 180 ns
RPLH
25 75 180 ns
RPHL
50 ns
RPDS
RECEIVER OUTPUT ENABLE/DISABLE TIMES
Output Enable Time to Low Level, t
Output Enable Time to High Level, t
Output Disable Time from High Level, t
Output Disable Time from Low Level, t
Output Enable Time from Shutdown to
Low Level, t
PRSL
Output Enable Time from Shutdown to
PLH
PRSH
(A) − t
(A)| and |t
PHL
PLH
High Level, t
1
Measured on |t
2
The transceivers are put into shutdown by bringing RE high and DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to enter
shutdown. If the inputs are in this state for at least 300 ns, the parts are guaranteed to enter shutdown.
25 50 ns CL = 15 pF (see Figure 11 and Figure 17)
PRZL
25 50 ns CL = 15 pF (see Figure 11 and Figure 17)
PRZH
25 45 ns CL = 15 pF (see Figure 11 and Figure 17)
PRHZ
25 45 ns CL = 15 pF (see Figure 11 and Figure 17)
PRLZ
720 1400 ns C
720 1400 ns C
(B) − t
(B)|.
PHL
RL = 60 Ω (see Figure 6 and Figure 12)
RL = 60 Ω (see Figure 6 and Figure 12)
RL = 27 Ω (see Figure 7 and Figure 13)
RL = 27 Ω (see Figure 7 and Figure 13)
RL = 110 Ω (see Figure 9 and Figure 15)
RL = 110 Ω (see Figure 8 and Figure 14)
R
= 110 Ω (see Figure 8 and Figure 14)
L
RL = 110 Ω (see Figure 9 and Figure 15)
= 110 Ω (see Figure 9 and Figure 15)
R
L
= 110 Ω (see Figure 8 and Figure 14)
R
L
= 0 V to 3.0 V, CL = 15 pF (see Figure 10
V
ID
Figure 16)
and
= 0 V to 3.0 V, CL = 15 pF (see Figure 10
V
ID
and
Figure 16)
= 0 V to 3.0 V, CL = 15 pF (see Figure 10
V
ID
Figure 16)
and
= 15 pF (see Figure 11 and Figure 17)
L
= 15 pF (see Figure 11 and Figure 17)
L
Rev. 0 | Page 4 of 12
ADM3493
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VCC to GND 7 V
Digital I/O Voltage (DE, RE, DI)
Digital I/O Voltage (R
Driver Output/Receiver Input Voltage −7.5 V to +12.5 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
θJA Thermal Impedance
8-Lead SOIC 121°C/W
Lead Temperature
Soldering (10 seconds) 300°C
Vapor Phase (60 seconds) 215°C
Infrared (15 seconds) 220°C
) VCC − 0.5 V to VCC + 0.5 V
OUT
−0.3 V to VCC + 0.3 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 12
ADM3493
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RO
1
ADM3493
RE
2
TOP VIEW
DE
3
(Not to Scale)
4
DI
Figure 2. Pin Configuration
Table 4. . Pin Function Descriptions
Pin No. Mnemonic Description
1 RO
Receiver Output. When enabled, if A > B by 200 mV, then RO = high.
If A < B by 200 mV, then RO = low.
2
RE Receiver Output Enable. A low level enables the receiver output, RO. A high level
places it in a high impedance state. If RE is high and DE is low, the device enters a low
power shutdown mode.
3 DE
Driver Output Enable. A high level enables the driver differential Outputs A and B.
A low level places it in a high impedance state. If
enters a low power shutdown mode.
4 DI
Driver Input. When the driver is enabled, a logic low on DI forces A low and B high
while a logic high on DI forces A high and B low.
5 GND Ground.
6 A Noninverting Receiver Input A and Noninverting Driver Output A.
7 B Inverted Receiver Input B and Inverted Driver Output B.
8 VCC Power Supply, 3.3 V ± 0.3 V.
V
8
CC
B
7
A
6
5
GND
05715-002
RE is high and DE is low, the device
Rev. 0 | Page 6 of 12
ADM3493
2
V
V
2
TEST CIRCUITS
A
B
D
V
CC
Figure 4. Driver V
RL/2
V
OD
V
/2
R
OC
L
05715-003
Figure 3. Driver V
V
OD
with Varying Common-Mode Voltage
OD
OD
375
R
L
375
and VOC
VCM=
–7V TO +12V
0V OR 3V
GENERATOR
1
PPR = 250kHz , 50% DUT Y CYCLE,
2
CL INCLUDES PROBE AND STRAY CAPACITANCE.
1
50
Figure 8. Driver Enable and Disable Times (t
05715-004
0V OR 3V
S1
D
2
C
= 50pF
L
V
OH+VOL
=
V
OM
2
t
6.0ns, ZO=50.
R
S1
D
2
C
=50pF
L
1.5V
PZH
RL= 110
, t
, t
PSH
CC
RL= 110
OUT
PHZ
OUT
05715-008
)
R
V
ID
0
V
OL
Figure 5. Receiver V
D
GENERATOR
1
PPR = 250kHz, 50% DUTY CYCLE,
CL INCLUDES PROBE AND STRAY CAP ACITANCE.
1
50
V
CC
V
I
OH
OL
(+)
and V
OH
OL
C
L
CL= 15pF
t
6.0ns, ZO=50.
R
Figure 6. Driver Differential Output Delay and Transition Times
S1
D
GENERATOR
1
PPR = 250kHz, 50% DUTY CY CLE,
2
CL INCLUDES PROBE AND STRAY CAP ACITANCE.
1
50
V
CC
V
OH+VOL
V
OM
=
1.5V
2
t
6.0ns, ZO=50.
R
Figure 7. Driver Propagation Delays
C
RL=
60
L
2
OM
RL=27
= 15pF
OUT
I
OH
(–)
OUT
2
1.5V
1
50
t
6.0ns, ZO=50.
R
, t
PZL
PSL
V
1
50
0
ID
t
R
OUT
R
C
VOM=
6.0ns, ZO=50.
L
V
, t
= 15pF
CC
2
05715-009
)
PLZ
2
05715-010
GENERATOR
1
PPR = 250kHz , 50% DUT Y CYCLE,
2
5715-005
05715-006
CL INCLUDES PROBE AND STRAY CAPACITANCE.
Figure 9. Driver Enable and Disable Times (t
GENERATOR
1
PPR = 250kHz , 50% DUT Y CYCLE,
2
CL INCLUDES PROBE AND STRAY CAP ACITANCE.
Figure 10. Receiver Propagation Delay
+1.5V
–1.5V
1
PPR = 250kHz, 50% DUT Y CYCLE,
05715-007
CL INCLUDES PROBE AND ST RAY CAPACITANCE.
S3
GENERATOR
V
R
ID
1
50
t
6.0ns, ZO=50.
R
1k
2
C
L
S1
S2
V
CC
05715-011
Figure 11. Receiver Enable and Disable Times
Rev. 0 | Page 7 of 12
ADM3493
V
V
V
V
V
V
V
SWITCHING CHARACTERISTICS
V
t
PLZ
OM
+1.5V
0.25V
t
RPHL
t
PRLZ
3
0
V
CC
V
OL
05715-015
, t
, t
PZL
)
PSL
PLZ
3
0
V
CC
0
05715-016
+3
S1 CLOSED
S2 OPEN
+1.5V
S3 = –1.5V
+1.5V
0
V
CC
V
OL
+3V
0
V
CC
V
OL
S1 CLOSED
S2 OPEN
S3 = –1.5V
t
PRZL
t
PRSL
+3
IN
1.5V 1. 5V
0
t
DD
+2V
50%50%
10%10%
–2V
t
TD
05715-012
OUT
t
DD
90%90%
t
TD
Figure 12. Driver Differential Output Delay and Transition Times
3
IN
1.5V 1.5V
0V
t
PHL
V
V
OM
V
OM
OH
V
OL
t
PLH
V
OH
V
OL
05715-013
A
OUT
B
OUT
t
PLH
V
OM
t
PHL
V
OM
Figure 13. Driver Propagation Delays
3
IN
t
PZH
OUT
Figure 14. Driver Enable and Disable Times (t
1.5V1.5V
0
t
PHZ
V
OM
0.25V
PZH
V
OH
0
05715-014
, t
, t
)
PSH
PHZ
OUT
IN
OUT
1.5V 1. 5V
t
PSL
V
OM
Figure 15. Driver Enable and Disable Times (t
IN
t
RPLH
OUT
V
OM
Figure 16. Receiver Propagation Delay
+3
S1 OPEN
0
V
OH
0
+3V
0
V
OH
0
S2 CLOSED
S3 = +1.5V
S1 OPEN
S2 CLOSED
S3 = +1.5V
OUT
IN
IN
+0.25V
+1.5V
t
t
PRSH
t
+1.5V
PRZH
+1.5V
PRHZ
Figure 17. Receiver Enable and Disable Times
1.5V1.5V
IN
OUT
IN
OUT
+0.25V
5715-017
Rev. 0 | Page 8 of 12
ADM3493
–
TYPICAL PERFORMANCE CHARACTERISTICS
30
0.8
25
20
15
10
OUTPUT CURRENT ( mA)
5
0
03
0.51.01.52.02.53.0 –30 –20 –10 0 10 20 30 40 50 60 70 80
OUTPUT VOLTAGE (V)
05715-018
.5
Figure 18. Output Current vs. Receiver Output Low Voltage
16
–14
–12
–10
–8
–6
OUTPUT CURRENT ( mA)
–4
–2
0
03
0.51.01.52.02.53.0
OUTPUT VOLTAGE (V)
05715-019
.5
Figure 19. Output Current vs. Receiver Output High Voltage
0.7
0.6
0.5
0.4
0.3
OUTPUT VOLTAGE (V)
0.2
0.1
0
–40
Figure 21. Receiver Output Low Voltage vs. Temperature, IO = 2.5 mA
100
90
80
70
60
50
40
30
OUTPUT CURRENT ( mA)
20
10
0
03.5
0.51.01.52.02.53.0
Figure 22. Driver Output Current vs. Differential Output Voltage
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
05715-021
05715-022
3.30
3.25
3.20
3.15
3.10
OUTPUT VOLTAGE (V)
3.05
3.00
–40
–30 –20 –10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 20. Receiver Output High Voltage vs. Temperature, IO = 1.5 mA
05715-020
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
OUTPUT VOLTAGE (V)
1.8
1.7
1.6
–40
–30 –20 –10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
05715-023
Figure 23. Driver Differential Output Voltage vs. Temperature, RI = 54 Ω
Rev. 0 | Page 9 of 12
ADM3493
–
140
120
100
80
60
40
OUTPUT CURRENT ( mA)
20
0
01
246810
OUTPUT VOLTAGE (V)
05715-024
2
Figure 24. Output Current vs. Driver Output Low Voltage
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
SUPPLY CURRENT (mA)
0.4
0.3 DE = RE = GND
0.2
–40
–30 –20 –10 0 10 20 30 40 50 60 70 80
DE = RE = X*
TEMPERATURE (°C)
Figure 26. Supply Current vs. Temperature
*X = DON’ T CARE
05715-026
125
–115
–105
–95
–85
–75
–65
–55
–45
–35
OUTPUT CURRENT ( mA)
–25
–15
–5
–7 3
–6 –5 –4 –3 –2 –1 0 1 2
OUTPUT VOLTAGE (V)
Figure 25. Output Current vs. Driver Output High Voltage
05715-025
100
90
80
70
60
50
40
30
20
SHUTDOWN CURRENT ( nA)
10
0
–10
–40
–30 –20 –10 0 10 20 30 40 50 60 70 80
TEMPERATURE (°C)
Figure 27. Shutdown Current vs. Temperature, VCC = 3.3 V
05715-027
Rev. 0 | Page 10 of 12
ADM3493
CIRCUIT DESCRIPTION
The ADM3493 is a low power transceiver for RS-485 and
RS-422 communications. The ADM3493 can transmit and
receive at data rates up to 250 kbps in a half duplex
configuration. Driver Enable (DE) and Receiver Enable (
RE
)
pins are included when disabled; the driver and receiver
outputs are high impedance.
Table 5. Transmitting Truth Table
Transmitting Inputs Transmitting
Mode
Outputs
RE
DE DI B A
X1 1 1 0 1 Normal
X1 1 0 1 0 Normal
0 0 X1 High-Z2 High-Z2 Normal
1 0 X1 High-Z2 High-Z2 Shutdown
1
X = Don’t care.
2
High-Z = High Impedance.
Table 6. Receiving Truth Table
Receiving Inputs Receiving
Mode
Outputs
RE
DE A - B RO
0 0 ≥+0.2 V 1 Normal
0 0 ≤−0.2 V 0 Normal
0 0 Inputs Open 1 Normal
1 0 X1 High-Z2 Shutdown
1
X = Don’t care.
2
High-Z = High Impedance
REDUCED EMI AND REFLECTIONS
The ADM3493 is a slew rate limited transceiver, minimizing
EMI and reducing reflections caused by improperly terminated
cables.
ADM3493 ADM3493
RO
RE
DE
DI
R
D
V
CC
R1
A
R
T
B
R2
ADM3493 ADM3493
MAXIMUM NUMBER OF T RANSCEIVERS ON BUS = 256
A
B
LOW POWER SHUTDOWN MODE
A low power shutdown mode is initiated by bringing both RE
high and DE low. The ADM3493 does not shut down unless
both the driver and receiver are disabled (high impedance). In
shutdown, the ADM3493 typically draws only 2 nA of supply
current. For the ADM3493, the t
the part was in the low power shutdown mode; the t
PSH
and t
enable times assume
PSL
and t
PZH
PZL
enable times assume the receiver or driver was disabled, but the
part was not shut down.
DRIVER OUTPUT PROTECTION
Two methods are implemented to prevent excessive output
current and power dissipation caused by faults or by bus
contention. Current limit protection on the output stage
provides immediate protection against short circuits over the
whole common-mode voltage range (see
Characteristics
). In addition, a thermal shutdown circuit forces
Typical Perfor m an c e
the driver outputs into a high impedance state if the die
temperature rises excessively.
PROPAGATION DELAY
Skew time is simply the difference between the low-to-high and
high-to-low propagation delay. Small driver/receiver skew times
help maintain a symmetrical mark-space ratio (50% duty cycle).
- t
The receiver skew time, |t
PRLH
|, is 20 ns for the ADM3493.
PRHL
The driver skew time is typically under 100 ns.
TYPICAL APPLICATIONS
The ADM3493 transceiver is designed for bidirectional data
communications on multipoint bus transmission lines. Figure
22 shows a typical network application’s circuits. To minimize
reflections, the line should be terminated at both ends in its
characteristic impedance, and stub lengths off the main line
should be kept as short as possible. The slew rate limited
ADM3493 is tolerant of imperfect termination.
A
R
T
B
A
B
R
RO
RE
DE
D
DI
R
RO
RE DI
NOTES
1. R
IS EQUAL T O THE CHARACTERISTIC IM PEDANCE OF THE CABLE.
T
D
DE
Figure 28. ADM3493 Typical Half Duplex RS-485 Network
Rev. 0 | Page 11 of 12
RO
R
RE
D
DIDE
05715-028
ADM3493
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
85
6.20 (0.2440)
5.80 (0.2284)
41
ORDERING GUIDE
Model
ADM3493ARZ1
ADM3493ARZ-REEL71
1
Z = Pb-free part.
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-AA
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
Figure 29. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
Temperature Range Package Description
−40°C to +85°C
−40°C to +85°C
8-Lead Standard Small Outline Package [SOIC_N] R-8
8-Lead Standard Small Outline Package [SOIC_N] R-8 1,000
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
8°
1.27 (0.0500)
0°
0.40 (0.0157)
× 45°
Package Options
Ordering
Quantity
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05715-0-10/05(0)
Rev. 0 | Page 12 of 12
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