ANALOG DEVICES ADM3483E, ADM3488E, ADM3490E, ADM3491E Service Manual

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V

V

V

3.3 V, ±15 kV ESD-Protected, Half- and

Full-Duplex, RS-485/RS-422 Transceivers

ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E

FEATURES

TIA/EIA RS-485/RS-422 compliant
±15 kV ESD protection on RS-485 input/output pins
Data rates

ADM3483E/ADM3488E: 250 kbps
ADM3486E: 2.5 Mbps

ADM3490E/ADM3491E: 12 Mbps
Half- and full-duplex options
Up to 32 nodes on the bus
Receiver open-circuit, fail-safe design
Low power shutdown current

(ADM3483E/ADM3486E/ADM3491E only)
Outputs high-Z when disabled or powered off
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
Industry-standard 75176 pinout
8-lead and 14-lead narrow SOIC packages

APPLICATIONS

Power/energy metering
Telecommunications
EMI-sensitive systems
Industrial control
Local area networks

GENERAL DESCRIPTION

The ADM3483E/ADM3486E/ADM3488E/ADM3490E/
ADM3491E are 3.3 V, low power data transceivers with
±15 kV ESD protection suitable for full- and half-duplex
communication on multipoint bus transmission lines. They
are designed for balanced data transmission, and they
comply with TIA/EIA standards RS485 and RS-422. The
ADM3483E/ADM3486E are half-duplex transceivers that
share differential lines and have separate enable inputs for
the driver and receiver. The full-duplex ADM3488E/
ADM3490E/ADM3491E transceivers have dedicated
differential line driver outputs and receiver inputs. The
ADM3491E also features separate enable inputs for the
driver and receiver.

The devices have a 12 kΩ receiver input impedance,
which allows up to 32 transceivers on a bus. Because only
one driver should be enabled at any time, the output of a
disabled or powered-down driver is tristated to avoid
overloading the bus.

FUNCTIONAL BLOCK DIAGRAMS

CC

ADM3483E/
ADM3486E

RO

RE

DE

DI

RO

DI

RO

RE

DE

DI

R

D

GND

Figure 1.

CC

ADM3488E/
ADM3490E

R

D

GND

Figure 2.

CC

ADM3491E

R

D

GND

Figure 3.

A

B

6284-001

A

B

Z

Y

6284-002

A

B

Z

Y

06284-003

(continued on Page 3)

Rev. A

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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams............................................................. 1

Revision History ............................................................................... 2

Specifications..................................................................................... 4

Driver Timing Specifications...................................................... 5

Receiver Timing Specifications .................................................. 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Test Circuits and Switching Characteristics.................................. 9

Typical Performance Characteristics ........................................... 11

Circuit Description......................................................................... 14

Devices with Receiver/Driver Enable—ADM3483E/

ADM3486E/ ADM3491E ........................................................... 14

Devices Without Receiver/Driver Enable― ADM3488E/

ADM3490E ................................................................................. 14

Low Power Shutdown Mode—ADM3483E/ ADM3486E/

ADM3491E ................................................................................. 14

Driver Output Protection.......................................................... 14

Propagation Delay...................................................................... 14

Line Length vs. Data Rate ......................................................... 14

±15 kV ESD Protection ............................................................. 15

Human Body Model .................................................................. 15

Typical Applications................................................................... 15

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

10/06—Rev. 0 to Rev. A

Added ADM3483E and ADM3488E ...............................Universal

Changes to Figure 1 and Figure 2................................................... 1

Inserted Table 3................................................................................. 5

Changes to Figure 4 and Figure 5................................................... 8

Inserted Figure 28 and Figure 29.................................................. 13

Changes to Figure 31 and Figure 32............................................. 16

Changes to Figure 34...................................................................... 17

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide.......................................................... 18

8/06—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E

GENERAL DESCRIPTION

(continued from Page 1)

The driver outputs of the ADM3483E/ADM3486E/
ADM3488E are slew rate limited, in order to reduce EMI
and data errors caused by reflections from improperly
terminated buses. The receiver has a fail-safe feature that
ensures a logic high output when the inputs are floating.

Table 1. Selection Table

Guaranteed Data

Part No.

ADM3483E 0.25 3.0 to 3.6 Half Yes Yes Yes 8
ADM3486E 2.5 3.0 to 3.6 Half Yes Yes Yes 8
ADM3488E 0.25 3.0 to 3.6 Full Yes No Yes 8
ADM3490E 12 3.0 to 3.6 Full No No Yes 8
ADM3491E 12 3.0 to 3.6 Full No Yes Yes 14

Rate (Mbps)

Supply
Voltage (V)

Half/Full
Duplex

Slew Rate
Limited

Excessive power dissipation caused by bus contention
or by output shorting is prevented with a thermal shut­down circuit.

The parts are fully specified over the industrial temperature range
and are available in 8-lead and 14-lead narrow SOIC packages.

Driver/Receiver
Enable

±15 kV ESD Protection
on Bus Pins

Pin Count

Rev. A | Page 3 of 20

ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E

SPECIFICATIONS

VCC = 3.3 V ± 0.3 V, TA = T

Table 2. ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DRIVER

Differential Outputs

Differential Output Voltage VOD 2.0 V RL = 100 Ω (RS-422) (see Figure 7)

1.5 V RL = 54 Ω (RS-485) (see Figure 7)

1.5 V RL = 60 Ω (RS-485) (see Figure 8)
Δ|VOD| for Complementary Output States1 ∆VOD 0.2 V RL = 54 Ω or 100 Ω (see Figure 7)
Common-Mode Output Voltage VOC 3 V RL = 54 Ω or 100 Ω (see Figure 7)
Δ|VOC| for Complementary Output States1 ∆VOC 0.2 V RL = 54 Ω or 100 Ω (see Figure 7)
Short-Circuit Output Current I
250 mA V
Output Leakage (Y, Z) (ADM3491E Only) IO

Normal Mode 20 μA

−20 μA

Shutdown Mode 1 μA

−1 μA

Logic Inputs

Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Logic Input Current I

RECEIVER

Differential Inputs

Differential Input Threshold Voltage VTH −0.2 0.2 V −7 V < VCM < +12 V
Input Hysteresis ∆VTH 50 mV VCM = 0 V
Input Resistance (A, B) RIN 12
Input Current (A, B) I

−0.8 mA DE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V

RO Logic Output

Output High Voltage VOH V
Output Low Voltage VOL 0.4 V I
Short-Circuit Output Current I
Tristate Output Leakage Current I

POWER SUPPLY

Voltage Range VCC 3.0 3.6 V
Supply Current ICC 1.1 2.2 mA

0.95 1.9 mA

Shutdown Current I

ESD PROTECTION

A, B, Y, Z Pins ±15 kV Human body model
All Pins Except A, B, Y, Z Pins ±4 kV Human body model

1

Δ|VOD| and Δ|VOC| are the changes in VOD and VOC, respectively, when DI input changes state.

MIN

to T

, unless otherwise noted.

MAX

−250 mA V

OSD

±2 μA

IN1

1.0 mA DE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V

IN2

±8 ±60 mA 0 V < VRO < VCC

OSR

±1 μA VCC = 3.6 V, 0 V < V

OZR

0.002 1 μA

SHDN

kΩ

− 0.4 V I

CC

= −7 V

OUT

= 12 V

OUT

DE = 0 V, RE
V

OUT

DE = 0 V, RE
V

OUT

DE = 0 V, RE
V

OUT

DE = 0 V, RE
V

OUT

DE, DI, RE
DE, DI, RE
DE, DI, RE

= 0 V, VCC = 0 V or 3.6 V,

= 12 V

= 0 V, VCC = 0 V or 3.6 V,

= −7 V

= VCC, VCC = 0 V or 3.6 V,

= 12 V

= VCC, VCC = 0 V or 3.6 V,

= −7 V

−7 V < VCM < +12 V

= −1.5 mA, VID = 200 mV (see Figure 9)

OUT

= 2.5 mA, VID = 200 mV (see Figure 9)

OUT

< VCC

OUT

No load, DI = 0 V or V

= 0 V or VCC

RE
No load, DI = 0 V or V

RE

= 0 V

DE = 0 V, RE

= VCC, DI = 0 V or VCC

, DE = VCC,

CC

, DE = 0 V,

CC

Rev. A | Page 4 of 20

ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E

DRIVER TIMING SPECIFICATIONS

VCC = 3.3 V, TA = 25°C.

Table 3. ADM3483E/ADM3488E

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

MAXIMUM DATA RATE 250 kbps
DIFFERENTIAL OUTPUT DELAY tDD 600 900 1400 ns RL = 60 Ω (see Figure 10)
DIFFERENTIAL OUTPUT TRANSITION TIME tTD 400 740 1200 ns RL = 60 Ω (see Figure 10)
PROPAGATION DELAY

From Low to High Level t
From High to Low Level t

|t

− t

PLH

| PROPAGATION DELAY SKEW1 t

PHL

ENABLE/DISABLE TIMING (ADM3483E ONLY)

Enable Time to Low Level t
Enable Time to High Level t
Disable Time from Low Level t
Disable Time from High Level t
Enable Time from Shutdown to Low Level t
Enable Time from Shutdown to High Level t

1

Measured on |t

PLH

(Y) − t

(Y)| and |t

PHL

PLH

(Z) − t

(Z)|.

PHL

700 930 1500 ns RL = 27 Ω (see Figure 11)

PLH

700 930 1500 ns RL = 27 Ω (see Figure 11)

PHL

±50 ns RL = 27 Ω (see Figure 11)

PDS

900 1300 ns RL = 110 Ω (see Figure 13)

PZL

600 800 ns RL = 110 Ω (see Figure 12)

PZH

50 80 ns RL = 110 Ω (see Figure 13)

PLZ

50 80 ns RL = 110 Ω (see Figure 12)

PHZ

1.9 2.7 μs RL = 110 Ω (see Figure 13)

PSL

2.2 3.0 μs RL = 110 Ω (see Figure 12)

PSH

VCC = 3.3 V, TA = 25°C.

Table 4. ADM3486E

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

MAXIMUM DATA RATE 2.5 Mbps
DIFFERENTIAL OUTPUT DELAY tDD 20 42 70 ns RL = 60 Ω (see Figure 10)
DIFFERENTIAL OUTPUT TRANSITION TIME tTD 15 28 60 ns RL = 60 Ω (see Figure 10)
PROPAGATION DELAY

From Low to High Level t
From High to Low Level t

|t

− t

PLH

| PROPAGATION DELAY SKEW

PHL

1

20 42 75 ns RL = 27 Ω (see Figure 11)

PLH

20 42 75 ns RL = 27 Ω (see Figure 11)

PHL

t

−6 ±12 ns RL = 27 Ω (see Figure 11)

PDS

ENABLE/DISABLE TIMING

Enable Time to Low Level t
Enable Time to High Level t
Disable Time from Low Level t
Disable Time from High Level t
Enable Time from Shutdown to Low Level t
Enable Time from Shutdown to High Level t

1

Measured on |t

PLH

(Y) − t

(Y)| and |t

PHL

PLH

(Z) − t

(Z)|.

PHL

52 100 ns RL = 110 Ω (see Figure 13)

PZL

52 100 ns RL = 110 Ω (see Figure 12)

PZH

40 80 ns RL = 110 Ω (see Figure 13)

PLZ

40 80 ns RL = 110 Ω (see Figure 12)

PHZ

700 1000 ns RL = 110 Ω (see Figure 13)

PSL

700 1000 ns RL = 110 Ω (see Figure 12)

PSH

Rev. A | Page 5 of 20

ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E

VCC = 3.3 V, TA = 25°C.

Table 5. ADM3490E/ADM3491E

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

MAXIMUM DATA RATE 12 15 Mbps
DIFFERENTIAL OUTPUT DELAY tDD 1 22 35 ns RL = 60 Ω (see Figure 10)
DIFFERENTIAL OUTPUT TRANSITION TIME tTD 3 11 25 ns RL = 60 Ω (see Figure 10)
PROPAGATION DELAY

From Low to High Level t
From High to Low Level t

|t

− t

PLH

| PROPAGATION DELAY SKEW1 t

PHL

ENABLE/DISABLE TIMING (ADM3491E ONLY)

Enable Time to Low Level t
Enable Time to High Level t
Disable Time from Low Level t
Disable Time from High Level t
Enable Time from Shutdown to Low Level t
Enable Time from Shutdown to High Level t

1

Measured on |t

PLH

(Y) − t

(Y)| and |t

PHL

PLH

(Z) − t

(Z)|.

PHL

RECEIVER TIMING SPECIFICATIONS

VCC = 3.3 V, TA = 25°C.

7 23 35 ns RL = 27 Ω (see Figure 11)

PLH

7 23 35 ns RL = 27 Ω (see Figure 11)

PHL

−1.4 ±8 ns RL = 27 Ω (see Figure 11)

PDS

42 90 ns RL = 110 Ω (see Figure 13)

PZL

42 90 ns RL = 110 Ω (see Figure 12)

PZH

35 80 ns RL = 110 Ω (see Figure 13)

PLZ

35 80 ns RL = 110 Ω (see Figure 12)

PHZ

650 900 ns RL = 110 Ω (see Figure 13)

PSL

650 900 ns RL = 110 Ω (see Figure 12)

PSH

Table 6. ADM3483E/ADM3486E/ADM3488E/ADM3490E/ADM3491E

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

PROPAGATION DELAY

From Low to High Level t

RPLH

ADM3486E/ADM3490E/ADM3491E 25 62 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
ADM3483E/ADM3488E 25 75 120 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)

From High to Low Level t

RPHL

ADM3486E/ADM3490E/ADM3491E 25 62 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
ADM3483E/ADM3488E 25 75 120 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)

|t

− t

RPLH

| PROPAGATION DELAY SKEW t

RPHL

RPDS

ADM3486E/ADM3490E/ADM3491E +6 ±10 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)
ADM3483E/ADM3488E +12 ±20 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 14)

ENABLE/DISABLE TIMING (ADM3483E/ADM3486E/
ADM3491E ONLY)

Enable Time to Low Level t
Enable Time to High Level t
Disable Time from Low Level t
Disable Time from High Level t
Enable Time from Shutdown to Low Level t
Enable Time from Shutdown to High Level t
Time to Shutdown1 t

1

The transceivers are put into shutdown mode by bringing the RE high and the DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to

enter shutdown. If the parts are in this state for 300 ns or more, the parts are guaranteed to enter shutdown.

25 50 ns CL = 15 pF (see Figure 15)

RPZL

25 50 ns CL = 15 pF (see Figure 15)

RPZH

25 45 ns CL = 15 pF (see Figure 15)

RPLZ

25 45 ns CL = 15 pF (see Figure 15)

RPHZ

720 1400 ns CL = 15 pF (see Figure 15)

RPSL

720 1400 ns CL = 15 pF (see Figure 15)

RPSH

80 190 300 ns

SHDN

Rev. A | Page 6 of 20