ANALOG DEVICES ADM 3491 ARZ Datasheet
3.3 V Slew Rate Limited, Half- and
V
V
Data Sheet
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Full-Duplex, RS-485/RS-422 Transceivers
FEATURES
Operate with 3.3 V supply
Interoperable with 5 V logic
EIA RS-422 and RS-485 compliant over full
common-mode range
Data rate options
ADM3483/ADM3488: 250 kbps
ADM3485/ADM3490/ADM3491: 10 Mbps
Half- and full-duplex options
Reduced slew rates for low EMI (ADM3483 and ADM3488)
2 nA supply current in shutdown mode
(ADM3483/ADM3485/ADM3491)
Up to 32 transceivers on the bus
−7 V to +12 V bus common-mode range
Specified over the –40°C to +85°C temperature range
8 ns skew (ADM3485/ADM3490/ADM3491)
8-lead SOIC and 14-lead SOIC (ADM3491 only) packages
APPLICATIONS
Low power RS-485/RS-422 applications
Te le co m
Industrial process control
HVAC
GENERAL DESCRIPTION
The ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 are
low power, differential line transceivers designed to operate using a
single 3.3 V power supply. Low power consumption, coupled with a
shutdown mode, makes the ADM3483/ADM3485/ADM3488/
ADM3490/ADM3491 ideal for power-sensitive applications.
The ADM3488/ADM3490/ADM3491 feature full-duplex communication, while the ADM3483/ADM3485 are designed for
half-duplex communication.
The ADM3483/ADM3488 feature slew rate limited drivers that
minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission at data rates
up to 250 kbps.
The ADM3485/ADM3490/ADM3491 transmit at up to 10 Mbps.
The receiver input impedance is 12 kΩ, allowing up to 32 transceivers to be connected on the bus. A thermal shutdown circuit
prevents excessive power dissipation caused by bus contention or
by output shorting. If a significant temperature increase is detected
FUNCTIONAL BLOCK DIAGRAMS
CC
ADM3483/
ADM3485
RO
RE
DE
DI
RO
DI
RO
RE
DE
DI
in the internal driver circuitry during fault conditions, then the
thermal shutdown circuit forces the driver output into a high
impedance state. If the inputs are unconnected (floating), the
receiver contains a fail-safe feature that results in a logic high
output state. The parts are fully specified over the commercial
and industrial temperature ranges. The ADM3483/ADM3485/
ADM3488/ADM3490 are available in 8-lead SOIC_N; the
ADM3491 is available in a 14-lead SOIC_N.
R
D
GND
Figure 1.
CC
R
ADM3488/
ADM3490
D
GND
Figure 2.
ADM3491
R
D
Figure 3.
A
B
05524-027
A
B
Z
Y
05524-026
A
B
Z
Y
05524-025
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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Fax: 781.461.3113 ©2005-2011 Analog Devices, Inc. All rights reserved.
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 4
Timing Specifications—ADM3485/ADM3490/ADM3491.... 5
Timing Specifications—ADM3483/ADM3488........................ 5
Timing Specifications—
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491...... 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Typical Performance Characteristics ............................................. 9
Test Circuits..................................................................................... 11
Switching Characteristics .............................................................. 13
Circuit Description......................................................................... 14
Devices with Receiver/Driver Enables
(ADM3483/ADM3485/ADM3491)......................................... 14
Devices Without Receiver/Driver Enables—
ADM3488/ADM3490................................................................ 14
Reduced EMI and Reflections (ADM3483/ADM3488) ....... 14
Low Power Shutdown Mode
(ADM3483/ADM3485/ADM3491)......................................... 14
Driver Output Protection.......................................................... 14
Propagation Delay...................................................................... 14
Typical Applications................................................................... 14
Line Length vs. Data Rate ......................................................... 15
Outline Dimensions....................................................................... 17
Ordering Guide .......................................................................... 18
REVISION HISTORY
11/11—Rev. D to Rev. E
Changes to Digital I/O Voltage (DE,
Table 6 ................................................................................................ 7
Moved Typical Performance Characteristics Section .................. 9
Moved Test Circuits Section.......................................................... 11
Moved Switching Characteristics Section ................................... 13
Changes to Note 1, Table 8 ............................................................ 14
Changes to Outline Dimensions................................................... 17
12/10—Rev. C to Rev. D
Changes to Figure 33...................................................................... 15
8/10—Rev. B to Rev. C
Changes to Table 2, Driver Input Logic......................................... 4
, DI) Parameter,
RE
10/06—Rev. A to Rev. B
Updated Format.................................................................. Universal
Added ADM3491 ...............................................................Universal
Changes to Specifications Section...................................................4
Changes to Typical Applications Section .................................... 14
7/06—Rev. 0 to Rev. A
Changes to Applications...................................................................1
Changes to General Description .....................................................1
Changes to Figure 19...................................................................... 10
Changes to Typical Applications Section .................................... 13
Changes to Figure 31 and Figure 32............................................. 14
Updated Outline Dimensions....................................................... 15
10/05—Revision 0: Initial Version
Rev. E | Page 2 of 20
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
Table 1. ADM34xx Part Comparison
Guaranteed
Part No.
ADM3483 0.25 3.0 to 3.6 Half Yes Yes 2 8
ADM3485 10 3.0 to 3.6 Half No Yes 2 8
ADM3488 0.25 3.0 to 3.6 Full Yes No N/A 8
ADM3490 10 3.0 to 3.6 Full No No N/A 8
ADM3491 10 3.0 to 3.6 Full No Yes 2 14
Data Rate (Mbps)
Supply
Voltage (V)
Half-/FullDuplex
Slew Rate
Limited
Driver/Receiver
Enable
Shutdown
Current (nA)
Pin
Count
Rev. E | Page 3 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
SPECIFICATIONS
VCC = 3.3 V ± 0.3 V, TA = T
Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Voltage (VOD) 2.0 V RL = 100 Ω (RS-422), VCC = 3.3 V ± 5% (see Figure 17)
1.5 V RL = 54 Ω (RS-485) (see Figure 17)
1.5 V RL = 60 Ω (RS-485), VCC = 3.3 V (see Figure 18)
∆ |VOD| for Complementary Output States1 0.2 V RL = 54 Ω or 100 Ω (see Figure 17)
Common-Mode Output Voltage (VOC) 3 V RL = 54 Ω or 100 Ω (see Figure 17)
∆ |VOC| for Common-Mode Output Voltage1 0.2 V RL = 54 Ω or 100 Ω (see Figure 17)
DRIVER INPUT LOGIC
CMOS Input Logic Threshold Low (VIL) 0.8 V
CMOS Input Logic Threshold High (VIH) 2.0 V
CMOS Logic Input Current (I
Output Leakage—Y, Z (IO)
Output Leakage (Y, Z) in Shutdown Mode (IO)
RECEIVER
Differential Input Threshold Voltage (VTH) −0.2 +0.2 V −7 V < VCM < +12 V
Input Hysteresis (∆ VTH) 50 mV VCM = 0 V
CMOS Output Voltage High (VOH) VCC – 0.4 V I
CMOS Output Voltage Low (VOL) 0.4 V I
Three-State Output Leakage Current (I
Input Resistance (RIN) 12 kΩ −7 V < VCM < +12 V
POWER SUPPLY CURRENT
Supply Current (ICC)
Supply Current in Shutdown Mode (I
Receiver Short-Circuit Output Current (I
1
∆VOD and ∆VOC are the changes in VOD and VOC, respectively, when DI input changes state.
to T
MIN
)
IN2
, unless otherwise noted.
MAX
DE, DI, RE
DE, DI, RE
) ±2 µA
IN1
DE, DI, RE
1.0 mA VIN = 12 V, DE = 0 V, VCC = 0 V or 3.6 V Input Current—A, B (I
−0.8 mA V
0.1 µA
= −7 V, DE = 0 V, VCC = 0 V or 3.6 V
IN
= 12 V, DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
V
IN
ADM3491 only
−0.1 µA
= −7 V, DE = 0 V, RE = 0 V, VCC = 0 V or 3.6 V,
V
IN
ADM3491 only
0.01 µA
= 12 V, DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
V
IN
ADM3491 only
−0.01 µA
= −7 V, DE = 0 V, RE = VCC, VCC = 0 V or 3.6 V,
V
IN
ADM3491 only
= −1.5 mA, VID = 200 mV (see Figure 19)
OUT
= 2.5 mA, VID = 200 mV (see Figure 19)
OUT
) ±1 µA VCC = 3.6 V, 0 V ≤ V
OZR
1.1 2.2 mA
0.95 1.9 mA
) 0.002 1 µA
SHDN
OSD
)
−250 mA V
250 mA V
) ±8 ±60 mA 0 V < VRO < VCC
OSR
DE = V
CC
DE = 0 V, RE = 0 V, no load, DI = 0 V or VCC
DE = 0 V, RE
= −7 V Driver Short-Circuit Output Current (I
OUT
= 12 V
OUT
, RE = 0 V or VCC, no load, DI = 0 V or VCC
= VCC, DI = VCC or 0 V
OUT
≤ VCC
Rev. E | Page 4 of 20
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
TIMING SPECIFICATIONS—ADM3485/ADM3490/ADM3491
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Delay (tDD) 1 22 35 ns
Differential Output Transition Time (tTD) 3 8 25 ns
Propagation Delay, Low-to-High Level (t
Propagation Delay, High-to-Low Level (t
|t
– t
| Propagation Delay Skew1 (t
PLH
PHL
DRIVER OUTPUT ENABLE/DISABLE TIMES (ADM3485/
) 7 22 35 ns
PLH
) 7 22 35 ns
PHL
) 8 ns
PDS
ADM3491 ONLY)
Output Enable Time to Low Level (t
Output Enable Time to High Level (t
Output Disable Time from High Level (t
Output Disable Time from Low Level (t
Output Enable Time from Shutdown to Low Level (t
Output Enable Time from Shutdown to High Level (t
1
Measured on |t
PLH
(Y) − t
(Y)| and |t
PHL
PLH
) 45 90 ns
PZL
) 45 90 ns
PZH
) 40 80 ns
PHZ
) 40 80 ns
PLZ
) 650 900 ns
PSL
) 650 900 ns
PSH
(Z) − t
(Z)|.
PHL
RL = 60 Ω (see Figure 20 and Figure 26)
RL = 60 Ω (see Figure 20 and Figure 26)
RL = 27 Ω (see Figure 21 and Figure 27)
RL = 27 Ω (see Figure 21 and Figure 27)
RL = 27 Ω (see Figure 21 and Figure 27)
RL = 110 Ω (see Figure 23 and Figure 29)
RL = 110 Ω (see Figure 22 and Figure 28)
RL = 110 Ω (see Figure 22 and Figure 28)
RL = 110 Ω (see Figure 23 and Figure 29)
RL = 110 Ω (see Figure 23 and Figure 29)
RL = 110 Ω (see Figure 22 and Figure 28)
TIMING SPECIFICATIONS—ADM3483/ADM3488
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Output Delay (tDD) 600 900 1400 ns
Differential Output Transition Time (tTD) 400 700 1200 ns
Propagation Delay, Low-to-High Level (t
Propagation Delay, High-to-Low Level (t
|t
– t
| Propagation Delay Skew1 (t
PLH
PHL
) 700 1000 1500 ns
PLH
) 700 1000 1500 ns
PHL
) 100 ns
PDS
DRIVER OUTPUT ENABLE/DISABLE TIMES (ADM3483 ONLY)
Output Enable Time to Low Level (t
Output Enable Time to High Level (t
Output Disable Time from High Level (t
Output Disable Time from Low Level (t
Output Enable Time from Shutdown to Low Level (t
Output Enable Time from Shutdown to High Level (t
1
Measured on |t
PLH
(Y) − t
(Y)| and |t
PHL
PLH
) 900 1300 ns
PZL
) 600 800 ns
PZH
) 50 80 ns
PHZ
) 50 80 ns
PLZ
) 1.9 2.7 µs
PSL
) 2.2 3.0 s
PSH
(Z) − t
(Z)|.
PHL
RL = 60 Ω (see Figure 20 and Figure 26)
RL = 60 Ω (see Figure 20 and Figure 26)
RL = 27 Ω (see Figure 21 and Figure 27)
RL = 27 Ω (see Figure 21 and Figure 27)
RL = 27 Ω (see Figure 21 and Figure 27)
= 110 Ω (see Figure 23 and Figure 29)
R
L
RL = 110 Ω (see Figure 22 and Figure 28)
RL = 110 Ω (see Figure 22 and Figure 28)
RL = 110 Ω (see Figure 23 and Figure 29)
RL = 110 Ω (see Figure 23 and Figure 29)
RL = 110 Ω (see Figure 22 and Figure 28)
Rev. E | Page 5 of 20
ADM3483/ADM3485/ADM3488/ADM3490/ADM3491 Data Sheet
TIMING SPECIFICATIONS—ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
VCC = 3.3 V, TA = 25°C, unless otherwise noted.
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
RECEIVER
Time to Shutdown (t
ADM3483/ADM3485/ADM34911 80 190 300 ns
Propagation Delay, Low-to-High Level (t
ADM3485/ADM3490/ADM3491 25 65 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 24 and Figure 30)
ADM3483/ADM3488 25 75 120 ns
Propagation Delay, High-to-Low Level (t
ADM3485/ADM3490/ADM3491 25 65 90 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 24 and Figure 30)
ADM3483/ADM3488 25 75 120 ns
|t
– t
| Propagation Delay Skew (t
PLH
PHL
ADM3485/ADM3490/ADM3491 10 ns VID = 0 V to 3.0 V, CL = 15 pF (see Figure 24 and Figure 30)
ADM3483/ADM3488 20 ns
RECEIVER OUTPUT ENABLE/DISABLE TIMES
(ADM3483/ADM3485/ADM3491 ONLY)
Output Enable Time to Low Level (t
Output Enable Time to High Level (t
Output Disable Time from High Level (t
Output Disable Time from Low Level (t
Output Enable Time from Shutdown to
Low Level (t
PRSL
Output Enable Time from Shutdown to
High Level (t
1
The transceivers are put into shutdown by bringing the RE high and DE low. If the inputs are in this state for less than 80 ns, the parts are guaranteed not to enter
shutdown. If the parts are in this state for 300 ns or more, the parts are guaranteed to enter shutdown.
PRSH
)
SHDN
)
RPLH
)
RPHL
)
RPDS
) 25 50 ns CL = 15 pF (see Figure 25 and Figure 31)
PRZL
) 25 50 ns CL = 15 pF (see Figure 25 and Figure 31)
PRZH
) 25 45 ns CL = 15 pF (see Figure 25 and Figure 31)
PRHZ
) 25 45 ns CL = 15 pF (see Figure 25 and Figure 31)
PRLZ
720 1400 ns CL = 15 pF (see Figure 25 and Figure 31)
)
720 1400 ns C
)
= 15 pF (see Figure 25 and Figure 31)
L
Rev. E | Page 6 of 20
Data Sheet ADM3483/ADM3485/ADM3488/ADM3490/ADM3491
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VCC to GND 7 V
Digital I/O Voltage (DE, RE, DI)
Digital I/O Voltage (RO) VCC − 0.5 V to VCC + 0.5 V
Driver Output/Receiver Input Voltage −7.5 V to +12.5 V
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +125°C
θJA Thermal Impedance
8-Lead SOIC 121°C/W
14-Lead SOIC 86°C/W
Lead Temperature
Soldering (10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
−0.3 V to +6 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. E | Page 7 of 20
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