ESD Protected, EMC Compliant, 3.3 V,
a
FEATURES
Operates with +3.3 V Supply
ESD Protection: 8 kV Meets IEC1000-4-2
EFT Protection: 2 kV Meets IEC1000-4-4
EIA RS-422 and RS-485 Compliant Over Full CM Range
19 k Input Impedance
Up to 50 Transceivers on Bus
20 Mbps Data Rate
Short Circuit Protection
Specified Over Full Temperature Range
Thermal Shutdown
Interoperable with 5 V Logic
1 mA Supply Current
2 nA Shutdown Current
8 ns Skew
APPLICATIONS
Telecommunications
DTE-DCE Interface
Packet Switching
Local Area Networks
Data Concentration
Data Multiplexers
Integrated Services Digital Network (ISDN)
AppleTalk
Industrial Controls
20 Mbps, EIA RS-485 Transceiver
ADM3485E
FUNCTIONAL BLOCK DIAGRAM
ADM3485E
RO
RE
DE
DI
R
B
A
D
GENERAL DESCRIPTION
The ADM3485E is a low power differential line transceiver
designed to operate using a single +3.3 V power supply. Low
power consumption makes it ideal for power sensitive applications. It is suitable for communication on multipoint bus transmission lines. Internal protection against electrostatic discharge
(ESD) and electrical fast transient (EFT) allows operation in
electrically harsh environments.
It is intended for balanced data transmission and complies with
both EIA Standards RS-485 and RS-422. It contains a differential line driver and a differential line receiver, and is suitable for
half duplex data transfer.
The input impedance is 19 kΩ allowing up to 50 transceivers to
be connected on the bus.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
Excessive power dissipation caused by bus contention or by
output shorting is prevented by a thermal shutdown circuit.
This feature forces the driver output into a high impedance
state if, during fault conditions, a significant temperature
increase is detected in the internal driver circuitry.
The receiver contains a fail-safe feature that results in a
logic high output state if the inputs are unconnected
(floating).
The ADM3485E is fabricated on BiCMOS, an advanced
mixed technology process combining low power CMOS
with fast switching bipolar technology.
The ADM3485E is fully specified over the industrial temperature range and is available in 8-lead DIP and SOIC
packages.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2000
ADM3485E–SPECIFICATIONS
(VCC = +3.3 V 0.3 V. All specifications T
MIN
to T
unless otherwise noted.)
MAX
Parameter Min Typ Max Units Test Conditions/Comments
DRIVER
Differential Output Voltage, V
∆|V
| for Complementary Output States 0.2 V R = 54 Ω or 100 Ω, Figure 1
OD
Common-Mode Output Voltage V
∆|V
| for Complementary Output States 0.2 V R = 54 Ω or 100 Ω, Figure 1
OC
OD
OC
CMOS Input Logic Threshold Low, V
CMOS Input Logic Threshold High, V
2.0 V RL = 100 Ω, Figure 1, VCC > 3.1 V
1.5 V R
1.5 V R
= 54 Ω, Figure 1
L
= 60 Ω, Figure 2, –7 V < V
L
3 V R = 54 Ω or 100 Ω, Figure 1
INL
2.0 V
INH
0.8 V
< +12 V
TST
Logic Input Current (DE, DI, RE) ± 1.0 µA
Output Short Circuit Current ± 250 mA VO = –7 V or +12 V
RECEIVER
Differential Input Threshold Voltage, V
Input Voltage Hysteresis, ∆V
TH
Input Resistance 12 19 kΩ –7 V < V
Input Current (A, B) +1 mA V
–0.2 +0.2 V –7 V < VCM < +12 V
TH
50 mV VCM = 0 V
= +12 V
IN
–0.8 mA V
= –7 V
IN
< +12 V
CM
Logic Enable Input Current (RE) ± 1 µA
Output Voltage Low, V
Output Voltage High, V
OL
OH
VCC – 0.4 V V I
Short Circuit Output Current ± 60 mA V
Three-State Output Leakage Current ± 1.0 µAV
0.4 V I
= +2.5 mA
OUT
= –1.5 mA
OUT
= GND or V
OUT
= 3.6 V, 0 V < V
CC
CC
OUT
< V
CC
POWER SUPPLY CURRENT
I
CC
1 1.2 mA DE = V
Outputs Unloaded,
, RE = 0 V
CC
1 1.2 mA DE = 0 V, RE = 0 V
Supply Current in Shutdown 0.002 1 µA DE = 0 V, RE = V
CC
ESD/EFT IMMUNITY
ESD Protection ± 8 kV IEC1000-4-2 A, B Pins Contact Discharge
EFT Protection ± 2 kV IEC1000-4-4, A, B Pins
Specifications subject to change without notice.
–2–
REV. A
ADM3485E
TIMING SPECIFICATIONS
(VCC = +3.3 V, TA = +25C)
Parameter Min Typ Max Units Test Conditions/ Comments
DRIVER
Differential Output Delay T
DD
Differential Output Transition Time 1 8 15 ns R
Propagation Delay Input to Output T
Driver O/P to O/P T
SKEW
PLH
, T
PHL
135nsR
72235nsR
8nsR
= 60 Ω, CL1 = CL2 = 15 pF, Figure 3
L
= 60 Ω, CL1 = CL2 = 15 pF, Figure 3
L
= 27 Ω, CL1 = CL2 = 15 pF, Figure 7
L
= 54 Ω, CL1 = CL2 = 15 pF, Figure 3
L
ENABLE/DISABLE
Driver Enable to Output Valid 45 90 ns R
Driver Disable Timing 40 80 ns R
= 110 Ω, CL = 50 pF, Figure 2
L
= 110 Ω, CL = 50 pF, Figure 2
L
Driver Enable from Shutdown 650 110 ns RL = 110 Ω, CL = 15 pF, Figure 2
RECEIVER
Time to Shutdown 80 190 300 ns
Propagation Delay Input to Output T
Skew T
Receiver Enable T
Receiver Disable T
PLH–TPHL
EN
DEN
PLH
, T
PHL
25 65 90 ns CL = 15 pF, Figure 8
10 ns CL = 15 pF, Figure 8
25 50 ns CL = 15 pF, Figure 6
25 45 ns CL = 15 pF, Figure 6
Receiver Enable from Shutdown 500 ns CL = 15 pF, Figure 6
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(VCC = +3.3 V 0.3 V, TA = T
MIN
to T
MAX
)
Parameter Min Typ Max Units Test Conditions/ Comments
DRIVER
Differential Output Delay T
DD
Differential Output Transition Time 2 8 15 ns R
Propagation Delay Input to Output T
Driver O/P to O/P T
SKEW
PLH
, T
PHL
170nsR
72270nsR
= 60 Ω, CL1 = CL2 = 15 pF, Figure 3
L
= 60 Ω, CL1 = CL2 = 15 pF, Figure 3
L
= 27 Ω, CL1 = CL2 = 15 pF, Figure 7
L
10 ns RL = 54 Ω, CL1 = CL2 = 15 pF, Figure 3
ENABLE/DISABLE
Driver Enable to Output Valid 45 110 ns R
Driver Disable Timing 40 110 ns R
= 110 Ω, CL = 50 pF, Figure 2
L
= 110 Ω, CL = 50 pF, Figure 2
L
Driver Enable from Shutdown 650 110 ns RL = 110 Ω, CL = 15 pF, Figure 2
RECEIVER
Time to Shutdown 50 190 500 ns
Propagation Delay Input to Output T
Skew T
Receiver Enable T
Receiver Disable T
PLH–TPHL
EN
DEN
PLH
, T
PHL
25 65 115 ns CL = 15 pF, Figure 8
20 ns CL = 15 pF, Figure 8
25 50 ns CL = 15 pF, Figure 6
25 50 ns CL = 15 pF, Figure 6
Receiver Enable from Shutdown 600 ns CL = 15 pF, Figure 6
Specifications subject to change without notice.
–3–REV. A
ADM3485E
ABSOLUTE MAXIMUM RATINGS*
(TA = +25°C unless otherwise noted)
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Inputs
Driver Input (DI) . . . . . . . . . . . . . . . . –0.3 V to V
Control Inputs (DE, RE) . . . . . . . . . . –0.3 V to V
+ 0.3 V
CC
+ 0.3 V
CC
Receiver Inputs (A, B) . . . . . . . . . . . . . . . –7.5 V to +12.5 V
Outputs
Driver Outputs . . . . . . . . . . . . . . . . . . . . . –7.5 V to +12.5 V
Receiver Output . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Power Dissipation 8-Lead DIP . . . . . . . . . . . . . . . . . 800 mW
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 140°C/W
θ
JA
Power Dissipation 8-Lead SOIC . . . . . . . . . . . . . . . . 650 mW
, Thermal Impedance . . . . . . . . . . . . . . . . . . . . 115°C/W
θ
JA
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C
ESD Rating: Air (Human Body Model, All Pins) . . . . . >4 kV
ESD Rating: IEC1000-4-2 Contact (A, B Pins) . . . . . . >8 kV
EFT Rating: IEC1000-4-4 (A, B Pins) . . . . . . . . . . . . . >2 kV
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods of time may affect device reliability.
ORDERING GUIDE
Model Temperature Range Package Description Package Options
ADM3485EAN –40°C to +85°C Plastic DIP N-8
ADM3485EAR –40°C to +85°C Small Outline (SOIC) SO-8
PIN CONFIGURATION
DIP/SOIC
RO
RE
DE
DI
1
ADM3485E
2
3
TOP VIEW
(Not to Scale)
4
8
V
CC
7
B
6
A
5
GND
PIN FUNCTION DESCRIPTIONS
Mnemonic DIP/
Pin SOIC Function
RO 1 Receiver Output. High when A > B by 200 mV or low when A < B by 200 mV.
RE 2 Receiver Output Enable. With RE low, the receiver output RO is enabled. With RE high, the output goes
high impedance. If RE is high and DE low, the ADM3485E enters a shutdown state.
DE 3 Driver Output Enable. A high level enables the driver differential outputs, A and B. A low level places it in a
high impedance state.
DI 4 Driver Input. When the driver is enabled, a logic low on DI forces A low and B high, while a logic high on DI
forces A high and B low.
GND 5 Ground Connection, 0 V.
A 6 Noninverting Receiver Input A/Driver Output A.
B 7 Inverting Receiver Input B/Driver Output B.
V
CC
8 Power Supply, 3.3 V ± 0.3 V.
–4–
REV. A
Test Circuits
ADM3485E
V
OD
V
CC
R/2
R/2
V
OC
Figure 1. Driver Voltage Measurement Test Circuit
V
CC
R
L
C
L
V
OUT
S20V OR 3V
DE IN
DE
S1
Figure 2. Driver Enable/Disable Test Circuit
C
DI
D
RL
DIFF
L1
V
OUT
C
L2
Figure 3. Driver Differential Output Delay Test Circuit
375
V
OD3
R
375
V
L
TST
Figure 5. Driver Voltage Measurement Test Circuit 2
V
R
L
OUT
CC
L
S2
+1.5V
–1.5V
S1
RE IN
RE
C
V
Figure 6. Receiver Enable/Disable Test Circuit
V
OM
R
L
V
DE
IN
V
CC
S1
C
L
OUT
Figure 7. Driver Propagation Delay Test Circuit
C
DI
D
RL
DIFF
L1
C
L2
A
B
RO
R
RE
Figure 4. Driver/Receiver Propagation Delay Test Circuit
3V
0V
V
ID
+1.5V
RE
V
OUT
C
L
Figure 8. Receiver Propagation Delay Test Circuit
–5–REV. A
ADM3485E
Switching Characteristics
3V
1.5V 1.5V
0V
B
A
0V
–VO
VO
VO
10% POINT
1/2 VO
90% POINT
t
PLH
t
SKEW
t
R
t
PLH
t
SKEW
90% POINT
10% POINT
t
F
DE
3V
1.5V
t
ZL
D
D
0V
1.5V
t
ZH
1.5V
O/P
LOW
O/P
HIGH
1.5V
t
LZ
t
0V
+ 0.25V
V
OL
HZ
V
OH
– 0.25V
V
OL
V
OH
Figure 9. Driver Propagation Delay, Rise/Fall Timing
A–B
RO
0V
t
PLH
1.5V
0V
t
PLH
V
OH
1.5V
V
OL
Figure 10. Receiver Propagation Delay
Figure 11. Driver Enable/Disable Timing
RE
1.5V
t
ZL
R
R
0V
1.5V
t
ZH
1.5V
O/P
LOW
O/P
HIGH
1.5V
t
LZ
t
HZ
Figure 12. Receiver Enable/Disable Timing
V
V
OL
OH
+ 0.25V
– 0.25V
3V
0V
V
OL
V
OH
–6–
REV. A
Typical Performance Characteristics–A
TEMPERATURE – C
3.30
–50 70
–30
RECEIVER O/P HIGH VOLTAGE – V
–10 10 30 50
3.25
3.15
3.10
3.05
2.90
3.20
3.00
2.95
90 110
DM3485E
14
12
10
8
6
4
OUTPUT CURRENT – mA
2
0
0
1.5
1.0
OUTPUT LOW VOLTAGE – V
2.0
2.5
3.0
3.50.5
Figure 13. Output Current vs. Receiver Output Low
Voltage
0.8
0.7
0.6
0.5
12
10
8
6
4
OUTPUT CURRENT – mA
2
0
0
0.5
1.5
1.0
OUTPUT HIGH VOLTAGE – V
2.0
2.5
3.0
3.5
Figure 16. Output Current vs. Receiver Output High
Voltage
0.4
0.3
0.2
RECEIVER OUTPUT LOW VOLTAGE – V
0.1
–30
–50 90
–10 10 30 50 70
TEMPERATURE – C
110
Figure 14. Receiver Output Low Voltage vs. Temperature
120
100
80
60
40
DRIVER OUTPUT CURRENT – mA
20
0
0.5
0
DIFFERENTIAL OUTPUT VOLTAGE – V
1.0
1.5
2.0
2.5
3.0
Figure 15. Driver Output Current vs. Differential
Output Voltage
Figure 17. Receiver Output High Voltage vs. Temperature
2.6
2.5
2.4
2.3
2.2
– V
2.1
OD
V
2.0
1.9
1.8
1.7
1.6
–30
–50 70
–10 10 30 50
TEMPERATURE – C
90 110
Figure 18. Driver Differential Output Voltage vs. Temperature
REV. A
–7–
ADM3485E
1.20
1.15
1.10
1.05
1.00
0.95
– mA
CC
I
0.90
0.85
0.80
0.75
0.70
–50 70
ICC (mA) DE = VCC, RE = X
ICC (mA) RE = LO, DE = LO
–30
–10 10 30 50
TEMPERATURE – C
90 110
Figure 19. Supply Current vs. Temperature
Table I. Comparison of RS-422 and RS-485 Interface Standards
Specification RS-422 RS-485
Transmission Type Differential Differential
Maximum Data Rate 10 MB/s 10 MB/s
Maximum Cable Length 4000 ft. 4000 ft.
Minimum Driver Output Voltage ±2 V ± 1.5 V
Driver Load Impedance 100 Ω 54 Ω
ESD/EFT TRANSIENT PROTECTION SCHEME
The ADM3485E uses protective clamping structures on its
inputs and outputs that clamp the voltage to a safe level and
dissipate the energy present in ESD (Electrostatic) and EFT
(Electrical Fast Transients) discharges.
The protection structure achieves ESD protection up to ±8 kV
according to IEC1000-4-2, and EFT protection up to ± 2 kV on
all I-O lines.
Receiver Input Resistance 4 kΩ min 12 kΩ min
Receiver Input Sensitivity ± 200 mV ± 200 mV
Receiver Input Voltage Range –7 V to +7 V –7 V to +12 V
No. of Drivers/Receivers Per Line 1/10 32/32
ESD TESTING
Two coupling methods are used for ESD testing, contact discharge and air-gap discharge. Contact discharge calls for a direct connection to the unit being tested. Air-gap discharge uses
a higher test voltage but does not make direct contact with the
Table II. Transmitting Truth Table
Transmitting
Inputs Outputs
RE DE DI B A
X11 01
X10 10
0 0 X Hi-Z Hi-Z
1 0 X Hi-Z Hi-Z
unit under test. With air discharge, the discharge gun is moved
toward the unit under test, developing an arc across the air gap,
hence the term air-discharge. This method is influenced by humidity, temperature, barometric pressure, distance and rate of
closure of the discharge gun. The contact-discharge method,
while less realistic, is more repeatable and is gaining acceptance
and preference over the air-gap method.
Although very little energy is contained within an ESD pulse,
the extremely fast rise time, coupled with high voltages, can
cause failures in unprotected semiconductors. Catastrophic
destruction can occur immediately as a result of arcing or heat-
Table III. Receiving Truth Table
ing. Even if catastrophic failure does not occur immediately, the
device may suffer from parametric degradation, which may
Receiving
Inputs Outputs
RE DE A–B RO
0 X > +0.2 V 1
0 X < –0.2 V 0
0 X Inputs O/C 1
1XX Hi-Z
result in degraded performance. The cumulative effects of continuous exposure can eventually lead to complete failure.
I-O lines are particularly vulnerable to ESD damage. Simply
touching or plugging in an I-O cable can result in a static discharge that can damage or completely destroy the interface
product connected to the I-O port.
It is extremely important, therefore, to have high levels of ESD
protection on the I-O lines.
It is possible that the ESD discharge could induce latchup in the
device under test, so it is important that ESD testing on the I-O
pins be carried out while device power is applied. This type of
testing is more representative of a real-world I-O discharge
where the equipment is operating normally when the discharge
occurs.
100
90
80
70
60
50
– nA
CC
I
40
30
20
10
0
–20
–40 80
0 204060
TEMPERATURE – C
ICC (mA)
Figure 20. Shutdown Current vs. Temperature
–8–
REV. A
ADM3485E
100%
90%
PEAK
I
36.8%
10%
t
RL
t
DL
Figure 21. Human Body Model Current Waveform
Table IV. ESD Test Results
ESD Test Method I-O Pins
IEC1000-4-2: Contact ±8 kV
100%
90%
TIME t
Four severity levels are defined in terms of an open-circuit voltage as a function of installation environment. The installation
environments are defined as
1. Well-Protected
2. Protected
3. Typical Industrial
4. Severe Industrial
V
t
300ms 16ms
V
5ns
50ns
t
0.2/0.4ms
Figure 23. IEC1000-4-4 Fast Transient Waveform
Table V shows the peak voltages for each of the environments.
PEAK
I
10%
0.1 TO 1ns
30ns
60ns
TIME
t
Figure 22. IEC1000-4-2 ESD Current Waveform
FAST TRANSIENT BURST IMMUNITY (IEC1000-4-4)
IEC1000-4-4 (previously 801-4) covers electrical fast-transient/
burst (EFT) immunity. Electrical fast transients occur as a
result of arcing contacts in switches and relays. The tests simulate the interference generated when, for example, a power relay
disconnects an inductive load. A spark is generated due to the
well known back EMF effect. In fact, the spark consists of a
burst of sparks as the relay contacts separate. The voltage appearing on the line, therefore, consists of a burst of extremely
fast transient impulses. A similar effect occurs when switching
on fluorescent lights.
The fast transient burst test, defined in IEC1000-4-4, simulates
this arcing and its waveform is illustrated in Figure 23. It consists of a burst of 2.5 kHz to 5 kHz transients repeating at
300 ms intervals. It is specified for both power and data lines.
Table V. Peak Voltages
Level V
(kV) PSU V
PEAK
PEAK
(kV) I-O
1 0.5 0.25
2 1 0.5
32 1
44 2
A simplified circuit diagram of the actual EFT generator is
illustrated in Figure 24.
C
D
HIGH
VOLTAGE
SOURCE
R
C
C
C
R
L
M
Z
S
50
OUTPUT
Figure 24. EFT Generator
These transients are coupled onto the signal lines using an EFT
coupling clamp. The clamp is 1 m long and completely surrounds the cable, providing maximum coupling capacitance
(50 pF to 200 pF typ) between the clamp and the cable. High
energy transients are capacitively coupled onto the signal lines.
Fast rise times (5 ns) as specified by the standard result in very
effective coupling. This test is very severe since high voltages are
coupled onto the signal lines. The repetitive transients can often
cause problems, where single pulses do not. Destructive latchup
may be induced due to the high energy content of the transients.
Note that this stress is applied while the interface products are
powered up and are transmitting data. The EFT test applies
hundreds of pulses with higher energy than ESD. Worst case
transient current on an I-O line can be as high as 40 A.
–9–REV. A
ADM3485E
Test results are classified according to the following
1. Normal performance within specification limits.
2. Temporary degradation or loss of performance that is selfrecoverable.
3. Temporary degradation or loss of function or performance
that requires operator intervention or system reset.
4. Degradation or loss of function that is not recoverable due to
damage.
APPLICATIONS INFORMATION
Differential Data Transmission
Differential data transmission is used to reliably transmit data at
high rates over long distances and through noisy environments.
Differential transmission nullifies the effects of ground shifts
and noise signals that appear as common-mode voltages on the
line.
Two main standards are approved by the Electronics Industries
Association (EIA) which specify the electrical characteristics of
transceivers used in differential data transmission. The RS-422
standard specifies data rates up to 10 MBaud and line lengths
up to 4000 ft. A single driver can drive a transmission line with
up to 10 receivers.
The RS-485 standard was defined to cater to true multipoint
communications. This standard meets or exceeds all the requirements of RS-422, but also allows multiple drivers and
receivers to be connected to a single bus. An extended commonmode range of –7 V to +12 V is defined.
The most significant difference between RS-422 and RS-485 is
the fact that the drivers may be disabled thereby allowing more
than one to be connected to a single line. Only one driver should
be enabled at a time, but the RS-485 standard contains additional specifications to guarantee device safety in the event of
line contention.
Cable and Data Rate
The transmission line of choice for RS-485 communications is a
twisted pair. Twisted pair cable tends to cancel common-mode
noise and also causes cancellation of the magnetic fields generated by the current flowing through each wire, thereby reducing
the effective inductance of the pair.
The ADM3485E is designed for bidirectional data communications on multipoint transmission lines. A typical application
showing a multipoint transmission network is illustrated in
Figure 23. Only one driver can transmit at a particular time, but
multiple receivers may be enabled simultaneously.
As with any transmission line, it is important that reflections are
minimized. This may be achieved by terminating the extreme
ends of the line using resistors equal to the characteristic impedance of the line. Stub lengths of the main line should also be
kept as short as possible. A properly terminated transmission
line appears purely resistive to the driver.
Receiver Open-Circuit Fail-Safe
The receiver input includes a fail-safe feature that guarantees a
logic high on the receiver when the inputs are open circuit or
floating.
Table VI. Comparison of RS-422 and RS-485 Interface
Standards
Specification RS-422 RS-485
Transmission Type Differential Differential
Maximum Cable Length 4000 ft. 4000 ft.
Minimum Driver Output Voltage ± 2 V ± 1.5 V
Driver Load Impedance 100 Ω 54 Ω
Receiver Input Resistance 4 kΩ min 12 kΩ min
Receiver Input Sensitivity ± 200 mV ± 200 mV
Receiver Input Voltage Range –7 V to +7 V –7 V to +12 V
–10–
REV. A
0.210 (5.33)
0.0098 (0.25)
0.0075 (0.19)
0.0500 (1.27)
0.0160 (0.41)
8
0
0.0196 (0.50)
0.0099 (0.25)
45
85
41
0.1968 (5.00)
0.1890 (4.80)
0.2440 (6.20)
0.2284 (5.80)
PIN 1
0.1574 (4.00)
0.1497 (3.80)
0.0500 (1.27)
BSC
0.0688 (1.75)
0.0532 (1.35)
SEATING
PLANE
0.0098 (0.25)
0.0040 (0.10)
0.0192 (0.49)
0.0138 (0.35)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
14
PIN 1
0.100
(2.54)
BSC
5
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
8-Lead SOIC
(SO-8)
ADM3485E
0.195 (4.95)
0.115 (2.93)
C3338–0–5/00 (rev. A) 00075
PRINTED IN U.S.A.
–11–REV. A
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