ANALOG DEVICES ADM3070E, ADM3071E, ADM3072E, ADM3073E, ADM3074E Service Manual

3.3 V, ±15 kV ESD-Protected, Half- and

V

V

V

www.BDTIC.com/ADI

Full-Duplex, RS-485/RS-422 Transceivers

ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E

FEATURES

TIA/EIA RS-485/RS-422 compliant
±15 kV ESD protection on RS-485 input/output pins
Data rates

ADM3070E/ADM3071E/ADM3072E: 250 kbps
ADM3073E/ADM3074E/ADM3075E: 500 kbps

ADM3076E/ADM3077E/ADM3078E: 16 Mbps
Half- and full-duplex options
True fail-safe receiver inputs
Up to 256 nodes on the bus

−40°C to +125°C temperature option
Hot-swap input structure on DE and
Reduced slew rates for low EMI
Low power shutdown current (all except ADM3071E/

ADM3074E/ADM3077E)
Outputs high-Z when disabled or powered off
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
8-lead and 14-lead narrow SOIC packages

RE

pins

FUNCTIONAL BLOCK DIAGRAMS

CC

ADM3070E/
ADM3073E/
ADM3076E

RO

RE

DE

DI

RO

R

D

GND

Figure 1.

CC

ADM3071E/
ADM3074E/

ADM3077E

R

A

B

Z

Y

06285-001

A

B

APPLICATIONS

Power/energy metering
Industrial control
Lighting systems
Telecommunications
Security systems
Instrumentation

GENERAL DESCRIPTION

The ADM307xE are 3.3 V, low power data transceivers with
±15 kV ESD protection suitable for full- and half-duplex
communication on multipoint bus transmission lines. They
are designed for balanced data transmission, and they comply
with TIA/EIA standards: RS-485 and RS-422.

The devices have a ⅛ unit load receiver input impedance, which
allows up to 256 transceivers on a bus. Because only one driver
should be enabled at any time, the output of a disabled or powered­down driver is tristated to avoid overloading the bus.

The receiver inputs have a true fail-safe feature, which eliminates
the need for external bias resistors and ensures a logic high
output level when the inputs are open or shorted. This guar­antees that the receiver outputs are in a known state before
communication begins and when communication ceases.

DI

RO

RE

DE

DI

D

GND

Figure 2.

CC

ADM3072E/
ADM3075E/

ADM3078E

R

D

GND

Figure 3.

Z

Y

6285-002

A

B

06285-003

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006–2008 Analog Devices, Inc. All rights reserved.

ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagrams ............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 4

Timing Specifications—ADM3070E/ADM3071E/

ADM3072E .................................................................................... 5

Timing Specifications—ADM3073E/ADM3074E/

ADM3075E .................................................................................... 6

Timing Specifications—ADM3076E/ADM3077E/

ADM3078E .................................................................................... 7

Absolute Maximum Ratings ............................................................ 8

ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Test Circuits and Switching Characteristics ................................ 10

REVISION HISTORY

8/08—Rev. A to Rev. B

Changes to Table 3 ............................................................................ 5

Changes to Figure 36 ...................................................................... 18

Updated Package Drawings ........................................................... 19

Changes to Ordering Guide .......................................................... 20

10/06—Rev. 0 to Rev. A

Added ADM3077E and ADM3078E ............................... Universal

Changes to Figure 2 and Figure 3 ................................................... 1

Changes to Figure 5 and Figure 6 ................................................... 9

Changes to Figure 34 and Figure 35 ............................................. 17

Updated Outline Dimensions ....................................................... 19

Changes to Ordering Guide .......................................................... 20

8/06—Revision 0: Initial Version

Typical Performance Characteristics ........................................... 12

Circuit Description......................................................................... 15

Function Tables ........................................................................... 15

Receiver Fail-Safe ....................................................................... 15

Hot-Swap Capability .................................................................. 16

Line Length vs. Data Rate ......................................................... 16

±15 kV ESD Protection ............................................................. 16

Human Body Model .................................................................. 16

256 Transceivers on the Bus ...................................................... 16

Reduced EMI and Reflections .................................................. 16

Low Power Shutdown Mode ..................................................... 17

Driver Output Protection .......................................................... 17

Typical Applications ................................................................... 17

Outline Dimensions ....................................................................... 19

Ordering Guide .......................................................................... 20

Rev. B | Page 2 of 20

ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E

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The driver outputs of the 250 kbps and 500 kbps devices are slew
rate limited to reduce EMI and data errors caused by reflections
from improperly terminated buses. Excessive power dissipation
caused by bus contention or by output shorting is prevented
with a thermal shutdown circuit.

Table 1. Selection Table

Half/Full

Part No.

ADM3070E Full 0.25 Yes Yes Yes 256 Yes 14
ADM3071E Full 0.25 Yes No No 256 Yes 8
ADM3072E Half 0.25 Yes Yes Yes 256 Yes 8
ADM3073E Full 0.5 Yes Yes Yes 256 Yes 14
ADM3074E Full 0.5 Yes No No 256 Yes 8
ADM3075E Half 0.5 Yes Yes Yes 256 Yes 8
ADM3076E Full 16 No Yes Yes 256 Yes 14
ADM3077E Full 16 No No No 256 Yes 8
ADM3078E Half 16 No Yes Yes 256 Yes 8

Duplex

Data Rate
(Mbps)

Slew Rate
Limited

Driver/Receiver
Enable

The parts are fully specified over the industrial temperature
ranges and are available in 8-lead and 14-lead narrow SOIC
packages.

Low Power
Shutdown

Nodes on
Bus

±15 kV ESD
on Bus Pins

Pin
Count

Rev. B | Page 3 of 20

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SPECIFICATIONS

VCC = 3.3 V ± 10%, TA = T

Table 2. ADM3070E/ADM3071E/ADM3072E/ADM3073E/ADM3074E/ADM3075E/ADM3076E/ADM3077E/ADM3078E

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DRIVER

Differential Outputs

Differential Output Voltage VOD 2.0 VCC V RL = 100 Ω (RS-422) (see Figure 7)

1.5 VCC V RL = 54 Ω (RS-485) (see Figure 7)
V
Δ|VOD| for Complementary Output States1ΔVOD
Common-Mode Output Voltage VOC V
Δ|VOC| for Complementary Output States
Short-Circuit Output Current I

−250 −40 mA −7 V < V
Short-Circuit Foldback Output Current I

−20 mA −7 V < V
Output Leakage (Y, Z) Full Duplex IO 125 μA

−100 μA

Logic Inputs

Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input Hysteresis V
Logic Input Current IIN ±1 μA

Input Impedance First Transition 1 10 kΩ DE
Thermal Shutdown Threshold TTS 175 °C
Thermal Shutdown Hysteresis T

RECEIVER

Differential Inputs

Differential Input Threshold Voltage VTH −200 −125 −50 mV −7 V < VCM < +12 V

Input Hysteresis

Input Resistance (A, B) RIN 96 kΩ −7 V < VCM < +12 V

Input Current (A, B)

−100 μA DE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
RO Logic Output

Output High Voltage VOH VCC − 0.6 V I
Output Low Voltage VOL 0.4 V I
Short-Circuit Output Current I
Tristate Output Leakage Current I

POWER SUPPLY

Supply Current ICC 0.8 1.5 mA

Shutdown Current

ESD PROTECTION

A, B, Y, Z Pins ±15 kV Human body model
All Pins Except A, B, Y, Z Pins ±4 kV Human body model

1

Δ|VOD| and Δ|VOC| are the changes in VOD and VOC, respectively, when the DI input changes state.

MIN

to T

, unless otherwise noted.

MAX

V No load

CC

0.2 V RL = 54 Ω or 100 Ω (see Figure 7)
/2 3 V RL = 54 Ω or 100 Ω (see Figure 7)

1

ΔV

0.2 V RL = 54 Ω or 100 Ω (see Figure 7)

OC

40 250 mA 0 V < V

OSD

20 mA (VCC − 1 V) < V

OSDF

100 mV

HYS

15 °C

TSH

CC

< 12 V

OUT

< VCC

OUT

< 12 V

OUT

< +1 V

OUT

DE = 0 V, RE
DE = 0 V, RE

DE, DI, RE
DE, DI, RE
DE, DI, RE
DE, DI, RE

= 0 V, VCC = 0 V or 3.6 V, VIN = 12 V
= 0 V, VCC = 0 V or 3.6 V, VIN = −7 V

ΔVTH

I

A, IB

OSR

OZR

15 mV VA + VB = 0 V

125 μA DE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V

= −1 mA

OUT

= 1 mA

OUT

±80 mA 0 V < VRO < VCC

±1 μA VCC = 3.6 V, 0 V < V

OUT

< VCC

CC

CC

= VCC

, RE = 0 V
, RE = VCC

= 0 V

I

SHDN

0.8 1.5 mA

0.8 1.5 mA

0.05 10 μA

No load, DE = V
No load, DE = V
No load, DE = 0 V, RE
DE = 0 V, RE

Rev. B | Page 4 of 20

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TIMING SPECIFICATIONS—ADM3070E/ADM3071E/ADM3072E

VCC = 3.3 V ± 10%, TA = T

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DRIVER

Maximum Data Rate 250 kbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
Rise Time/Fall Time tDR/tDF 350 1600 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
|t

− t

DPLH

| Differential Driver Output Skew t

DPHL

Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t

RECEIVER

Maximum Data Rate 250 kbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
|t

− t

RPLH

| Output Skew t

RPHL

Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t

TIME TO SHUTDOWN t

1

VCC = 3.3 V.

MIN

to T

, unless otherwise noted.

MAX

250 1500 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)

DPLH

250 1500 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)

DPHL

200 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)

DSKEW

2500 ns See Figure 10

DZH

2500 ns See Figure 11

DZL

100 ns See Figure 11

DLZ

100 ns See Figure 10

DHZ

5500 ns See Figure 10

DZH(SHDN)

5500 ns See Figure 11

DZL(SHDN)

200 ns CL = 15 pF (see Figure 12 and Figure 13)

RPLH

200 ns CL = 15 pF (see Figure 12 and Figure 13)

RPHL

30 ns CL = 15 pF (see Figure 12 and Figure 13)

RSKEW

50 ns See Figure 14

RZH

50 ns See Figure 14

RZL

50 ns See Figure 14

RLZ

50 ns See Figure 14

RHZ

4000 ns See Figure 14

RZH(SHDN)

4000 ns See Figure 14

RZL(SHDN)

50 200 600 ns

SHDN

1

Rev. B | Page 5 of 20

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TIMING SPECIFICATIONS—ADM3073E/ADM3074E/ADM3075E

VCC = 3.3 V ± 10%, TA = T

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

DRIVER

Maximum Data Rate 500 kbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
Rise Time/Fall Time tDR/tDF 200 800 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
|t

− t

DPLH

| Differential Driver Output Skew t

DPHL

Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t

RECEIVER

Maximum Data Rate 500 kbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
|t

− t

RPLH

| Output Skew t

RPHL

Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t

TIME TO SHUTDOWN t

MIN

to T

, unless otherwise noted.

MAX

180 800 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)

DPLH

180 800 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)

DPHL

DSKEW

2500 ns See Figure 10

DZH

2500 ns See Figure 11

DZL

100 ns See Figure 11

DLZ

100 ns See Figure 10

DHZ

DZH(SHDN)

DZL(SHDN)

200 ns CL = 15 pF (see Figure 12 and Figure 13)

RPLH

200 ns CL = 15 pF (see Figure 12 and Figure 13)

RPHL

RSKEW

50 ns See Figure 14

RZH

50 ns See Figure 14

RZL

50 ns See Figure 14

RLZ

50 ns See Figure 14

RHZ

RZH(SHDN)

RZL(SHDN)

50 200 600 ns

SHDN

100 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)

4500 ns See Figure 10

4500 ns See Figure 11

30 ns CL = 15 pF (see Figure 12 and Figure 13)

4000 ns See Figure 14

4000 ns See Figure 14

Rev. B | Page 6 of 20