ADM3076E/ADM3077E/ADM3078E: 16 Mbps
Half- and full-duplex options
True fail-safe receiver inputs
Up to 256 nodes on the bus
−40°C to +125°C temperature option
Hot-swap input structure on DE and
Reduced slew rates for low EMI
Low power shutdown current (all except ADM3071E/
ADM3074E/ADM3077E)
Outputs high-Z when disabled or powered off
Common-mode input range: −7 V to +12 V
Thermal shutdown and short-circuit protection
8-lead and 14-lead narrow SOIC packages
RE
pins
FUNCTIONAL BLOCK DIAGRAMS
CC
ADM3070E/
ADM3073E/
ADM3076E
RO
RE
DE
DI
RO
R
D
GND
Figure 1.
CC
ADM3071E/
ADM3074E/
ADM3077E
R
A
B
Z
Y
06285-001
A
B
APPLICATIONS
Power/energy metering
Industrial control
Lighting systems
Telecommunications
Security systems
Instrumentation
GENERAL DESCRIPTION
The ADM307xE are 3.3 V, low power data transceivers with
±15 kV ESD protection suitable for full- and half-duplex
communication on multipoint bus transmission lines. They
are designed for balanced data transmission, and they comply
with TIA/EIA standards: RS-485 and RS-422.
The devices have a ⅛ unit load receiver input impedance, which
allows up to 256 transceivers on a bus. Because only one driver
should be enabled at any time, the output of a disabled or powereddown driver is tristated to avoid overloading the bus.
The receiver inputs have a true fail-safe feature, which eliminates
the need for external bias resistors and ensures a logic high
output level when the inputs are open or shorted. This guarantees that the receiver outputs are in a known state before
communication begins and when communication ceases.
DI
RO
RE
DE
DI
D
GND
Figure 2.
CC
ADM3072E/
ADM3075E/
ADM3078E
R
D
GND
Figure 3.
Z
Y
6285-002
A
B
06285-003
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The driver outputs of the 250 kbps and 500 kbps devices are slew
rate limited to reduce EMI and data errors caused by reflections
from improperly terminated buses. Excessive power dissipation
caused by bus contention or by output shorting is prevented
with a thermal shutdown circuit.
Table 1. Selection Table
Half/Full
Part No.
ADM3070E Full 0.25 Yes Yes Yes 256 Yes 14
ADM3071E Full 0.25 Yes No No 256 Yes 8
ADM3072E Half 0.25 Yes Yes Yes 256 Yes 8
ADM3073E Full 0.5 Yes Yes Yes 256 Yes 14
ADM3074E Full 0.5 Yes No No 256 Yes 8
ADM3075E Half 0.5 Yes Yes Yes 256 Yes 8
ADM3076E Full 16 No Yes Yes 256 Yes 14
ADM3077E Full 16 No No No 256 Yes 8
ADM3078E Half 16 No Yes Yes 256 Yes 8
Duplex
Data Rate
(Mbps)
Slew Rate
Limited
Driver/Receiver
Enable
The parts are fully specified over the industrial temperature
ranges and are available in 8-lead and 14-lead narrow SOIC
packages.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Differential Output Voltage VOD 2.0 VCC V RL = 100 Ω (RS-422) (see Figure 7)
1.5 VCC V RL = 54 Ω (RS-485) (see Figure 7)
V
Δ|VOD| for Complementary Output States1ΔVOD
Common-Mode Output Voltage VOC V
Δ|VOC| for Complementary Output States
Short-Circuit Output Current I
−250 −40 mA −7 V < V
Short-Circuit Foldback Output Current I
−20 mA −7 V < V
Output Leakage (Y, Z) Full Duplex IO 125 μA
−100 μA
Logic Inputs
Input High Voltage VIH 2.0 V
Input Low Voltage VIL 0.8 V
Input Hysteresis V
Logic Input Current IIN ±1 μA
Input Impedance First Transition 1 10 kΩ DE
Thermal Shutdown Threshold TTS 175 °C
Thermal Shutdown Hysteresis T
RECEIVER
Differential Inputs
Differential Input Threshold Voltage VTH −200 −125 −50 mV −7 V < VCM < +12 V
Input Hysteresis
Input Resistance (A, B) RIN 96 kΩ −7 V < VCM < +12 V
Input Current (A, B)
−100 μA DE = 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
RO Logic Output
Output High Voltage VOH VCC − 0.6 V I
Output Low Voltage VOL 0.4 V I
Short-Circuit Output Current I
Tristate Output Leakage Current I
POWER SUPPLY
Supply Current ICC 0.8 1.5 mA
Shutdown Current
ESD PROTECTION
A, B, Y, Z Pins ±15 kV Human body model
All Pins Except A, B, Y, Z Pins ±4 kV Human body model
1
Δ|VOD| and Δ|VOC| are the changes in VOD and VOC, respectively, when the DI input changes state.
MIN
to T
, unless otherwise noted.
MAX
V No load
CC
0.2 V RL = 54 Ω or 100 Ω (see Figure 7)
/2 3 V RL = 54 Ω or 100 Ω (see Figure 7)
1
ΔV
0.2 V RL = 54 Ω or 100 Ω (see Figure 7)
OC
40 250 mA 0 V < V
OSD
20 mA (VCC − 1 V) < V
OSDF
100 mV
HYS
15 °C
TSH
CC
< 12 V
OUT
< VCC
OUT
< 12 V
OUT
< +1 V
OUT
DE = 0 V, RE
DE = 0 V, RE
DE, DI, RE
DE, DI, RE
DE, DI, RE
DE, DI, RE
= 0 V, VCC = 0 V or 3.6 V, VIN = 12 V
= 0 V, VCC = 0 V or 3.6 V, VIN = −7 V
ΔVTH
I
A, IB
OSR
OZR
15 mV VA + VB = 0 V
125 μA DE = 0 V, VCC = 0 V or 3.6 V, VIN = 12 V
= −1 mA
OUT
= 1 mA
OUT
±80 mA 0 V < VRO < VCC
±1 μA VCC = 3.6 V, 0 V < V
OUT
< VCC
CC
CC
= VCC
, RE = 0 V
, RE = VCC
= 0 V
I
SHDN
0.8 1.5 mA
0.8 1.5 mA
0.05 10 μA
No load, DE = V
No load, DE = V
No load, DE = 0 V, RE
DE = 0 V, RE
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 250 kbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
Rise Time/Fall Time tDR/tDF 350 1600 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
|t
− t
DPLH
| Differential Driver Output Skew t
DPHL
Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t
RECEIVER
Maximum Data Rate 250 kbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
|t
− t
RPLH
| Output Skew t
RPHL
Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t
TIME TO SHUTDOWN t
1
VCC = 3.3 V.
MIN
to T
, unless otherwise noted.
MAX
250 1500 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
DPLH
250 1500 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
DPHL
200 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 500 kbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
Rise Time/Fall Time tDR/tDF 200 800 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
|t
− t
DPLH
| Differential Driver Output Skew t
DPHL
Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t
RECEIVER
Maximum Data Rate 500 kbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
|t
− t
RPLH
| Output Skew t
RPHL
Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t
TIME TO SHUTDOWN t
MIN
to T
, unless otherwise noted.
MAX
180 800 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
DPLH
180 800 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
DPHL
DSKEW
2500 ns See Figure 10
DZH
2500 ns See Figure 11
DZL
100 ns See Figure 11
DLZ
100 ns See Figure 10
DHZ
DZH(SHDN)
DZL(SHDN)
200 ns CL = 15 pF (see Figure 12 and Figure 13)
RPLH
200 ns CL = 15 pF (see Figure 12 and Figure 13)
RPHL
RSKEW
50 ns See Figure 14
RZH
50 ns See Figure 14
RZL
50 ns See Figure 14
RLZ
50 ns See Figure 14
RHZ
RZH(SHDN)
RZL(SHDN)
50 200 600 ns
SHDN
100 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 16 Mbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
Rise Time/Fall Time tDR/tDF 15 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
|t
− t
DPLH
| Differential Driver Output Skew t
DPHL
Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t
RECEIVER
Maximum Data Rate 16 Mbps
Propagation Delay, Low-to-High Level t
Propagation Delay, High-to-Low Level t
|t
− t
RPLH
| Output Skew t
RPHL
Enable to Output High t
Enable to Output Low t
Disable Time from Low t
Disable Time from High t
Enable Time from Shutdown to High t
Enable Time from Shutdown to Low t
TIME TO SHUTDOWN t
MIN
to T
, unless otherwise noted.
MAX
50 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
DPLH
50 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
DPHL
8 ns CL = 50 pF, RL = 54 Ω (see Figure 8 and Figure 9)
VCC to GND −0.3 V to +6 V
Digital Input/Output Voltage (DE, RE, DI)
Receiver Output Voltage (RO) −0.3 V to (VCC + 0.3 V)
Driver Output (A, B, Y, Z)/Receiver
Input (A, B) Voltage −8 V to +13 V
Driver Output Current ±250 mA
Operating Temperature Range
ADM307xEA −40°C to +85°C
ADM307xEY −40°C to +125°C
Storage Temperature Range −65°C to +150°C
θJA Thermal Impedance
8-Lead SOIC_N 158°C/W
14-Lead SOIC_N 120°C/W
Lead Temperature, Soldering (20 sec) 260°C
−0.3 V to +6 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Receiver Output. When enabled, if (A − B) ≥ −50 mV, RO is high. If
(A − B) ≤ −200 mV, RO is low.
3 N/A 2
Receiver Output Enable. A low level enables the receiver output.
RE
A high level places it in a high impedance state. If RE
is high and DE
is low, the device enters a low power shutdown mode.
4 N/A 3 DE
Driver Output Enable. A high level enables the driver differential
A and B outputs. A low level places it in a high impedance state. If
is high and DE is low, the device enters a low power shutdown mode.
RE
5 3 4 DI
Driver Input. With a half-duplex part when the driver is enabled, a
logic low on DI forces A low and B high; a logic high on DI forces
A high and B low. With a full-duplex part when the driver is enabled,
a logic low on DI forces Y low and Z high; a logic high on DI forces
Y high and Z low.
6, 7 4 5 GND
9 5 N/A Y
N/A N/A 6 A
12 8 N/A A
10 6 N/A Z
N/A N/A 7 B
11 7 N/A B
14 1 8 V
CC
Ground.
Noninverting Driver Output.
Noninverting Receiver Input A and Noninverting Driver Output A.
Noninverting Receiver Input A.
Inverting Driver Output.
Inverting Receiver Input B and Inverting Driver Output B.
Inverting Receiver Input B.
Power Supply, 3.3 V ± 10%. Bypass VCC to GND with a 0.1 μF capacitor.
1, 8, 13 N/A N/A NC No Connect. Not internally connected; can be connected to GND.
The ADM307xE series are high speed transceivers for RS485
and RS-422 communications. Each device contains one driver
and one receiver. All devices feature fail-safe circuitry, which
guarantees a logic high receiver output when the receiver inputs
are open or shorted or when they are connected to a terminated
transmission line with all drivers disabled (see the Receiver FailSafe section). The ADM307xE also feature a hot-swap capability,
allowing line insertion without erroneous data transfer (see the
Hot-Swap Capability section). The ADM3070E/ADM3071E/
ADM3072E feature reduced slew rate drivers that minimize
EMI and reduce reflections caused by improperly terminated
cables, allowing for error-free data transmission at rates up to
250 kbps.
The ADM3073E/ADM3074E/ADM3075E also offer slew rate
limits, allowing transmit speeds up to 500 kbps. The ADM3076E/
ADM3077E/ADM3078E driver slew rates are not limited, making
possible transmit speeds of up to 16 Mbps. The ADM3072E/
ADM3075E/ADM3078E are half-duplex transceivers; the
ADM3070E/ADM3071E/ADM3073E/ADM3074E/ADM3076E/
ADM3077E are each full-duplex transceivers. All devices operate
from a single 3.3 V supply. Drivers are output short-circuit
current limited, and thermal shutdown circuitry protects
drivers against excessive power dissipation. When activated,
the thermal shutdown circuitry places the driver outputs into
a high impedance state.
The ADM307xE family guarantees a logic high receiver output
when the receiver inputs are shorted, open, or connected to a
terminated transmission line with all drivers disabled. This is
done by setting the receiver input threshold between −50 mV
and −200 mV. If the differential receiver input voltage (A − B)
is greater than or equal to −50 mV, RO is logic high. If A − B
is less than or equal to −200 mV, RO is logic low. In the case
of a terminated bus with all transmitters disabled, the receiver
differential input voltage is pulled to 0 V by the termination.
With the receiver thresholds of the ADM307xE family, this
results in a logic high with a 50 mV minimum noise margin.
When a circuit board is inserted into a hot (or powered) backplane, differential disturbances to the data bus can lead to data
errors. During this period, processor logic output drivers are
high impedance and are unable to drive the DE and
RE
inputs
of the RS-485 transceivers to a defined logic level. Leakage currents
up to ±10 μA from the high impedance state of the processor
logic drivers can cause standard CMOS enable inputs of a transceiver to drift to an incorrect logic level. Additionally, parasitic
circuit board capacitance can cause coupling of V
or GND to
CC
the enable inputs. Without the hot-swap capability, these factors
can improperly enable the driver or receiver of the transceiver.
When V
RE
rises, an internal pull-down circuit holds DE low and
CC
high. After the initial power-up sequence, the pull-down
circuit becomes transparent, resetting the hot-swap tolerable input.
LINE LENGTH vs. DATA RATE
The RS-485/RS-422 standard covers line lengths up to 4000 feet.
For line lengths greater than 4000 feet, Figure 37 illustrates an
example line repeater.
±15 kV ESD PROTECTION
Two coupling methods are used for ESD testing: contact
discharge and air-gap discharge. Contact discharge calls for
a direct connection to the unit being tested. Air-gap discharge
uses a higher test voltage but does not make direct contact with
the test unit. With air-gap discharge, the discharge gun is moved
toward the unit under test, developing an arc across the air gap,
thus the term air-gap discharge. This method is influenced by
humidity, temperature, barometric pressure, distance, and rate
of closure of the discharge gun. The contact discharge method,
while less realistic, is more repeatable and is gaining acceptance
and preference over the air-gap method.
Although very little energy is contained within an ESD pulse, the
extremely fast rise time, coupled with high voltages, can cause
failures in unprotected semiconductors. Catastrophic destruction can occur immediately as a result of arcing or heating.
Even if catastrophic failure does not occur immediately, the
device can suffer from parametric degradation that can result
in degraded performance. The cumulative effects of continuous
exposure can eventually lead to complete failure.
Input/output lines are particularly vulnerable to ESD damage.
Simply touching or connecting an input/output cable can result
in a static discharge that damages or completely destroys the
interface product connected to the input/output port. It is
extremely important, therefore, to have high levels of ESD
protection on the input/output lines.
The ESD discharge can induce latch-up in the device under test,
so it is important that ESD testing on the input/output pins be
carried out while device power is applied. This type of testing
is more representative of a real-world input/output discharge,
which occurs when equipment is operating normally.
The transmitter outputs and receiver inputs of the ADM307xE
family are characterized for protection to a ±15 kV limit using
the human body model.
HUMAN BODY MODEL
Figure 33 shows the human body model and the current
waveform it generates when discharged into low impedance.
This model consists of a 100 pF capacitor charged to the ESD
voltage of interest, which is then discharged into the test device
through a 1.5 kΩ resistor.
HIGH
VOLTAGE
GENERATOR
HUMAN BODY MODEL
ESD ASSOC. STD 55.1
100%
90%
PEAK
I
36.8
10%
t
RL
Figure 33. Human Body Model and Current Waveform
R1
ESD TEST METHOD
t
DL
R2
C1
R2
1.5kC1100pF
DEVICE
UNDER
TEST
TIME
t
256 TRANSCEIVERS ON THE BUS
The standard RS-485 receiver input impedance is 12 kΩ
(1 unit load), and the standard driver can drive up to 32 unit
loads. The ADM307xE family of transceivers has a ⅛ unit
load receiver input impedance (96 kΩ), allowing up to 256
transceivers to be connected in parallel on one communication line. Any combination of these devices and other
RS-485 transceivers with a total of 32 unit loads or fewer
can be connected to the line.
REDUCED EMI AND REFLECTIONS
The ADM3070E/ADM3071E/ADM3072E feature reduced
slew rate drivers that minimize EMI and reduce reflections
caused by improperly terminated cables, allowing for errorfree data transmission at rates up to 250 kbps. The ADM3073E/
ADM3074E/ADM3075E offer higher driver output slew rate
limits, allowing for transmit speeds of up to 500 kbps.
LOW POWER SHUTDOWN MODE
(ALL EXCEPT ADM3071E/ADM3074E/ADM3077E)
Low power shutdown mode is initiated by bringing both RE
high and DE low. In shutdown mode, the device draws less
than 1 μA of supply current.
RE
and DE can be driven simultaneously, but the parts are guaranteed not to enter shutdown if
RE
is high and DE is low for fewer than 50 ns. If the inputs are
in this state for 600 ns or more, the parts are guaranteed to enter
shutdown. Enable times t
originally in a low power shutdown state (see the
and Switching Characteristics
and t
) assume that the part was originally shut down. It
ZL(SHDN)
and tZL assume that the part was not
ZH
Tes t Ci rcu its
section). Enable times (t
ZH(SHDN)
takes drivers and receivers longer to become enabled from low
power shutdown mode (t
receiver disable mode (t
ZH
ZH(SHDN)
, tZL).
, t
ZL(SHDN)
) than from driver/
DRIVER OUTPUT PROTECTION
The ADM307xE family features two methods to prevent
circuits over the whole common-mode voltage range (see
Figure 22 and Figure 23). In addition, a thermal shutdown
circuit forces the driver outputs into a high impedance state
if the die temperature rises excessively.
TYPICAL APPLICATIONS
The ADM3072E/ADM3075E/ADM3078E transceivers are
designed for bidirectional data communications on multipoint
bus transmission lines. Figure 34 shows a typical network
applications circuit. The ADM3071E/ADM3074E/ADM3077E
transceivers are designed for point-to-point transmission lines
(see Figure 35). The ADM3070E/ADM3073E/ADM3076E
transceivers are designed for full-duplex RS-485 networks
(see Figure 36).
To minimize reflections, terminate the line at both ends with
a termination resistor (the value of the termination resistor
should be equal to the characteristic impedance of the cable
used) and keep stub lengths off the main line as short as possible.
excessive output current and power dissipation caused by
faults or by bus contention. Current limit protection on the
output stage provides immediate protection against short
ADM3072E/
ADM3075E/
ADM3078E
RO
RE
DE
DI
NOTES
1. MAXIMUM NUMBER OF NODES: 256.
2.
R
D
IS EQUAL TO THE CHARACTERI STIC IM PEDANCE OF THE CABLE USED.
CONTROLL ING DIMENSI ONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
85
1
1.27 (0.0500)
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-012-A A
BSC
6.20 (0.2441)
5.80 (0.2284)
4
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
0.31 (0.0122)
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
0.40 (0.0157)
45°
012407-A
Figure 38. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
8.75 (0.3445)
8.55 (0.3366)
BSC
8
7
6.20 (0.2441)
5.80 (0.2283)
1.75 (0.0689)
1.35 (0.0531)
SEATING
PLANE
8°
0°
0.25 (0.0098)
0.17 (0.0067)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
45°
4.00 (0.1575)
3.80 (0.1496)
0.25 (0.0098)
0.10 (0.0039)
COPLANARIT Y
0.10
14
1
1.27 (0.0500)
0.51 (0.0201)
0.31 (0.0122)
CONTROLL ING DIMENSIONS ARE IN MILLIMETERS; INCH DI MENSIONS
(IN PARENTHESES) ARE ROUNDED-O FF MIL LIMETE R EQUIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AB
Figure 39. 14-Lead Standard Small Outline Package [SOIC_N]