ANALOG DEVICES ADM2914 Service Manual

Quad UV/OV Positive/Negative

V

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FEATURES

Quad UV/OV positive/negative supervisor
Supervises up to 2 negative rails
Adjustable UV and OV input thresholds
High threshold accuracy over temperature: ±1.5%
1 V buffered reference output
Open-drain
Adjustable reset timeout with disable option
Outputs guaranteed down to V
Glitch immunity
62 μA supply current
16-lead QSOP package

APPLICATIONS

Server supply monitoring
FPGA/DSP core and I/O voltage monitoring
Telecommunications equipment
Medical equipment

and OV reset outputs

UV

of 1 V

CC

VH1

VL1

VH2

VL2

VH3

VL3

VH4

VL4

Voltage Supervisor

FUNCTIONAL BLOCK DIAGRAM

CC

ADM2914

500mV

500mV

500mV

MUX

500mV

ADM2914

TIMER

TIMER

UV

OUTPUT

LOGIC

OV

LOGIC

REF

LATCH/DIS

REF

GENERAL DESCRIPTION

The ADM2914 is a quad voltage supervisory IC ideally suited
for monitoring multiple rails in a wide range of applications.

Each monitored rail has two dedicated input pins, VHx and VLx,
which allows each rail to be monitored for both overvoltage
(OV) and undervoltage (UV) conditions. A common active low
undervoltage (
of the monitored voltage rails.

The ADM2914 includes a 1 V buffered reference output, REF,
that acts as an offset when monitoring a negative voltage. The
three-state SEL pin determines the polarity of the third and
fourth inputs, that is, it configures the device to monitor
positive or negative supplies.

The device incorporates an internal shunt regulator that enables
the device to be used in higher voltage systems. This feature
requires a resistor to be placed between the main supply rail and

UV

) and overvoltage (OV) pin is shared by each

SEL GND

Figure 1.

the V

pin to limit the current flow into the VCC pin to no

CC

greater than 10 mA. The ADM2914 uses the internal shunt
regulator to regulate V

if the supply line exceeds the absolute

CC

maximum ratings.

The ADM2914 is available in two models. The ADM2914-1
offers a latching overvoltage output that can be cleared by
toggling the

pin that can override and disable both the

LATCH

input pin. The ADM2914-2 has a disable

OV

and UV output

signals.

The ADM2914 is available in a 16-lead QSOP package. The
device operates over the extended temperature range of −40°C
to +125°C.

08170-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009-2010 Analog Devices, Inc. All rights reserved.

ADM2914

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TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1 

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 4

ESD Caution .................................................................................. 4

Pin Configurations and Function Descriptions ........................... 5

Typical Performance Characteristics ............................................. 6

Theory of Operation ........................................................................ 8

Voltage Supervision ...................................................................... 8

Polarity Configuration ................................................................. 8

Monitoring Pin Connections ...................................................... 9

Threshold Accuracy ................................................................... 10

Voltage Monitoring Example .................................................... 10

Power-Up and Power-Down ..................................................... 11

UV

/OV Timing Characteristics ............................................... 11

Timer Capacitor Selection ........................................................ 11

UV

and OV Rise and Fall Times .............................................. 12

UV

/OV Output Characteristics ............................................... 12

Glitch Immunity ......................................................................... 12

Undervoltage Lockout (UVLO) ............................................... 12

Shunt Regulator .......................................................................... 12

OV

Latch (ADM2914-1) ........................................................... 13

Disable (ADM2914-2) ............................................................... 13

Typical Applications ....................................................................... 14

Outline Dimensions ....................................................................... 16

Ordering Guide .......................................................................... 16

REVISION HISTORY

2/10—Rev. A: Rev. B

Changes to Figure 17 and Figure 18 ............................................... 9

12/09—Rev. 0: Rev. A

Changes to Shunt Regulator Section ............................................ 12

5/09—Revision 0: Initial Version

Rev. B | Page 2 of 16

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SPECIFICATIONS

TA = −40°C to +85°C. Typical values at TA = 25°C, unless otherwise noted. VCC = 3.3 V, VLx = 0.45 V, VHx = 0.55 V,
SEL = V

, DIS = open, unless otherwise noted.

CC

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SHUNT REGULATOR

VCC Shunt Regulator Voltage, V

SHUNT

6.2 6.6 7.0 V TA = −40°C to +125°C
VCC Shunt Regulator Load Regulation, ∆V

SHUNT

SUPPLY

Supply Voltage, V
Minimum VCC Output Valid, V
Supply Undervoltage Lockout, V
Supply Undervoltage Lockout Hysteresis, ∆V
Supply Current, I

1

CC

CCR(MIN)

CC(UVLO)

CC(HYST)

CC

REFERENCE OUTPUT

Reference Output Voltage, V

REF

0.985 1 1.020 V TA = −40°C to +125°C
UNDERVOLTAGE/OVERVOLTAGE CHARACTERISTICS

Undervoltage/Overvoltage Threshold, V
Undervoltage/Overvoltage Threshold to Output Delay, t
VHx, VLx Input Current, I

VHL

UOT

UOD

±30 nA TA = −40°C to +125°C
UV

/OV Timeout Period, t

UOTO

6 8.5 14 ms TA = −40°C to +125°C
OV

LATCH CLEAR INPUT (ADM2914-1)

OV

Latch Clear Threshold Input High, V

OV

Latch Clear Threshold Input Low, V

LATCH

Input Current, I

LATCH

LATCH

LATCH

(IH)

(IL)

DISABLE INPUT (ADM2914-2)

DIS Input High, V
DIS Input Low, V
DIS Input Current, I

DIS(IH)

DIS(IL)

DIS

TIMER CHARACTERISTICS

TIMER Pull-Up Current, I

TIMER(UP)

−1.2 −2.1 −2.8 A TA = −40°C to +125°C
TIMER Pull-Down Current, I

TIMER(DOWN)

1.2 2.1 2.8 A TA = −40°C to +125°C
TIMER Disable Voltage, V

TIMER(DIS)

OUTPUT VOLTAGE

Output Voltage High, UV/OV, V

Output Voltage Low, UV/OV, V

OH

OL

0.01 0.15 V

THREE-STATE INPUT SEL

Low Level Input Voltage, VIL 0.4 V
High Level Input Voltage, VIH 1.4 V
Pin Voltage When Left in High-Z State, V

Z

0.6 0.9 1.2 V TA = −40°C to +125°C
SEL High, Low Input Current, I
Maximum SEL Input Current, I

1

The maximum voltage on the VCC pin is limited by the input current. The VCC pin has an internal 6.5 V shunt regulator and, therefore, a low impedance supply greater

than 6 V may exceed the maximum allowed input current. When operating from a higher supply than 6 V, always use a dropper resistor.

SEL

SEL(MAX)

6.2 6.6 6.9 V ICC = 5 mA

200 300 mV ICC = 2 mA to 10 mA

2.3 V

V

SHUNT

1 V DIS = 0 V

1.9 2 2.1 V DIS = 0 V, VCC rising
5 25 50 mV DIS = 0 V
62 100 A VCC = 2.3 V to 6 V

0.985 1 1.015 V I

= ±1 mA

VREF

492.5 500 507.5 mV
50 125 500 s VHx = V

UOT

±15 nA

6 8.5 12.5 ms C

TIMER

= 1 nF

1.2 V

0.8 V

> 0.5 V

±1 A

V

LATCH

1.2 V

0.8 V
1 2 3 A V

−1.3 −2.1 −2.8 A V

1.3 2.1 2.8 A V

> 0.5 V

DIS

TIMER

TIMER

= 0 V

= 1.6 V

−180 −270 mV Referenced to VCC

= 2.3 V; I

1 V

0.1 0.3 V

0.7 0.9 1.1 V I

V

CC

= 2.3 V; I

V

CC

= 1 V; IUV = 100 A

V

CC

= ±10 A

SEL

±25 A
±30 A SEL tied to VCC or GND

LATCH

− 5 mV or VLx = V

= −1 A

/

OV

UV

= 2.5 mA

/

OV

UV

= VCC,

+ 5 mV

UOT

Rev. B | Page 3 of 16

ADM2914

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VCC −0.3 V to +6 V
UV, OV
TIMER −0.3 V to (VCC + 0.3 V)
VLx, VHx, LATCH, DIS, SEL
ICC 10 mA
Reference Load Current (I
IUV, IOV 10 mA

Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Lead Temperature (Soldering, 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

) ±1 mA

REF

−0.3 V to +16 V

−0.3 V to +7.5 V

Table 3. Thermal Resistance

Package Type θJA Unit

16-Lead QSOP 104 °C/W

ESD CAUTION

Rev. B | Page 4 of 16

ADM2914

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

VH1

VL1

VH2

VL2

VH3

VL3

VH4

VL4

1

2

3

ADM2914-1

4

TOP VIEW

5

(Not to Scale)

6

7

8

16

15

14

13

12

11

10

9

V

CC

TIMER

SEL

LATCH

UV

OV

REF

GND

08170-002

Figure 2. ADM2914-1 Pin Configuration Figure 3. ADM2914-2 Pin Configuration

Table 4. Pin Function Descriptions

Mnemonic
Pin No. ADM2914-1 ADM2914-2 Description

1 VH1 VH1
3 VH2 VH2
2 VL1 VL1
4 VL2 VL2
5 VH3 VH3
7 VH4 VH4

Voltage High Input 1 and Voltage High Input 2. If the voltage monitored by VH1 or VH2 drops
below 0.5 V, an undervoltage condition is detected. Connect to V

Voltage Low Input 1 and Voltage Low Input 2. If the voltage monitored by VL1 or VL2 rises above

0.5 V, an overvoltage condition is detected. Tie to GND when not in use.

Voltage High Input 3 and Voltage High Input 4. The polarity of these inputs is determined by the
state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage
and the voltage monitored by VH3 or VH4 drops below 0.5 V, an undervoltage condition is
detected. Conversely, when the input is configured as a negative voltage and the input drops

below 0.5 V, an overvoltage condition is detected. Connect to V
6 VL3 VL3
8 VL4 VL4

Voltage Low Input 3 and Voltage Low Input 4. The polarity of these inputs is determined by the

state of the SEL pin (see Table 5). When the monitored input is configured as a positive voltage

and the voltage monitored by VL3 or VL4 rises above 0.5 V, an overvoltage condition is detected.

Conversely, when the input is configured as a negative voltage and the input rises above 0.5 V, an

undervoltage condition is detected. Tie to GND when not in use.
9 GND GND Device Ground.
10 REF REF

Buffered Reference Output. This pin is a 1 V reference that is used as an offset when monitoring

negative voltages. This pin can source or sink 1 mA, and drive loads up to 1 nF. Larger capacitive

loads may lead to instability. Leave unconnected when not in use.
11

OV

OV Overvoltage Reset Output. OV is asserted low if a negative polarity input voltage drops below its

associated threshold or if a positive polarity input voltage exceeds its threshold. The ADM2914-1

allows OV to be latched low. The ADM2914-2 holds OV low for an adjustable timeout period

determined by the TIMER capacitor. This pin has a weak pull-up to VCC and can be pulled up to

16 V externally. Leave this pin unconnected when not in use.
12

UV

UV Undervoltage Reset Output. UV is asserted low if a negative polarity input voltage exceeds its

associated threshold or if a positive polarity input voltage drops below its threshold. UV

low for an adjustable timeout period set by the external capacitor tied to the TIMER pin. The UV

pin has a weak pull-up to V

resistor. Leave this pin unconnected when not in use.
13

LATCH

DIS

OV Latch Bypass Input/Clear Pin. When pulled high, the OV latch is cleared. When held high, the

output has the same delay and output characteristics as the UV output. When pulled low, the

OV

OV

output is latched when asserted. (Applies only to the ADM2914-1.)

OV and UV Disable Input. When pulled high, the OV and UV outputs are held high irrespective of

the state of the VHx and VLx input pins. However, if a UVLO condition occurs, the OV

outputs are asserted. This pin has a weak internal pull-down (2 µA) to GND. Leave this pin

unconnected when not in use. (Applies only to the ADM2914-2.)
14 SEL SEL

Input Polarity Select. This three-state input pin allows the polarity of VH3, VL3, VH4, and VL4 to be

configured. Connect to V

configurations (see Table 5).
15 TIMER TIMER

Adjustable Reset Delay Timer. Connect an external capacitor to the TIMER pin to program the

reset timeout delay. Refer to Figure 15 in the Typical Performance Characteristics section.

16 V

V

CC

CC

Connect this pin to V

Supply Voltage. V

CC

operates as a direct supply for voltages up to 6 V. For voltages greater than

CC

6 V, it operates as a shunt regulator. A dropper resistor must be used in this configuration to limit

the current to less than 10 mA. When used without the resistor, the voltage at this pin must not

exceed 6 V. A 0.1 F bypass capacitor or greater should be used.

Rev. B | Page 5 of 16

VH1

1

VL1

2

VH2

3

ADM2914-2

4

VL2

VH3

VL3

VH4

VL4

and can be pulled up to 16 V externally via an external pull-up

CC

or GND, or leave open to select one of three possible input polarity

CC

5

6

7

8

TOP VIEW

(Not to Scale)

CC

to bypass the timer.

V

16

CC

15

TIMER

SEL

14

DIS

13

UV

12

OV

11

REF

10

9

GND

08170-011

when not in use.

CC

when not in use.

is held

and UV

ADM2914

V

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TYPICAL PERFORMANCE CHARACTERISTICS

0.505

0.504

0.503

(V)

UOT

0.502

0.501

0.500

0.499

0.498

0.497

THRESHOLD VOLTAGE,

0.496

0.495

–40 –30 –20 –10 0 10 20 30 40 50 60 70 80

TEMPERATURE ( °C)

Figure 4. Input Threshold Voltage vs. Temperature

08170-012

6.80

6.75

6.70

6.65

(V)

6.60

CC

V

6.55

6.50

6.45

6.40
02468

–40°C

+85°C

+25°C

I

(mA)

CC

Figure 7. VCC Shunt Voltage vs. ICC

08170-014

10

100

95

90

85

80

75

(µA)

CC

I

70

65

60

55

50

–40 –15 10 35 60 85

VCC = 6V

VCC = 3.3V

VCC = 2.3V

TEMPERATURE (° C)

Figure 5. Supply Current vs. Temperature

6.80

6.75

6.70

6.65

(V)

6.60

CC

V

6.55

6.50

6.45

6.40
–40 –15 10 35 60 85

TEMPERATURE ( °C)

Figure 6. VCC Shunt Voltage vs. Temperature

200µA
1mA
2mA
5mA
10mA

1.005

1.004

1.003

(V)

REF

1.002

1.001

1.000

0.999

0.998

0.997

REFERENCE VOL TAGE, V

0.996

08170-013

0.995
–40 –20 0 20 40 60 80

TEMPERATURE (° C)

08170-016

Figure 8. Buffered Reference Voltage vs. Temperature

1000

900

800

700

600

500

400

300

TRANSIENT DURATION (µs)

200

100

08170-014

0

0.1 1 10 100

VCC = 6V

VCC = 2.3V

COMPARATOR OVERDRIVE (% OF V

RESET ASSERT ED
ABOVE THE LI NE

)

TH

08170-017

Figure 9. Transient Duration vs. Comparator Overdrive

Rev. B | Page 6 of 16

ADM2914

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(mA)

UV

PULL-DOW N CURRENT I

3.0

2.5

2.0

1.5

1.0

0.5

0

VHx = 0.45V
SEL = V

CC

UV = 150mV

UV = 50mV

12

11

(ms)

UOTO

10

9

8

7

UV/OV TIMEOUT PERIOD, t

6

–40 –15 10 3 5 60 85

Figure 10.

0.9

0.8

0.7

0.6

0.5

0.4

0.3

UV VOLTAGE (V)

0.2

0.1

0

–0.1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0

TEMPERATURE (°C)

UV

/OV Timeout Period vs. Temperature

WITH 10kΩ PULL-UP

WITHOUT PULL-UP

SUPPLY VOLTAGE, V

(V)

CC

Figure 11. UV Output Voltage vs. VCC

5.0

VHx = 0.55V

4.5

SEL = V

CC

4.0

3.5

3.0

2.5

2.0

UV VOLTAG E (V)

1.5

1.0

0.5

0

01234

SUPPLY VOLTAGE, V

(V)

CC

Figure 12. UV Output Voltage vs. VCC

08170-018

08170-019

08170-020

5

–0.5

012 345

1000

900

800

700

600

(mV)

OL

500

400

UV/OV, V

300

200

100

0

0510

SUPPLY VOLTAGE, V

Figure 13. I

+85°C

I

SINK

SINK

– 40°C

, IUV vs. VCC

(mA)

(V)

CC

+25°C

Figure 14. UV/OV Voltage Output Low vs. Output Sink Current

10k

(ms)

1k

UOTO

t

100

10

UV/OV TIMEOUT PERIOD,

1

0.1 1 10 100 1000
TIMER PI N CAPACITANCE C

TIMER

(nF)

Figure 15. UV/OV Timeout Period vs. Capacitance

08170-021

6

08170-022

15

08170-023

Rev. B | Page 7 of 16

ADM2914

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THEORY OF OPERATION

VOLTAGE SUPERVISION

The ADM2914 supervises up to four voltage rails for overvol­tage and undervoltage conditions. Two pins, VHx and VLx, are
assigned to monitor each rail, one for overvoltage detection and
the other for undervoltage detection. Each pin is connected to
the input of an internal voltage comparator, and its voltage level
is internally compared with a 0.5 V voltage reference with
accuracy of ±1.5%.

The output of each of the internal undervoltage comparators is
tied to a common
internal overvoltage comparators are tied to a common
output pin.

5

3.3V

PSU

2.5V

1.8V

UV

output pin. Likewise, the outputs of the

V

VH1

VL1

VH2

VL2

VH3

VL3

VH4

VL4

CC

ADM2914

LATCH/DIS

SEL

TIMER

UV

OV

OV

SYSTEM

POLARITY CONFIGURATION

The ADM2914 is capable of monitoring supply voltages of both
positive and negative polarities. The SEL pin is a three-state pin
that determines the polarity of Input 3 and Input 4. As summa­rized in Tab le 5 , the SEL pin is either connected to GND, V
or left unconnected.

When an input is configured to monitor a positive voltage, using
the three-resistor scheme shown in Figure 17, VHx is connected
to the high-side tap of the resistor divider and VLx is connected
to the low-side tap of the resistor divider.

Conversely, when an input is configured to monitor a negative
voltage, UVx and OVx are swapped internally. The negative
voltage for monitoring is then connected as shown in Figure 18.
VHx is still connected to the high-side tap and VLx is still
connected to the low-side tap. Within this configuration, an
undervoltage condition occurs when the monitored voltage is less
negative than the programmed threshold, and an overvoltage
condition occurs when the monitored voltage is more negative
than the configured threshold.

,

CC

REF

Figure 16. Typical Applications Diagram

GND

08170-003

Table 5. Polarity Configuration

Input 3 Input 4
SEL Pin Polarity UV Condition OV Condition Polarity UV Condition OV Condition

Connected to VCC Positive VH3 < 0.5 V VL3 > 0.5 V Positive VH4 < 0.5 V VL4 > 0.5 V
Left Unconnected Positive VH3 < 0.5 V VL3 > 0.5 V Negative VL4 > 0.5 V VH4 < 0.5 V
Connected to GND Negative VL3 > 0.5 V VH3 < 0.5 V Negative VL4 > 0.5 V VH4 < 0.5 V

Rev. B | Page 8 of 16

ADM2914

V

V

M

(

(

M

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MONITORING PIN CONNECTIONS

Positive Voltage Monitoring Scheme

When monitoring a positive supply, the desired nominal
operating voltage for monitoring is denoted by V
nominal current through the resistor divider, V
overvoltage trip point, and V

M

R

X

PH

R

Y

V

PL

R

Z

Figure 17. Positive Undervoltage/Overvoltage Monitoring Configuration

is the undervoltage trip point.

UV

ADM2914

VHx

VLx

UVx

0.5V

OVx

Figure 17 illustrates the positive voltage monitoring input connec­tion. Three external resistors, R
voltage for monitoring, V
low-side voltage, V

. The high-side voltage is connected to the

PL

, RY, and RZ, divide the positive

X

, into high-side voltage, VPH, and

M

corresponding VHx pin, and the low-side voltage is connected
to the corresponding VLx pin.

To trigger an overvoltage condition, the low-side voltage (in this
case, V
low-side voltage, V

) must exceed the 0.5 V threshold on the VLx pin. The

PL

, is given by the following equation:

PL

⎛

R

⎜

=

VV

PL

OV

⎜
⎝

⎞

Z

⎟

V5.0=

⎟

++

RRR

YX

Z

⎠

Also,

V

M

I

Therefore, R

RRR =++

YX

Z

, which sets the desired trip point for the

Z

overvoltage monitor, is calculated using the following equation:

()

VR)5.0(

M

=

Z

()

OV

(1)

()

IV

M

, IM is the

M

is the

OV

08170-004

To trigger the undervoltage condition, the high-side voltage,

, must exceed the 0.5 V threshold on the VHx pin. The

V

PH

high-side voltage, V

VV

=

UVPH

Because R

When R

is already known, RY can be expressed as follows:

Z

R −=

Y

()

and RZ are known, RX is calculated using the following

Y

, is given by the following equation:

PH

⎛

Y

⎜
⎜
⎝

)

V

)5.0(

M

()

IV

MUV

+

R

⎞

RR

Z

⎟

V5.0=

⎟

RRR

++

YX

Z

⎠

(2)

Z

equation:

V

)

X

M

I

()

R −−=

, IM, VOV, or VUV changes, each step must be recalculated.

If V

M

RR

(3)

Y

Z

Negative Voltage Monitoring Scheme

Figure 18 shows the circuit configuration for negative supply
voltage monitoring. To monitor the negative voltage, a 1 V
reference voltage is required to connect to the end node of the
voltage divider circuit. This reference voltage is generated
internally and is output through the REF pin.

REF

R

Z

V

NH

R

V

R

Figure 18. Negative Undervoltage/Overvoltage Monitoring Configuration

VHx

Y

NL

VLx

X

V

M

ADM2914

OVx

0.5V

UVx

08170-005

The equations described in the Positive Voltage Monitoring
Scheme section need some minor modifications for use with
negative voltage monitoring. The 1 V reference voltage is added
to the overall voltage drop; it must therefore be subtracted from

, VUV, and VOV before using each in the previous equations.

V

M

To monitor a negative voltage level, the resistor divider circuit
divides the voltage differential level between the 1 V reference
voltage and the negative supply voltage into high-side voltage,

, and low-side voltage, VNL. Similar to the positive voltage

V

NH

monitoring scheme, the high-side voltage, V
the corresponding VH
connected to the corresponding VL

pin, and the low-side voltage, VNL, is

X

pin. Refer to the Vol t a ge

X

, is connected to

NH

Monitoring Example section for more information.

Rev. B | Page 9 of 16

ADM2914

V

(

)

(

)

–

http://www.BDTIC.com/ADI

THRESHOLD ACCURACY

The reset threshold accuracy is fundamental, especially at lower
voltage levels. Consider an FPGA application that requires a 1 V
core voltage input with tolerance of ±5%, where the supply has a
specified regulation, for example, ±1.5%. As shown in Figure 19, to
ensure that the supply is within the FPGA input voltage require­ment range, its voltage level must be monitored for UV and OV
conditions. The voltage swing on the supply itself causes the
voltage band available for setting the monitoring threshold to be
quite narrow. In this example, the threshold voltages, including
the tolerances, must fit within a monitor region of only 0.035 V.
The ADM2914 device with 0.1% resistors can achieve this level
of accuracy.

OLTAGE

1.05V

1.015V

1V CORE

VOLTAGE

0.985V

0.95V

UV

+5% TOLERANCE

–5% TOLERANCE

Figure 19. Monitoring Threshold Accuracy Example

3.5% RANGE FOR
OV MONIT ORING

+1.5% SUPPLY REGULATION

–1.5% SUPPLY
REGULATION

3.5% RANGE FO R
UV MONITO RING

t

TIME

UOTO

VOLTAGE MONITORING EXAMPLE

To illustrate how the ADM2914 device works in a real application,
consider the 1 V input example shown in Figure 19, with the
addition of a −12 V rail.

The first step is to choose the nominal current flow through
both voltage divider circuits, for example, 5 µA.

For the 1 V ± 5% input, due to the specified ±1.5% regulation of
the supply, the UV and OV thresholds should be set in the middle
of the voltage monitoring band. In this case, on the ±3.25%
points of the supply, the UV threshold is 0.9675 V and the OV
threshold is 1.0325 V.

Input these values into Equation 1.

=

R

Z

()

Insert the value of R

=

R

Y

()

1)5.0(

6

−

()

1050325.1

×

into Equation 2.

Z

1)5.0(

6

−

()

1059675.0

×

Then substitute the calculated values for R
Equation 3.

1

=

R

X

6

−

105

×

This design approach meets the application specifications. As
described previously, the 1 V rail is specified with an input
requirement of ±5% and a supply tolerance of ±1.5%. This
effectively means that the OV threshold of the monitoring

k5.96

≈

k42.6k5.96

≈−

and RY into

Z

k5.96k42.6k5.96

≈−−

Rev. B | Page 10 of 16

08170-006

device, including all the tolerance factors, must fit within the

1.015 V to 1.05 V range. Similarly, the UV threshold range must
be between 0.95 V and 0.985 V.

The four worst-case scenarios of minimum and maximum
undervoltage and overvoltage thresholds are calculated as follows:

Minimum overvoltage threshold

⎛

V

MINOV

_

⎛

14925.0

+=

⎜

⎜
⎝

>=

⎜

1%)5.1V5.0(

+−=

⎜
⎝

+

)999.0)(6420500,96(

⎞
⎟

⎟

)001.1)(500,96(

⎠

V015.1V016.1

RR

−+−

YX

()

R

%1.0

+

Z

⎞

%)1.0(%)1.0(

⎟
⎟
⎠

Maximum overvoltage threshold

⎛
⎜

++=

V

MAXOV

_

V05.1V049.1

<=

1%)5.1V5.0(

⎜
⎝

()

R

Z

+++

RR

YX

−

%1.0

⎞

%)1.0(%)1.0(

⎟
⎟
⎠

The maximum and minimum overvoltage threshold values lie
within the 1.015 V to 1.05 V range specified. The minimum and
maximum undervoltage thresholds are calculated as follows:

Minimum undervoltage threshold

⎛
⎜

+−=

V

MINUV

_

V95.0V953.0

>=

1%)5.1V5.0(

⎜

()()

Y

⎝

−

R

%)1.0(

X

+++

RR

Z

⎞
⎟
⎟

%1.0%1.0

⎠

Maximum undervoltage threshold

⎛

V

MAXUV

_

<=

⎜

1%)5.1V5.0(

++=

⎜
⎝

V985.0V984.0

R

()

Y

%)1.0(

+

X

()

RR

Z

⎞
⎟
⎟

%1.0%1.0

−+−

⎠

Again, these values fit within the specified undervoltage
monitoring range. All four worst-case scenarios satisfy the
tolerance requirement; therefore, the design approach is valid.

12V RAIL

1V RAIL

5V

96.5kΩ

6.42Ω

96.5kΩ

Figure 20. Positive and Negative Supply Monitor Example

2.49MΩ

23.4kΩ

89.8kΩ

VH1

VL1

VL3

VH3

REF

V

CC

ADM2914

GND

OV

UV

SEL

08170-007

ADM2914

(

)

(

)

V

V

http://www.BDTIC.com/ADI

Next, consider a −12 V input, which is specified with a ±20%
input. The threshold accuracy required by the supply is chosen
to be within ±5% of the −12 V rail. Therefore, the overvoltage
threshold is set to −13.5 V, and the undervoltage threshold is

−10.5 V. The negative voltage scheme configuration requires
that the 1 V reference voltage be accounted for in Equation 1 to
Equation 3. The 1 V reference voltage is subtracted from V
V

, and VOV, and the absolute value of the result is taken.

UV

,

M

Equation 1 becomes

112)5.0(

=

R

Z

()

−−

6

−

()

10515.13

×−−

k8.89

≈

Refer to Figure 15 in the Typical Performance Characteristics
section, which illustrates the delay time as a function of the
timer capacitor value. A minimum capacitor value of 10 pF is
required. The chosen timer capacitor must have a leakage current
that is less than the 1.3 µA TIMER pin charging current. To
bypass the timeout period, connect the TIMER pin to V

Hx MONITOR TI MING

VHx

V

UOT

t

UOD

t

UOTO

.

CC

Insert the value of R

=

R

Y

()

To c al c ul ate R

()

=

R

X

into Equation 2.

Z

112)5.0(

−−

6

−

()

10515.10

×−−

, insert the value of RZ and RY into Equation 3.

X

112

−−

()()

6

−

105

×

≈−

k4.23k8.89

M49.2k4.23k8.89

≈−−

POWER-UP AND POWER-DOWN

On power-up, when VCC reaches 1 V, the active low UV output

OV

is asserted, and the
tage on the V
assert

CC

UV

low and OV high. When VCC exceeds 1.9 V (minimum),

the VHx and VLx inputs take control. When V

output pulls up to VCC. When the vol-

pin reaches 1 V, the ADM2914 is guaranteed to

and each of

CC

the VHx inputs are valid, an internal timer begins. Subsequent

UV

to an adjustable time delay,

weakly pulls high.

UV/OV TIMING CHARACTERISTICS

UV

is an active low output. It is asserted when any of the four
monitored voltages is below its associated threshold. When the
voltage on the V
UV

low for an adjustable period, t

pin is above 2 V, an internal timer holds

CC

, after the voltage on all

UOTO

the monitoring rails rises above their thresholds. This allows
time for all monitored power supplies to stabilize after power­up. Similarly, any monitored voltage that falls below its threshold
initiates a timer reset, and the timer starts again when all the
monitoring rails rise above their thresholds.

UV

The

and OV outputs are held asserted after all faults have
cleared for an adjustable timeout period, determined by the
value of the external capacitor attached to the TIMER pin.

TIMER CAPACITOR SELECTION

The UV and OV timeout period on the ADM2914 is programma­ble via the external timer capacitor, C
TIMER pin and ground. The timeout period, t
using the following equation:

tC

UOTOTIMER

F/sec)10)(115)((9−=

, placed between the

TIMER

, is calculated

UOTO

UV

VHx

UV

WHEN AN INPUT IS CONFIGURED TO MONITOR A NEGATIVE VOLTAGE,
VHx WILL TRIG GER AN OVERVOLTAGE CONDITION.

VLx

OV

WHEN AN INPUT IS CO NFIGURED TO MO NITOR A NEGATIVE VOLTAGE,
VLx WILL TRIGGER AN UNDERVOLTAGE CONDITION.

1V

UOD

)

CC

CC

VHx MONITOR T IMING (TIMER PI N TIED TO V

V

UOT

t

UOD

1V

Figure 21. VHx Positive Voltage Monitoring Timing Diagram

Lx MONITOR TIMING

V

UOT

t

UOD

1V

VLx MONITOR TI MING (T IMER PIN T IED TO V

V

VLx

UOT

t

UOD

OV

Figure 22. VLx Positive Voltage Monitoring Timing Diagram

1V

t

UOD

t

UOTO

t

08170-024

)

08170-025

Rev. B | Page 11 of 16

ADM2914

V

V

−

−

(

=

http://www.BDTIC.com/ADI

UV AND OV RISE AND FALL TIMES

The UV and OV output rise times (from 10% to 90%) can be
approximated using the following formula:

))((2.2

CRt−≈

UPPULLR

LOAD

where:

is the internal weak pull-up resistance with an approx-

R

PULL-UP

imate value of 400 kΩ at room temperature with V
C

is the external load capacitance on the output pin.

LOAD

UV

When a fault occurs, the

or OV output fall time can be

> 1 V.

CC

expressed as

))((2.2

CRt−≈

LOADDOWNPULL

where R

F

PULL-DOWN

is the internal pull-down resistance, which is
approximately 50 Ω. Assuming a load capacitance of 150 pF, the
fall time is 16.5 ns.

UV/OV OUTPUT CHARACTERISTICS

Both the OV and UV outputs have a strong pull-down to
ground and a weak internal pull-up to V

. This permits the pins

CC

to behave as open-drain outputs. When the rise time on the pin
is not critical, the weak pull-up removes the requirement for an
external pull-up resistor. The open-drain configuration allows
for wire-OR’ing of outputs, which is particularly useful when
more than one signal needs to pull down on the output.

= 1 V, a maximum VOL = 0.15 V at UV is guaranteed. At

At V

CC

V

= 1 V, the weak pull-up current on OV is almost turned on.

CC

Consequently, if the state and pull-up strength of the
important at very low V

, an external pull-up resistor of no more

CC

OV

pin are

than 100 kΩ is advised. By adding an external pull-up resistor,

OV

the pull-up strength on the

pin is greater. Therefore, if it is
connected in a wire-OR’ed configuration, the pull-down strength
of any single device must account for this additional pull-up
strength.

GLITCH IMMUNITY

The ADM2914 is immune to short transients that may occur
on the monitored voltage rails. The device contains internal
filtering circuitry that provides immunity to fast transient
glitches. Figure 9 illustrates glitch immunity performance by
showing the maximum transient duration without causing a
reset pulse. Glitch immunity makes the ADM2914 suitable for
use in noisy environments.

UNDERVOLTAGE LOCKOUT (UVLO)

The ADM2914 has an undervoltage lockout circuit that monitors
the voltage on the V
below 1.9 V (minimum), the circuit is activated. The
is asserted and the
assert. When V

pin. When the voltage on VCC drops

CC

OV

output is cleared and not allowed to

recovers, UV exhibits the same timing

CC

UV

output

characteristics as if an undervoltage condition had occurred
on the inputs.

SHUNT REGULATOR

The ADM2914 is powered via the VCC pin. The VCC pin can
be directly connected to a voltage rail of up to 6 V. In this
mode, the supply current of the device does not exceed
100 µA. An internal shunt regulator allows the ADM2914 to
operate at voltage levels greater than 6 V by simply placing a
dropper resistor in series between the supply rail and the V
pin to limit the input current to less than 10 mA.

Once the supply voltage, V

, has been established, an

IN

appropriate value for the dropper resistor can be calculated.
Begin by determining the maximum supply current
required, I

, by adding the current drawn from the

CCtotal

reference and/or the pull resistors between the outputs and

pin to the maximum specified supply current. The

the V

CC

minimum and maximum shunt regulator voltage specified
in Table 1, V

SHUNT min

and V

SHUNT max

, are also required in the

following calculations.

Calculate the maximum and minimum dropper resistor
values

IN

min

SHUNT

SHUNT

100

min

max

R

=

MAX

R

=

MIN

I

CCtotal

VV

IN

max

Based on these values, choose a real-world resistor value
within this range. Then, given the specified accuracy of this
resistor, calculate the minimum and maximum real resistor
value variation, R

REALmin

and R

REALmax

, respectively.

The maximum device power is calculated as follows:

DeviceMax

=

VP

SHUNTmax

SHUNTmax

IV

CCtotal

⎡
⎢
⎣

−

VV

max

IN

R

REAL

SHUNTmax

min

)

−

Icc

To check that the calculated value of the resistor will be
acceptable, calculate the maximum device temperature rise;

PθTemp

JARISEmax

DeviceMax

Add this value to the ambient operating temperature. If the
resistor value is acceptable, the result will lie within the
specified operating temperature range of the device,

to +85°C.

TOTAL

−40°C

CC

⎤

+

⎥
⎦

Rev. B | Page 12 of 16

ADM2914

http://www.BDTIC.com/ADI

OV LATCH (ADM2914-1)

If an overvoltage condition occurs when the

OV

pulled low, the
the latch. If an
latch is bypassed and the
UV

pin, with an identical timeout period. If the
pulled low while the timeout period is active, the
latches low, as in normal operation.

pin latches low. Pulling

OV

condition clears while

OV

pin behaves in the same way as the

LATCH

LATCH

LATCH

pin is

high clears

is high, the

LATCH

OV

pin is

pin

DISABLE (ADM2914-2)

Pulling the DIS pin high disables both the UV and OV outputs,
and forces both outputs to remain weakly pulled high, regard­less of any faults that are detected at the inputs. If a UVLO

UV

condition is detected, the
however, the timeout function is bypassed. As soon as the
UVLO condition clears, the
normal operation when the pin is left unconnected, DIS has a
weak 2 µA internal pull-down current.

output is asserted and pulls low;

UV

output pulls high. To guarantee

Rev. B | Page 13 of 16

ADM2914

http://www.BDTIC.com/ADI

TYPICAL APPLICATIONS

1

5V

1

3.3V

2.5V

1.8V

1.5MΩ

10.7kΩ

162kΩ

1

1

V

CC

1MΩ

11.7 kΩ

174kΩ

111kΩ

1.82kΩ

27.1kΩ

137kΩ

3.48kΩ

VH1

VL1

VH2

VL2

VH3

VL3

VH4

VL4

ADM2914

SEL

TIMER

SYSTEM

UV

OV

LATCH/DIS

PSU

51.7kΩ

NOTES

1

1.5% SUPPLY TOLERANCE AND 5% INPUT TOLERANCE REQUIREMEN T.

REF

GND

08170-008

Figure 23. Typical Application Diagram for Monitoring 5 V, 3.3 V, 2.5 V, and 1.8 V

1

+12V

PSU

–5V

1.98MΩ

5.62kΩ

83.5kΩ

2

1.96MΩ

27.1kΩ

167kΩ

VH1

VL1

VH2

VL2

VH3

VL3

VH4

VL4

REF

1kΩ

V

CC

ADM2914

LATCH/DIS

GND

SEL

TIMER

SYSTEM

UV

OV

NOTES

1

1.5% SUPPLY TOLERANCE AND 5% INPUT TOLERANCE REQUIREMEN T.

2

3% SUPPLY TOLERANCE AND 15% INPUT TOLERANCE REQUIREMEN T.

Figure 24. Typical Application Diagram for Monitoring +12 V and −5 V

Rev. B | Page 14 of 16

08170-009

ADM2914

2

3

http://www.BDTIC.com/ADI

PSU

NOTES

1

1.5% SUPPLY TOLERANCE AND 10% INPUT TOLERANCE REQUIREMENT.
2% SUPPLY TOLERANCE AND 15% INPUT TOLERANCE REQUIREMEN T.
4% SUPPLY TOLERANCE AND 15% INPUT TOLERANCE REQUIREMEN T.

+48V
+16V
–3.3V
–48V

11.5 MΩ

8.45kΩ

117k Ω

1

1

2

3

V

CC

681kΩ

1.43kΩ

21.3kΩ

1.5MΩ

26.1kΩ

187kΩ

2.87MΩ

5.56kΩ

27.1kΩ

VH1

VL1

VH2

VL2

VH3

VL3

VH4

VL4

REF

ADM2914

GND

SEL

TIMER

OV

LATCH/DIS

UV

SYSTEM

08170-010

Figure 25. Typical Application Diagram for Monitoring +48 V, +16 V, −3.3 V, and −48 V

Rev. B | Page 15 of 16

ADM2914

http://www.BDTIC.com/ADI

OUTLINE DIMENSIONS

0.197 (5.00)

0.193 (4.90)

0.189 (4.80)

16

1

0.065 (1.65)

0.049 (1.25)

0.010 (0.25)

0.004 (0.10)

COPLANARIT Y

0.004 (0.10)

0.025 (0.64)
BSC

CONTROLL ING DIMENSIONS ARE IN INCHES; MIL LIMETERS DIMENSIO NS
(IN PARENTHESES) ARE ROUNDED-O FF INCH EQ UIVALENTS FOR
REFERENCE ON LY AND ARE NOT APPROPRI ATE FOR USE IN DESIGN.

Figure 26. 16-Lead Shrink Small Outline Package [QSOP]

ORDERING GUIDE

1

Model

ADM2914-1ARQZ −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
ADM2914-1ARQZ-RL7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
ADM2914-2ARQZ −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
ADM2914-2ARQZ-RL7 −40°C to +125°C 16-Lead Shrink Small Outline Package [QSOP] RQ-16
EVAL-ADM2914EBZ Evaluation Board

1

Z = RoHS Compliant Part.

Temperature Range Package Description Package Option

9

0.158 (4.01)

0.154 (3.91)

0.150 (3.81)

8

0.069 (1.75)

0.053 (1.35)

SEATING

0.012 (0.30)

0.008 (0.20)

COMPLIANT TO JEDEC STANDARDS MO-137-AB

PLANE

0.244 (6.20)

0.236 (5.99)

0.228 (5.79)

8°
0°

0.010 (0.25)

0.006 (0.15)

(RQ-16)

Dimensions shown in inches and (millimeters)

0.050 (1.27)

0.016 (0.41)

0.020 (0.51)

0.010 (0.25)

0.041 (1.04)
REF

012808-A

©2009-2010 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D08170-0-2/10(B)

Rev. B | Page 16 of 16