Datasheet ADM2486 Datasheet (Analog Devices)

High Speed, Half-Duplex iCoupler

®

FEATURES

Half-duplex, isolated RS-485 transceiver PROFIBUS®-compliant ANSI EIA/TIA 485-A and ISO 8482: 1987(E) compliant 20 Mbps data rate 5 V or 3 V operation (V High common-mode transient immunity: >25 kV/μs Isolated DE status output Receiver open-circuit, fail-safe design Thermal shutdown protection 50 nodes on bus Safety and regulatory approvals

UL recognition—2500 V CSA Component Acceptance Notice #5A VDE Certificate of Conformity

DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01 DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000

V

= 560 V peak

IORM

Operating temperature range: −40°C to +85°C Wide body, 16-lead SOIC package

APPLICATIONS

Isolated RS-485/RS-422 interfaces PROFIBUS networks Industrial field networks Multipoint data transmission systems

GENERAL DESCRIPTION

The ADM2486 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines and complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E).

)

DD1

for 1 minute per UL 1577

rms

Isolated RS-485 Transceiver

ADM2486

FUNCTIONAL BLOCK DIAGRAM

V

DD1

RTS

TxD

LOGIC SIDE

PV

RxD

RE

GND

GALVANIC ISOLATION

1

Figure 1.

The device employs Analog Devices’ iCoupler technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. The logic side of the device is powered with either a 5 V or a 3 V supply, and the bus side uses an isolated 5 V supply.

The ADM2486 driver has an active-high enable feature. The driver differential outputs and the receiver differential inputs are connected internally to form a differential input/output port that imposes minimal loading on the bus when the driver is

or V

disabled or when V

DD1

= 0 V. Also provided is an active-

DD2

high receiver disable feature that causes the receive output to enter a high impedance state.

The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention might cause excessive power dissipation. The part is fully specified over the industrial temperature range and is available in a 16-lead, wide body SOIC package.

V

DD2

ADM2486

GND

2

DE

A

B

BUS SIDE

04604-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADM2486

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

ADM2486 Characteristics ............................................................... 7

Package Characteristics ............................................................... 7

Regulatory Information............................................................... 7

Insulation and Safety-Related Specifications............................ 7

VDE 0884 Insulation Characteristics ........................................8

Pin Configuration and Function Descriptions............................. 9

Test Circuits..................................................................................... 10

Switching Characteristics ..............................................................11

Typical Performance Characteristics ........................................... 12

REVISION HISTORY

Circuit Description......................................................................... 14

Electrical Isolation...................................................................... 14

Truth Tables................................................................................. 14

Power-Up/Power-Down Thresholds ....................................... 14

Thermal Shutdown .................................................................... 15

Receiver Fail-Safe Inputs ........................................................... 15

Magnetic Field Immunity.......................................................... 15

Applications Information.............................................................. 16

Power_Valid Input ..................................................................... 16

Isolated Power Supply Circuit .................................................. 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

3/05—Rev. B to Rev. C

Change to Package Characteristics................................................. 7

Changes to Figure 12, Figure 14, and Figure 15 ......................... 11

Change to Power_Valid Input Section......................................... 16

1/05—Rev. A to Rev. B

Added PROFIBUS logo ................................................................... 1

11/04—Rev. 0 to Rev. A

Changes to Figure 1.......................................................................... 1

Changes to Figure 6........................................................................ 10

Added Figure 22 through Figure 25............................................. 13

Updated Outline Dimensions....................................................... 18

Changes to Ordering Guide.......................................................... 18

Rev. C | Page 2 of 20

ADM2486

SPECIFICATIONS

2.7 V ≤ V

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Differential Outputs

Bus Enable Output

Logic Inputs

RECEIVER

Differential Inputs

RxD Logic Output

≤ 5.5 V, 4.75 V ≤ V

DD1

≤ 5.25 V, TA = T

DD2

MIN

to T

, unless otherwise noted.

MAX

Differential Output Voltage, VOD 5 V R = ∞, see Figure 3

2.1 5 V R = 50 Ω (RS-422), see Figure 3

2.1 5 V R = 27 Ω (RS-485), see Figure 3

2.1 5 V

= −7 V to 12 V, V

V

TST

DD1

≥ 4.7,

see Figure 4 ∆ |VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 3 Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 3 ∆ |VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 3 Output Short-Circuit Current, V Output Short-Circuit Current, V

Output High Voltage V V V Output Low Voltage 0.1 V I

0.1 0.3 V I

0.2 0.4 V I

Input High Voltage 0.7 V Input Low Voltage 0.25 V CMOS Logic Input Current (TxD, RTS, RE, PV)

= High 60 200 mA −7 V ≤ V

OUT

= Low 60 200 mA −7 V ≤ V

OUT

− 0.1 V I

DD2

− 0.3 V

DD2

− 0.4 V

DD2

V

DD1

− 0.1 V I

DD2

− 0.2 V I

DD2

V

DD1

−10 0.01 10 µA

ODE

TxD, RTS, RE

TxD, RTS, RE, PV = V

≤ +12 V

OUT

≤ +12 V

OUT

= 20 µA = 1.6 mA = 4 mA = −20 µA = −1.6 mA = −4 mA

, PV , PV

DD1

or 0 V

Differential Input Threshold Voltage, VTH −200 200 mV −7 V ≤ VCM ≤ +12V Input Hysteresis 70 mV −7 V ≤ VCM ≤ +12V Input Resistance (A, B) 20 30 kΩ −7 V ≤ VCM ≤ +12V Input Current (A, B)

Output High Voltage V V Output Low Voltage 0.1 V I

0.2 0.4 V I Output Short-Circuit Current 7 85 mA V Three-State Output Leakage Current ±1 µA 0.4 V ≤ V

0.6 mA VIN = +12 V

−0.35 mA VIN = −7 V

− 0.1 V I

DD1

− 0.4 V

DD1

− 0.2 V I

DD1

= 20 µA, VA − VB = 0.2 V

OUT

= 4 mA, VA − VB = 0.2 V

OUT

= −20 µA, VA − VB = −0.2 V

OUT

= −4 mA, VA − VB = −0.2 V

OUT

= GND or VCC

OUT

≤ 2.4 V

OUT

Rev. C | Page 3 of 20

ADM2486

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY CURRENT

Logic Side 1.3 mA RTS = 0 V, V

2.9 mA 2 Mbps, V

10.2 mA 20 Mbps, V

0.8 mA RTS = 0 V, V

1.1 mA 2 Mbps, V

4.3 mA 20 Mbps, V Bus Side 3.0 mA RTS = 0 V

53.4 mA 2 Mbps, RTS = V

86.7 mA 20 Mbps, RTS = V

COMMON-MODE TRANSIENT IMMUNITY1 25 kV/µs

HIGH FREQUENCY, COMMON-MODE NOISE IMMUNITY

1

Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation.

V

is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common-mode is slewed. The

CM

common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

DD1

= 1 kV,

V

CM

= 5.5 V

= 5.5 V, see Figure 5

= 3 V

= 3 V, see Figure 5

, see Figure 5

DD1

, see Figure 5

DD1

transient magnitude = 800 V

100 mV

= +5 V, −2 V < V

V

HF

1 MHz < f

TEST

< 7 V,

TEST2

< 50 MHz, see Figure 6

Rev. C | Page 4 of 20

ADM2486

TIMING SPECIFICATIONS

2.7 V ≤ V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Maximum Data Rate 20 Mbps Propagation Delay, t RTS-to-DE Propagation Delay 20 35 55 ns See Figure 8 Pulse Width Distortion, t

Switching Skew, t

Rise/Fall Time, tR, tF 5 15 ns

Enable Time 43 53 ns See Figure 9 and Figure 14 Disable Time 43 55 ns See Figure 9 and Figure 14 Enable Skew, |t Disable Skew, |t

RECEIVER

Propagation Delay, t Differential Skew, t Enable Time 3 13 ns RL = 1 kΩ, CL = 15 pF, see Figure 11 and Figure 15 Disable Time 3 13 ns RL = 1 kΩ, CL = 15 pF, see Figure 11 and Figure 15

POWER_VALID INPUT

Enable Time 1 2 µs Disable Time 3 5 µs

≤ 5.5 V, 4.75 V ≤ V

DD1

PLH

2 5 ns

SKEW

− t

AZH

BZL

− t

AHZ

BLZ

PLH

SKEW

≤ 5.25 V, TA = T

DD2

, t

25 45 55 ns R

PHL

5 ns

PWD

MIN

to T

, unless otherwise noted.

MAX

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 7

LDIFF

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and

R

LDIFF

Figure 12

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and

R

LDIFF

Figure 12

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 7 and

R

LDIFF

Figure 12

|, |t

− t

AZL

|, |t

, t

PHL

| 1 3 ns See Figure 9 and Figure 14

BZH

− t

ALZ

| 2 5 ns See Figure 9 and Figure 14

BHZ

25 45 55 ns CL = 15 pF, see Figure 10 and Figure 13

5 ns CL = 15 pF, see Figure 10 and Figure 13

Rev. C | Page 5 of 20

ADM2486

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. All voltages are relative to their respective ground.

Table 3.

Parameter Rating V

−0.5 V to +7 V

DD1

V

−0.5 V to +6 V

DD2

Digital Input Voltage (RTS, RE, TxD) Digital Output Voltage

RxD −0.5 V to V

DE −0.5 V to V Driver Output/Receiver Input Voltage −9 V to +14 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −55°C to +150°C Average Output Current per Pin −35 mA to +35 mA θJA Thermal Impedance 73°C/W Lead Temperature

Soldering (10 sec) 260°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−0.5 V to V

DD1

DD2

+ 0.5 V

+ 0.5 V + 0.5 V

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. C | Page 6 of 20

ADM2486

ADM2486 CHARACTERISTICS

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output)1 R Capacitance (Input-Output)

1

Input Capacitance2 C Input IC Junction-to-Case Thermal Resistance θ Output IC Junction-to-Case Thermal Resistance θ

1

Device considered a 2-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.

2

Input capacitance is from any input data pin to ground

REGULATORY INFORMATION

The ADM2486 has been approved by the following organizations:

Table 5.

Organization Approval Type Notes

UL

CSA Approved under CSA Component Acceptance Notice #5A. File 205078. VDE Certified according to DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01

Recognized under 1577 component recognition program. File E214100

Complies with DIN EN 60747-5-2 (VDE 0884 Part 2): 2003-01, DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000 File 2471900-4880-0001

1012 Ω

I-O

C

3 pF f = 1 MHz

I-O

4 pF

I

33 °C/W

JCI

28 °C/W

JCO

Thermocouple located at center of package underside

In accordance with UL1577, each ADM2486 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).

In accordance with VDE 0884, each ADM2486 is proof tested by applying an insulation test voltage ≥1050 V

PEAK

(partial discharge detection limit = 5 pC).

for 1 sec

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration. Minimum External Air Gap (Clearance) L(I01) 7.45 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation. Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1. Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1).

Measured from input terminals to output terminals, shortest distance through air.

Measured from input terminals to output terminals, shortest distance along body.

Rev. C | Page 7 of 20

ADM2486

VDE 0884 INSULATION CHARACTERISTICS

This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits.

An asterisk (*) on the physical package denotes VDE 0884 approval for 560 V peak working voltage.

Table 7.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110 for Rated Mains Voltage

≤150 V rms I to IV

≤300 V rms I to III

≤400 V rms I to II Climatic Classification 40/85/21 Pollution Degree (DIN VDE 0110, Table 1) 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage, Method b1 VPR 1050 V

V

× 1.875 = VPR, 100% Production Tested, tm = 1 sec, Partial Discharge < 5 pC

IORM

Input-to-Output Test Voltage, Method a

(After Environmental Tests, Subgroup 1)

V

× 1.6 = VPR, tm = 60 sec, Partial Discharge < 5 pC 896 V

IORM

(After Input and/or Safety Test, Subgroup 2/3)

V

× 1.2 = VPR, tm = 60 sec, Partial Discharge < 5 pC VPR 672 V

IORM

Highest Allowable Overvoltage

(Transient Overvoltage, tTR = 10 sec) VTR 4000 V

Safety-Limiting Values (Mximum Value Allowed in the Event of a Failure. See

Figure 21.)

Case Temperature TS 150 °C

Input Current IS,

Output Current IS, Insulation Resistance at Ts, VIO = 500 V RS >109 Ω

560 V

IORM

PEAK

265 mA

INPUT

335 mA

OUTPUT

Rev. C | Page 8 of 20

ADM2486

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

DD1

1

GND

2

1

ADM2486

3

RxD

RTS TxD

GND

NC = NO CONNECT

1

PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND1. PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND2.

RE

PV

1

TOP VIEW

(Not to Scale)

4 5 6 4

7 8

16

V

DD2

1

15

GND

2

14

NC

13

B

12

A

11

NC

5

10

DE

1

9

GND

2

04604-003

Figure 2. Pin Configuration

Table 8.

Pin No. Mnemonic Function

1 V

Power Supply (Logic Side).

DD1

2, 8 GND1 Ground (Logic Side). 3 R×D

Receiver Output Data. This output is high when (A – B) > 200 mV, and low when (A – B) < –200 mV. The output is three-stated when the receiver is disabled, that is, when RE is driven high.

4

RE

Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and driving

it high disables the receiver. 5 RTS Request to Send Input. Driving this input high enables the driver, and driving it low disables the driver. 6 TxD Transmit Data Input. Data to be transmitted by the driver is applied to this input. 7 PV Power_Valid. Used during power-up and power-down. See the Applications Information section. 9, 15 GND2 Ground (Bus Side). 10 DE

Driver Enable Status Output. This output signals the driver enable or disable status to other devices on

the bus. DE is high when the driver is enabled and low when the driver is disabled. 11, 14 NC No Connect. 12 A

Noninverting Driver Output/Receiver Input. When the driver is disabled, or when V

DD1

or V

is powered

DD2

down, Pin A is put into a high impedance state to avoid overloading the bus. 13 B

Inverting Driver Output/Receiver Input. When the driver is disabled, or when V

DD1

or V

is powered

DD2

down, Pin B is put into a high impedance state to avoid overloading the bus. 16 V

Power Supply (Bus Side).

DD2

Rev. C | Page 9 of 20

ADM2486

V

TEST CIRCUITS

V

OD

Figure 3. Driver Voltage Measurement

375Ω

V

60Ω

OD3

375Ω

Figure 4. Driver Voltage Measurement

RTS

TxD

RxD

GALVANIC ISOLATION

RE

V

GND

DD1

1

V

DD2

Figure 5. Supply-Current Measurement Test Circuit

R

GND

V

TEST

2

V

OC

DE

150Ω

A

B

V

DD2

GND

04604-005

04604-006

195Ω

110Ω

195Ω

2

04604-004

RTS

TxD

RxD

RE

TxD

RTS

A

R

B

Figure 7. Driver Propagation Delay

GALVANIC ISOLATION

GND

V

DD1

1

V

DD2

Figure 8. RTS-to-DE Propagation Delay

A

S1

B

Figure 9. Driver Enable/Disable

LDIFF

50pF

GND

2

V

C

L1

C

L2

110Ω

OUT

DE

04604-007

150Ω

50pF

A

B

04604-008

V

CC

S2

04604-009

A

V

RTS

TxD

100nF

GND

B

A

2

GND

CM(HF)

2.2kΩ

2

RxD

RECEIVE

ENABLE

GALVANIC ISOLATION

V

DD1

100nF

GND

V

1

DD2

Figure 6. High Frequency Common-Mode Noise Test Circuit

DE

V

GND

DD2

195Ω

110Ω

195Ω

2

470nF

50Ω

V

110nF

TEST2

22kΩ

RE

B

F

,

TEST

V

HF

Figure 10. Receiver Propagation Delay

+1.5V

S1

–1.5V

04604-010

RE

RE IN

OUT

C

L

04604-012

R

L

C

V

L

OUT

V

CC

S2

04604-013

Figure 11. Receiver Enable/Disable

Rev. C | Page 10 of 20

ADM2486

SWITCHING CHARACTERISTICS

V

DD1

0V

B

A

V

OH

A, B

V

OL

A–B

0.5V

DD1

t

PALH

t

PBLH

1/2VO

VO

t

SKEW

t

= |t

PWD

90% POINT

10% POINT

t

R

Figure 12. Driver Propagation Delay, Rise/Fall Timing

0V 0V

PALH

0.5V

DD1

t

– t

|, |t

PBLH

– t

PAHL

PBHL

|

90% POINT

10% POINT

t

F

t

PAHL

SKEW

04604-011

0.7V

DD1

RTS

A, B

RE

0.5V

t

DD1

ZL

2.3V

ZH

2.3V

t

LZ

t

HZ

0.5V

DD1

V

VOH– 0.5V

Figure 14. Driver Enable/Disable Timing

0.5V

t

ZL

DD1

0.5V

t

LZ

OH

DD1

+ 0.5V

0.3V

0.7V

0.3V

DD1

V

DD1

OL

OH

04604-021

0V

1.5V O/P LOW

t

ZH

O/P HIGH

1.5V

t

HZ

V

OL

VOH– 0.5V

Figure 15. Receiver Enable/Disable Timing

+ 0.5V

V

OL

V

OH

04604-020

RxD

t

PLH

1.5V 1.5V

t

SKEW

= |t

PLH

– t

PHL

Figure 13. Receiver Propagation Delay

t

PHL

V

OH

|

V

OL

04604-019

RxD

0V

Rev. C | Page 11 of 20

ADM2486

TYPICAL PERFORMANCE CHARACTERISTICS

1.4

1.2

1.0

0.8

0.6

0.4

SUPPLY CURRENT (mA)

0.2

0

–40

I

_RCVR_ENABLE @ 5.5V

DD1

I

_DE_ENABLE @ 5.5V

DD2

25

TEMPERATURE (°C)

Figure 16. Unloaded Supply Current vs. Temperature

50

45

40

35

30

25

TIME (ns)

20

15

10

5

0

RECEIVER

–40

t

PLH

t

PHL

TEMPERATURE (°C)

25

Figure 17. Driver Propagation Delay vs. Temperature

1

2

4

85

04604-029

CH1 2.00V CH2 2.00V CH3 2.00V CH4 2.00V

M20.0ns A CH2 3.12V

T 6.00000ns

04604-025

Figure 19. Driver/Receiver Propagation Delay, Low to High

= 54 Ω, CL1 = CL2 = 100 pF)

(R

LDiff

1

3

4

85

04604-026

CH1 5.00V CH2 2.00V CH3 2.00V CH4 2.00V

M20.0ns A CH1 2.60V

T –444.400ns

04604-028

Figure 20. Driver/Receiver Propagation Delay, High to Low

= 54 Ω, CL1 = CL2 = 100 pF)

(R

LDiff

50

DRIVER

t

DRIVER

–40

BHL

DRIVER

t

ALH

DRIVER

t

BLH

TEMPERATURE (°C)

t

AHL

25

45

40

35

30

25

TIME (ns)

20

15

10

5

0

Figure 18. Receiver Propagation Delay vs. Temperature

350

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

85

04604-027

0

SIDE 2

SIDE 1

50 100 150 200

CASE TEMPERATURE (°C)

04604-018

Figure 21. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per VDE 0884

Rev. C | Page 12 of 20

ADM2486

0

4.78

–5

–10

–15

–20

OUTPUT CURRENT (mA)

–25

–30

3.04

3.30

3.56 3.82

4.07 4.31 4.55

OUTPUT VOLTAGE (V)

Figure 22. Output Current vs. Receiver Output High Voltage

35

30

25

20

15

10

OUTPUT CURRENT (mA)

5

4.79

5.00

04604-031

4.76

4.74

4.72

4.70

OUTPUT VOLTAGE (V)

4.68

4.66 –40

–25

–10 5

20 35 50

TEMPERATURE (°C)

65

80

Figure 24. Receiver Output High Voltage vs. Temperature I = −4 mA

0.32

0.30

0.28

0.26

0.24

OUTPUT VOLTAGE (V)

0.22

04604-033

1.67

0.23

0

0.46 0.69

0.93 1.17 1.42

OUTPUT VOLTAGE (V)

1.9302.20

Figure 23. Output Current vs. Receiver Output Low Voltage

04604-032

0.20 –40

–25

–10 5

20 35 50

TEMPERATURE (°C)

65

80

Figure 25. Receiver Output Low Voltage vs. Temperature I = –4 mA

04604-034

Rev. C | Page 13 of 20

ADM2486

CIRCUIT DESCRIPTION

ELECTRICAL ISOLATION

In the ADM2486, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 26). Driver input and request-to-send signals, applied to the TxD and RTS pins, respectively, and referenced to logic ground (GND appear at the transceiver section referenced to isolated ground

). Similarly, the receiver output, referenced to isolated

(GND

2

ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground.

iCoupler Technology

The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted.

TxD

RTS

RxD

RE

DIGITAL ISOLATION

Figure 26. ADM2486 Digital Isolation and Transceiver Sections

TRUTH TABLES

The truth tables in this section use these abbreviations:

Letter Description

H High level I Indeterminate L Low level X Irrelevant Z High impedance (off) NC Disconnected

), are coupled across an isolation barrier to

1

V

DD1

ENCODE

DECODE

GND

1

ISOLATION

BARRIER

DECODE

ENCODE

V

GND

DD2

2

D

R

TRANSCEIVER

A B

DE

Table 9. Transmitting

Supply Status Inputs Output V

V

DD1

RTS TxD A B DE

DD2

On On H H H L H On On H L L H H On On L X Z Z L On Off X X Z Z L Off On X X Z Z L Off Off X X Z Z L

Table 10. Receiving

Supply Status Inputs Output V

V

DD1

A − B (V)

DD2

RE

RxD

On On >0.2 L or NC H On On <−0.2 L or NC L On On −0.2 < A − B < 0.2 L or NC I On On Inputs open L or NC H On On X H Z On Off X L or NC H Off On X L or NC H Off Off X L or NC L

POWER-UP/POWER-DOWN THRESHOLDS

The power-up/power-down characteristics of the ADM2486 are in accordance with the supply thresholds shown in Table 11. Upon power-up, the ADM2486 output signals (A, B, RxD, and DE) reach their correct state once both supplies have exceeded their thresholds. Upon power-down, the ADM2486 output signals retain their correct state until at least one of the supplies drops below its power-down threshold. When the V

04604-022

down threshold is crossed, the ADM2486 output signals reach their unpowered states within 4 µs.

Table 11. Power-Up/Power-Down Thresholds

Supply Transition Threshold (V)

V

Power-up 2.0

DD1

V

Power-down 1.0

DD1

V

Power-up 3.3

DD2

V

Power-down 2.4

DD2

power-

DD1

Rev. C | Page 14 of 20

ADM2486

β

THERMAL SHUTDOWN

The ADM2486 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150°C is reached. As the device cools, the drivers are re-enabled at a temperature of 140°C.

RECEIVER FAIL-SAFE INPUTS

The receiver input includes a fail-safe feature that guarantees a logic high RxD output when the A and B inputs are floating or open-circuited.

MAGNETIC FIELD IMMUNITY

Because iCouplers use a coreless technology, no magnetic components are present, and the problem of magnetic saturation of the core material does not exist. Therefore, iCouplers have essentially infinite dc field immunity. The analysis below defines the conditions under which this may occur. The ADM2486’s 3 V operating condition is examined because it represents the most susceptible mode of operation.

The limitation on the iCoupler’s ac magnetic field immunity is set by the condition in which the induced error voltage in the receiving coil (the bottom coil in this case) is made sufficiently large, either to falsely set or reset the decoder. The voltage induced across the bottom coil is given by

β−

d

⎞

⎛

=

V

⎜

dt

⎝

where, if the pulses at the transformer output are greater than

1.0 V in amplitude: = magnetic flux density (gauss)

N = number of turns in receiving coil

= radius of nth turn in receiving coil (cm)

r

n

The decoder has a sensing threshold of about 0.5 V; therefore, there is a 0.5 V margin in which induced voltages can be tolerated.

Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the

0.5 V margin at the decoder, a maximum allowable magnetic

field is calculated, as shown in Figure 27.

2

; Nn ,...,2,1=

π

r

⎟

∑

n

⎠

100.000

10.000

1.000

0.100

FLUX DENSITY (kGAUSS)

0.010

MAXIMUM ALLOWABLE MAGNETIC

0.001 1k 10k 100k 100M1M 10M

Figure 27. Maximum Allowable External Magnetic Flux Density

MAGNETIC FIELD FREQUENCY (Hz)

04604-016

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold of the decoder.

Figure 28 shows the magnetic flux density values in terms of more familiar quantities such as maximum allowable current flow at given distances away from the ADM2486 transformers.

1000.00

DISTANCE = 1m

100.00

DISTANCE = 5mm

10.00

1.00

0.10

MAXIMUM ALLOWABLE CURRENT (kA)

0.01

DISTANCE = 100mm

1k 10k 100k 100M1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 28. Maximum Allowable Current for

Various Current-to-ADM2486 Spacings

04604-017

At combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

Rev. C | Page 15 of 20

ADM2486

APPLICATIONS INFORMATION

POWER_VALID INPUT

To avoid chatter on the A and B outputs caused by slow powerup and power-down transients on V features a power_valid (PV) digital input. This pin should be driven low until V

exceeds 2.0 V. When V

DD1

2.0 V, this pin should be driven high. Conversely, upon powerdown, PV should be driven low before V

If the PV pin is driven with an open-drain output, the recommended value for the pull-up resistor is a 10 kΩ resistor, bypassed with a 100 pF capacitor to GND

The power_valid input can be driven, for example, by the output of a system reset circuit such as the ADM809Z, which has a threshold voltage of 2.32 V.

V

DD1

(>100 µs/V), the device

DD1

is greater than

DD1

reaches 2.0 V.

DD1

(see Figure 30).

1

V

DD1

V

DD1

10kΩ

ADM2486

PV

V

DD1

RESET

ADM809Z

2.32V

2.0V

t

RESET

100pF

POR

Figure 30. Driving PV with an Open-Drain Output

V

DD1

GND

1

2.32V

2.0V

04604-030

V

DD1

RESET

ADM809Z

2.32V

2.0V

t

RESET

POR

ADM2486

PV

Figure 29. Driving PV with ADM809Z

GND

1

2.32V

2.0V

04604-023

Rev. C | Page 16 of 20

ADM2486

ISOLATED POWER SUPPLY CIRCUIT

The ADM2486 requires isolated power capable of 5 V at 100 mA to be supplied between the V

and GND2 pins. If no suitable

DD2

integrated power supply is available, a discrete circuit, such as the one in Figure 31, can be used. A center-tapped transformer provides electrical isolation. The primary winding is excited with a pair of square waveforms that are 180° out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP667 linear voltage regulator provides a regulated power supply to the ADM2486’s bus-side circuitry.

V

CC

1nF

3.9kΩ

V

CC

100nF

74HC14A

PR

D

74HC74A

CLK

100nF

CLR

Q

BS107A

To create the pair of square waves, a D-type flip-flop with complementary Q/

outputs is used. The flip-flop can be

Q

connected so that output Q follows the clock input signal. If no local clock signal is available, a simple digital oscillator can be implemented with a hex-inverting Schmitt trigger and a resistor and capacitor. In this case, values of 3.9 kΩ and 1 nF generate a 364 kHz square wave. A pair of discrete NMOS transistors, switched by the Q/

flip-flop outputs, conduct current through

Q the center tap of the primary transformer, winding in an alternating fashion.

ISOLATION

BARRIER

SD103C

V

CC

78253

SD103C

IN

22µF

ADP667

SET GND SHDN

OUT

5V

10µF

Figure 31. Isolated Power Supply Circuit

V

CC

V

DD1

ADM2486

GND

1

V

GND

DD2

2

04604-024

Rev. C | Page 17 of 20

ADM2486

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

1.27 (0.0500) BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013AA

9

7.60 (0.2992)

7.40 (0.2913)

8

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.75 (0.0295)

0.25 (0.0098)

8° 0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

Figure 32. 16-Lead Standard Small Outline Package [SOIC]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Data Rate (Mbps) Temperature Range Package Description Quantity Package Option

ADM2486BRW 20 −40°C to +85°C 16-Lead, Wide Body SOIC 47 RW-16 ADM2486BRW-REEL 20 −40°C to +85°C 16-Lead, Wide Body SOIC 1,000 RW-16 ADM2486BRWZ1 20 −40°C to +85°C 16-Lead, Wide Body SOIC 47 RW-16 ADM2486BRWZ-REEL1 20 −40°C to +85°C 16-Lead, Wide Body SOIC 1,000 RW-16

1

Z = Pb-free part.

Rev. C | Page 18 of 20

ADM2486

NOTES

Rev. C | Page 19 of 20

ADM2486

NOTES

D04604–0–3/05(C)

Rev. C | Page 20 of 20

Datasheet ADM2486 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

TIMING SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

ADM2486 CHARACTERISTICS

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

VDE 0884 INSULATION CHARACTERISTICS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TEST CIRCUITS

SWITCHING CHARACTERISTICS

TYPICAL PERFORMANCE CHARACTERISTICS

CIRCUIT DESCRIPTION

ELECTRICAL ISOLATION

iCoupler Technology

TRUTH TABLES

POWER-UP/POWER-DOWN THRESHOLDS

THERMAL SHUTDOWN

RECEIVER FAIL-SAFE INPUTS

MAGNETIC FIELD IMMUNITY

APPLICATIONS INFORMATION

POWER_VALID INPUT

ISOLATED POWER SUPPLY CIRCUIT

OUTLINE DIMENSIONS

ORDERING GUIDE