Datasheet ADM2485 Datasheet (ANALOG DEVICES)

High Speed, Isolated RS-485 Transceiver

V

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FEATURES

Half-duplex, isolated RS-485 transceiver Integrated oscillator driver for external transformer PROFIBUS® compliant Complies with ANSI/TIA/EIA RS-485-A-98 and

ISO 8482:198 Data rate: 16 Mbps 5 V or 3.3 V operation (V 50 nodes on bus High common-mode transient immunity: >25 kV/μs Isolated DE OUT status output Thermal shutdown protection Safety and regulatory approvals

UL recognition: 2500 V rms for 1 minute per UL 1577

VDE Certificate of Conformity

DIN V VDE V 0884-10 (VDE V 0884-10):2006-12

Reinforced insulation, V Operating temperature range: –40°C to +85°C Wide-body, 16-lead SOIC package

7(E)

DD1

)

= 560 V peak

IORM

with Integrated Transformer Driver

ADM2485

FUNCTIONAL BLOCK DIAGRAM

D1 D2

RTS

TxD

RxD

RE

V

DD1

OSC

GALVANIC IS OLATIO N

GND

1

Figure 1.

DD2

ADM2485

GND

2

DE OUT

A

B

06021-001

APPLICATIONS

Isolated RS-485/RS-422 interfaces PROFIBUS networks Industrial field networks Multipoint data transmission systems

GENERAL DESCRIPTION

The ADM2485 differential bus transceiver is an integrated, galvanically isolated component designed for bidirectional data communication on multipoint bus transmission lines. It is designed for balanced transmission lines and complies with ANSI/TIA/EIA RS-485-A-98 and ISO 8482:1987(E).

The device employs Analog Devices, Inc., iC to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package. An on-chip oscillator outputs a pair of square waveforms that drive an external transformer to provide isolated power with an external transformer. The logic side of the device can be powered with either a 5 V or a 3.3 V supply, and the bus side is powered with an isolated 5 V supply.

oupler® technology

The ADM2485 driver has an active high enable. The driver dif

ferential outputs and the receiver differential inputs are connected internally to form a differential input/output port that imposes minimal loading on the bus when the driver is disabled or when V

DD1

or V

= 0 V. Also provided is an active

DD2

high receiver disable that causes the receive output to enter a high impedance state.

The device has current-limiting and thermal shutdown features

o protect against output short circuits and situations where bus

t contention might cause excessive power dissipation. The part is fully specified over the industrial temperature range and is available in a 16-lead, wide-body SOIC package.

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

12/07—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Changes to Features Section............................................................ 1

Changes to Table 4............................................................................ 6

Changes to VDE 0884-2 Insulation Characteristics Section ...... 7

Changes to PCB Section and Figure 34 ....................................... 16

Updated Outline Dimensions....................................................... 17

1/07—Revision 0: Initial Version

Rev. A | Page 2 of 20

ADM2485

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SPECIFICATIONS

2.7 V ≤ V

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Differential Outputs

Bus Enable Output

Logic Inputs

RECEIVER

Differential Inputs

RxD Logic Output

TRANSFORMER DRIVER

Oscillator Frequency 400 500 600 kHz V 230 330 430 kHz V Switch-On Resistance 0.5 1.5 Ω Start-Up Voltage 2.2 2.5 V

≤ 5.5 V, 4.75 V ≤ V

DD1

Differential Output Voltage, V

≤ 5.25 V, TA = T

DD2

OD

MIN

to T

, unless otherwise noted.

MAX

5 V R = ∞, see Figure 21

2.1 5 V R = 50 Ω (RS-422), see Figure 21

2.1 5 V R = 27 Ω (RS-485), see Figure 21

2.1 5 V V

= –7 V to +12 V, V

TST

≥ 4.75 V, see Figure 22

DD1

Δ|VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 21 Common-Mode Output Voltage, V

OC

3 V R = 27 Ω or 50 Ω, see Figure 21 Δ|VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 21 Output Short-Circuit Current, V Output Short-Circuit Current, V

Output High Voltage V V V Output Low Voltage 0.1 V I

0.1 0.3 V I

0.2 0.4 V I

Input High Voltage 0.7 V Input Low Voltage 0.25 V CMOS Logic Input Current (TxD, RTS, RE)

Differential Input Threshold Voltage, V

= High 60 200 mA −7 V ≤ V

OUT

= Low 60 200 mA −7 V ≤ V

OUT

− 0.1 V I

DD2

− 0.3 V

DD2

− 0.4 V

DD2

DD1

− 0.1 V I

DD2

− 0.2 V I

DD2

V

DD1

−10 +0.01 +10 μA

TH

−200 +200 mV −7 V ≤ VCM ≤ +12V

ODE

TxD, RTS, RE TxD, RTS, RE TxD, RTS, RE = V

≤ +12 V

OUT

≤ +12 V

OUT

= 20 μA = 1.6 mA = 4 mA = −20 μA = −1.6 mA = −4 mA

DD1

or 0 V

Input Hysteresis 70 mV −7 V ≤ VCM ≤ +12V Input Resistance (A, B) 20 30 kΩ −7 V ≤ VCM ≤ +12V Input Current (A, B) 0.6 mA VIN = +12 V

−0.35 mA VIN = −7 V

Output High Voltage V V Output Low Voltage 0.1 V I

0.2 0.4 V I Output Short-Circuit Current 7 85 mA V Tristate Output Leakage Current ±1 μA 0.4 V ≤ V

− 0.1 V I

DD1

− 0.4 V

DD1

− 0.2 V I

DD1

= +20 μA, VA − VB = +0.2 V

OUT

= +1.5 mA, VA − VB = +0.2 V

OUT

= −20 μA, VA − VB = −0.2 V

OUT

= −4 mA, VA − VB = −0.2 V

OUT

= GND or V

OUT

DD1

= 5.5 V = 3.3 V

≤ 2.4 V

OUT

CC

Rev. A | Page 3 of 20

ADM2485

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Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY CURRENT

Logic Side 2.5 mA RTS = 0 V, V

2.3 mA 2.5 Mbps, V

5.0 6.5 mA 16 Mbps, V

1.26 mA RTS = 0 V, V

1.5 mA 2.5 Mbps, V

2.9 mA 16 Mbps, V Bus Side 1.7 2.5 mA RTS = 0 V

49.0 mA

2.5 Mbps, RTS = V load conditions

55.0 75.0 mA

16 Mbps, RTS = V

load conditions COMMON-MODE TRANSIENT IMMUNITY HIGH FREQUENCY COMMON-MODE

NOISE IMMUNITY

1

CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential

difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

1

25 kV/μs Transient magnitude = 800 V, VCM = 1 kV 100 mV

VHF = +5 V, −2 V < V

1 MHz < f

= 5.5 V

DD1

= 5.5 V, see Figure 23

DD1

= 5.5 V, see Figure 23

DD1

= 3.3 V

DD1

= 3.3 V, see Figure 23

DD1

= 3.3 V, see Figure 23

DD1

, see Figure 23 for

DD1

, see Figure 23 for

DD1

< +7 V,

TEST2

< 50 MHz, see Figure 24

TEST

Rev. A | Page 4 of 20

ADM2485

+

–

A

V

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TIMING SPECIFICATIONS

2.7 V ≤ V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

Maximum Data Rate 16 Mbps Propagation Delay Input-to-Output

RTS-to-DE OUT Propagation Delay 20 35 55 ns See Figure 26 Driver Output-to-Output, t Rise/Fall Time, tR, tF 5 15 ns R

Enable Time 43 53 ns See Figure 4 and Figure 27 Disable Time 43 55 ns See Figure 4 and Figure 27 Enable Skew, |t Disable Skew, |t

RECEIVER

Propagation Delay, t Differential Skew, t Enable Time 3 13 ns RL = 1 kΩ, CL = 15 pF, see Figure 5 and Figure 29 Disable Time 3 13 ns RL = 1 kΩ, CL = 15 pF, see Figure 5 and Figure 29

Timing Diagrams

3V

0V

B

A

V

OUT

0V

V

OUT

– B

≤ 5.5 V, 4.75 V ≤ V

DD1

t

, t

PLH

PHL

1/2V

OUT

V

OUT

90% POINT

10% POINT

t

AZH

AHZ

1.5V

PLH

− t

|, |t

BZL

− t

|, |t

BLZ

, t

PLH

PHL

SKEW

t

R

t

SKEW

AZL

ALZ

− t

= |t

DD2

BZH

PLH

≤ 5.25 V, TA = T

| 1 3 ns See Figure 4 and Figure 27

| 2 5 ns See Figure 4 and Figure 27

BHZ

– t

|

PHL

Figure 2. Driver Propagation Delay, Rise/Fall Timing

0V 0V

to T

MIN

25 45 55 ns R

2 5 ns R

, unless otherwise noted.

MAX

LDIFF

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 25

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 2 and Figure 25

25 45 55 ns CL = 15 pF, see Figure 3 and Figure 28 5 ns CL = 15 pF, see Figure 3 and Figure 28

1.5V

t

PHL

90% POINT

t

F

10% POINT

06021-012

RTS

– B

RE

0.5V

DD1

t

ZL

2.3V

t

ZH

2.3V

Figure 4. Driver Enable/Disable Timing

0.5V

DD1

t

ZL

t

LZ

t

HZ

t

0.5V

LZ

DD1

VOH + 0.5V

VOH – 0.5V

DD1

0.7V

0.3V

0.7

0.3V

DD1

V

OL

V

OH

0V

06021-014

RxD

t

PLH

1.5V 1.5V

t

SKEW

= |t

PLH

– t

PHL

t

PHL

V

OH

|

V

OL

06021-013

Figure 3. Receiver Propagation Delay

Rev. A | Page 5 of 20

RxD

1.5V OUTPUT LOW

t

ZH

0V

OUTPUT HIGH

1.5V

t

HZ

V

+ 0.5V

OH

VOH – 0.5V

V

OL

V

OH

06021-015

Figure 5. Receiver Enable/Disable Timing

ADM2485

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PACKAGE CHARACTERISTICS

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-to-Output) Capacitance (Input-to-Output) Input Capacitance

2

Input IC Junction-to-Case Thermal Resistance θ

Output IC Junction-to-Case Thermal Resistance θ

1

Device considered a 2-terminal device: Pin 1 to Pin 8 are shorted together and Pin 9 to Pin 16 are shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

Table 4. ADM2485 Approvals

Organization Approval Type Notes

UL

VDE

Recognized under the Component Recognition

rogram of Underwriters Laboratories, Inc.

P

Certified according to DIN V VDE V 0884-10

VDE V 0884-10): 2006-12

(

1

R

I-O

C

I-O

C

I

JCI

JCO

1012 Ω 3 pF f = 1 MHz 4 pF 33 °C/W

28 °C/W

Thermocouple located at center of

age underside

pack Thermocouple located at center of

age underside

pack

In accordance with UL 1577, each ADM2485 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 second (current leakage detection limit = 5 μA).

In accordance with DIN V VDE V 0884-10, each ADM2485 is proof tested by applying an insulation test voltage ≥1050 V peak for 1 second (partial discharge detection limit = 5 pC).

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 5.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration Minimum External Air Gap (External Clearance) L(I01) 5.15 min mm

Measured from input terminals t shortest distance through air

Minimum External Tracking (Creepage) L(I02) 5.5 min mm

Measured from input terminals t

shortest distance along body Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303-1 Isolation Group IIIa Material Group (DIN VDE 0110: 1989-01, Table 1)

o output terminals,

Rev. A | Page 6 of 20

ADM2485

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VDE 0884-2 INSULATION CHARACTERISTICS

This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits.

An asterisk (*) on packages denotes DIN V VDE V 0884-10 approval.

Table 6.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110 for Rated Mains Voltage

≤150 V rms I to IV ≤300 V rms I to III

≤400 V rms I to II Climatic Classification 40/85/21 Pollution Degree (DIN VDE 0110: 1989-01, Table 1) 2 Maximum Working Insulation Voltage V Input-to-Output Test Voltage V

Method B1: V

Method A (After Environmental Tests, Subgroup 1): V

× 1.875 = VPR, 100% Production Tested, tm = 1 sec, Partial Discharge < 5 pC 1050 V peak

IORM

× 1.6 = VPR, tm = 60 sec,

IORM

PR

Partial Discharge <5 pC 896 V peak

Method A (After Input and/or Safety Test, Subgroup 2/3): V

Partial Discharge <5 pC Highest Allowable Overvoltage Safety-Limiting Values

2

1

Case Temperature T Input Current I Output Current I

Insulation Resistance at T

1

Transient overvoltage, tTR = 10 sec.

2

The safety-limiting value is the maximum value allowed in the event of a failure. See Figure 14 for the thermal derating curve.

3

VIO = 500 V.

3

S

× 1.2 = VPR, tm = 60 sec,

IORM

672 V peak V

TR

S

S, INPUT

S, OUTPUT

R

S

560 V peak

4000 V peak

150 °C 265 mA 335 mA

9

>10

Ω

Rev. A | Page 7 of 20

ADM2485

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. All voltages are relative to their respective grounds.

Table 7.

Parameter Rating V

DD1

V

DD2

Digital Input Voltage (RTS, RE, TxD) Digital Output Voltage

RxD −0.5 V to V DE OUT −0.5 V to V

D1, D2 13 V Driver Output/Receiver Input Voltage −9 V to +14 V Operating Temperature Range −40°C to +85°C Storage Temperature Range −55°C to +150°C Average Output Current per Pin −35 mA to +35 mA θJA Thermal Impedance 73°C/W Lead Temperature

Soldering (10 sec) 300°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−0.5 V to +6 V

−0.5 V to V

DD1

DD2

+ 0.5 V

+ 0.5 V + 0.5 V

Stresses above those listed under Absolute Maximum Ratings

y cause permanent damage to the device. This is a stress

ma rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 8 of 20

ADM2485

G

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

D1

D2

ND

1

V

DD1

RxD

RE

RTS

TxD

Figure 6. Pin Configuration

Table 8. Pin Function Description

Pin No. Mnemonic Function

1 D1 Transformer Driver Terminal 1. 2 D2 Transformer Driver Terminal 2. 3 GND 4 V

DD1

1

Ground, Logic Side. Power Supply, Logic Side (3.3 V or 5 V). Decoupling capacitor to GND1 required; capacitor value should be

between 0.01 μF and 0.1 μF.

5 RxD

Receiver Output Data. This output is high when (A − B) > 200 mV and low when (A − B) < −200 mV. The output is tristated when the receiver is disabled, that is, when RE

6

RE

Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver; driving it

high disables the receiver. 7 RTS 8 TxD 9, 11, 14, 15 GND

2

10 DE OUT 12 A

Driver Enable Input. Driving this input high enables the driver; driving it low disables the driver.

Driver Input. Data to be transmitted by the driver is applied to this input.

Ground, Bus Side.

Driver Enable Status Output.

Noninverting Driver Output/Receiver Input. When the driver is disabled or V

Pin A is put in a high impedance state to avoid overloading the bus. 13 B

Inverting Driver Output/Receiver Input. When the driver is disabled or V

Pin B is put in a high impedance state to avoid overloading the bus. 16 V

DD2

Power Supply, Bus Side (Isolated 5 V Supply). Decoupling capacitor to GND2 required; capacitor value

should be between 0.01 μF and 0.1 μF.

1

2

3

ADM2485

4

TOP VIEW

(Not to Scale)

5

6

7

8

16

15

14

13

12

11

10

9

V

DD2

GND

2

GND

2

B

A

GND

2

DE OUT

GND

2

06021-002

is driven high.

or V

is powered down,

DD2

is powered down,

DD2

DD1

or V

Rev. A | Page 9 of 20

ADM2485

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TYPICAL PERFORMANCE CHARACTERISTICS

2.40

60

2.35

2.30

2.25

2.20

2.15

SUPPLY CURRENT (mA)

2.10

2.05

2.00 –40 –20 0 20 40 60 80

I

_DE_ENABLE_V

DD2

_RE_ENABLE_V

DD1

TEMPERATURE (°C)

DD1

= 5.5V

DD1

= 5.5V

Figure 7. Unloaded Supply Current vs. Temperature

5.0

I

_PROFIBUS LOAD_TxD = 1 6Mbps_V

DD1

4.5

4.0

3.5 I

_NO LOAD_TxD = 16Mbps_V

DD1

3.0

2.5

2.0

SUPPLY CURRENT (mA)

1.5

DD1

I

1.0

0.5

0

Figure 8. Logic Side Supply Cu

_PROFIBUS LOAD_TxD = 2 Mbps_V

I

DD1

I

_NO LOAD_TxD = 2Mbps_V

DD1

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

rrent (I

DD1

= 5.00V

DD1

= 5.00V

DD1

= 1 mA) vs. Temperature

60

I

_ PROFIBUS LOAD_TxD = 1 6Mbps_V

DD2

50

DD2

= 5.00V

50

40

30

20

10

DRIVER PROPAG ATION DELAY (ns)

0

–40 –20 0 20 40 60 80

06021-016

t

PLHA

PLHB

t

PHLB

t

PHLA

TEMPERATURE (°C)

06021-019

Figure 10. Driver Propagation Delay vs. Temperature

60

Rx PROP DELAY,

50

40

Rx PROP DELAY,

30

20

10

RECEIVER PROPAGATIO N DELAY (ns)

0

–40 –20 0 20 40 60 80

06021-017

t

= 5.00V

PLH_VDD2

t

= 5.00V

PHL_VDD2

TEMPERATURE (°C)

06021-020

Figure 11. Receiver Propagation Delay vs. Temperature

I

_PROFIBUS L OAD_TxD = 2Mb ps_V

DD2

40

30

20

SUPPLY CURRENT (mA)

DD2

I

Figure 9. Bus Side Supply Current (I

_NO LOAD_TxD = 16Mbps_V

I

DD2

10

I

_NO LOAD_TxD = 2Mbps_V

DD2

0

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

DD2

= 5.00V

DD2

= 5.00V

DD2

= 5.00V

= 2 mA) vs. Temperature

06021-018

Rev. A | Page 10 of 20

3

2

DI

B

A

CH1 2.0V Ω

CH3 2.0V Ω

CH2 2.0V Ω M20.0ns 1. 25GS/s

IT 8.0p s/pt

A CH3 2.60V

Figure 12. Driver/Receiver Propagation Delay, Low to High

= 54 Ω, CL1 = CL2 = 100 pF)

(R

LDIFF

6021-021

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60

50

1

3

CH1 1.0V Ω

CH3 2.0V Ω

CH2 1.0V Ω M10.0ns A CH1 120mV

T 19.8000ns

Figure 13. Driver/Receiver Propagation Delay, High to Low

= 54 Ω, CL1 = CL2 = 100 pF)

(R

LDIFF

350

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

SIDE 2

SIDE 1

40

30

20

OUTPUT CURRENT (mA)

10

0

012345

06021-022

OUTPUT VOLTAGE (V)

06021-025

Figure 16. Output Current vs. Receiver Output Low Voltage

4.75

4.74

4.73

4.72

4.71

4.70

OUTPUT VOLTAGE (V)

4.69

4.68

0

50 100 150 200

CASE TEMPERATURE ( °C)

Figure 14. Thermal Derating Curve, D

with Case Temperature per VDE 0884-2

0

–10

–20

–30

–40

–50

OUTPUT CURRENT ( mA)

–60

–70

012345

OUTPUT VOLTAGE (V)

Figure 15. Output Current vs. R

ependence of Safety-Limiting Values

eceiver Output High Voltage

4.67 –40 –20 0 20 40 60 80

06021-023

Figure 17. Receiver Output High Voltage vs. Temperature (I

TEMPERATURE (°C)

= –4 mA)

DD2

06021-031

0.32

0.30

0.28

0.26

0.24

OUTPUT VOLTAGE (V)

0.22

0.20 –40 –20 0 20 40 60 80

06021-024

Figure 18. Receiver Output Low Voltage vs. Temperature (I

TEMPERATURE (°C)

= –4 mA)

DD2

06021-032

Rev. A | Page 11 of 20

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D1

1

2

D2

CH1 2.0V Ω CH2 2.0V Ω M400ns 125MS/ s

8.0ns/p t

Figure 19. Switching Waveforms

(50 Ω Pul

l-Up to V

DD1

A CH2 1.52V

on D1 and D2)

1

06021-033

D1

D2

CH1 2.0V Ω CH2 2.0V Ω M80ns 625MS/ s

1.6ns/p t

Figure 20. Switching Waveforms

(Break

-Before-Make, 50 Ω Pull-Up to V

A CH2 1.52V

on D1 and D2)

DD1

06021-034

Rev. A | Page 12 of 20

ADM2485

Ω

V

A

V

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TEST CIRCUITS

V

OD

R

Figure 21. Driver Voltage Measurement

375

V

60Ω

OD3

375Ω

Figure 22. Driver Voltage Measurement

RTS

TxD

RxD

RE

V

DD1

GND

GALVANIC IS OLATION

V

1

DD2

GND

Figure 23. Supply-Current Measurement Test Circuit

V

TEST

2

V

OC

DE OUT

150Ω

V

A

B

GND

DD2

06021-003

06021-004

195Ω

110Ω

195Ω

2

A

R

B

LDIFF

C

L1

C

L2

6021-007

Figure 25. Driver Propagation Delay

GND

2

DE OUT

150Ω

A

B

50pF

06021-008

RTS

TxD

RxD

RE

GALVANIC ISOLATIO N

GND

V

DD1

1

V

DD2

Figure 26. RTS to DE OUT Propagation Delay

CC

A

TxD

06021-005

RTS

Figure 27. Driver Enable/Disable

S1

B

50pF

110Ω

V

OUT

S2

6021-009

GND

DE OUT

V

DD2

195Ω

A

110Ω

B

195Ω

GND

2

V

CM (HF)

GND

2.2kΩ

2

RTS

TxD

RxD

RE

GALVANIC IS OLATION

100nF

GND

V

1

DD2

100nF

V

DD1

Figure 24. High Frequency, Common-Mode Noise Test Circuit

V

RE

B

OUT

C

L

06021-010

Figure 28. Receiver Propagation Delay

RE

V

CC

R

L

C

V

L

OUT

S2

06021-011

F

,

V

22kΩ

TEST2

110nF

TEST

V

HF

+1.5

S1

–1.5V

06021-006

RE IN

50Ω

470nF

50Ω

2

Figure 29. Receiver Enable/Disable

Rev. A | Page 13 of 20

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CIRCUIT DESCRIPTION

ELECTRICAL ISOLATION

In the ADM2485, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see

Figure 30). Driver input and data enable, applied to the

xD and RTS pins, respectively, and referenced to logic ground

T (GND

), are coupled across an isolation barrier to appear at the

1

transceiver section referenced to isolated ground (GND

).

2

Similarly, the receiver output, referenced to isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to logic ground.

iCoupler Technology

The digital signals are transmitted across the isolation barrier using iCoupler technology. This technique uses chip-scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are then decoded into the binary value that was originally transmitted.

V

D1 D2

DD1

ENCODE

DECODE

1

ISOLATION

BARRIER

OSC

TxD

RTS

RxD

RE

DIGITAL ISOLATION

GND

Figure 30. ADM2485 Digital Isolation and Transceiver Sections

DECODE

ENCODE

V

GND

DD2

2

D

R

TRANSCEIVER

A

B

DE OUT

TRUTH TABLES

Tabl e 1 0 and Tabl e 11 use the abbreviations found in Tabl e 9.

Table 9. Truth Table Abbreviations

Letter Description

H High level I Indeterminate L Low level X Irrelevant Z High impedance (off) NC Disconnected

06021-026

Table 10. Transmitting

Supply Status Inputs Outputs

V

DD1

V

DD2

RTS TxD A B DE OUT

On On H H H L H On On H L L H H On On L X Z Z L On Off X X Z Z L Off On X X Z Z L Off Off X X Z Z L

Table 11. Receiving

Supply Status Input Outputs

V

DD1

V

DD2

A − B

RE

RxD

On On >+0.2 V L or NC H On On <–0.2 V L or NC L On On −0.2 V < A − B < +0.2 V L or NC I On On Inputs open L or NC H On On X H Z On Off X L or NC H Off On X L or NC H Off Off X L or NC L

THERMAL SHUTDOWN

The ADM2485 contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150°C is reached. As the device cools, the drivers are re-enabled at a temperature of 140°C.

RECEIVER FAIL-SAFE INPUTS

The receiver input includes a fail-safe feature that guarantees a Logic high RxD output when the A and B inputs are floating or open-circuited.

Rev. A | Page 14 of 20

ADM2485

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MAGNETIC FIELD IMMUNITY

Because iCouplers use a coreless technology, no magnetic components are present and the problem of magnetic saturation of the core material does not exist. Therefore, iCouplers have essentially infinite dc field immunity. The following analysis defines the conditions under which this can occur. The ADM2485

3.3 V operating condition is examined because it represents the most susceptible mode of operation.

The limitation on the iC set by the condition in which the induced error voltage in the receiving coil (the bottom coil, in this case) is made sufficiently large, either to falsely set or reset the decoder. The voltage induced across the bottom coil is given by

dβ

−

⎞

⎛

V

=

⎟

⎜

∑

dt

⎠

⎝

where, if the pulses at the transformer output are greater than

1.0 V in am

plitude:

β is the magnetic flux density (gauss). N is the number of turns in the receiving coil. r

is the radius of nth turn in the receiving coil (cm).

n

The decoder has a sensing threshold of about 0.5 V; therefore, t

here is a 0.5 V margin where induced voltages can be tolerated.

Given the geometry of the receiving coil and an imposed r

equirement that the induced voltage is, at most, 50% of the

0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in

100

10

1

0.1

oupler ac magnetic field immunity is

2

; n = 1, 2 … N (1)

π

r

n

Figure 31.

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kGauss induces a voltage of 0.25 V at the receiving coil, which is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and it is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

Figure 32 shows the magnetic flux density values in terms of more

familiar quantities, such as maximum allowable current

flow at given distances from the ADM2485 transformers.

1000

100

DISTANCE = 5mm

10

0

0.1

MAXIMUM ALL OWABLE CURRENT (kA)

0.01

DISTANCE = 100mm

1k 10k 100k 100M1M 10M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 32. Maximum Allowable Current for

Vari

ous Current-to-ADM2485 Spacings

DISTANCE = 1m

06021-028

At combinations of strong magnetic field and high frequency, any loops formed by printed circuit board (PCB) traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care must be taken in the layout of such traces to avoid this possibility.

FLUX DENSIT Y (kGAUSS)

0.01

MAXIMUM ALLOWABLE MAGNETIC

0.001 1k 10k 100k 100M1M 10M

Figure 31. Maximum Allowable External Magnetic Flux Density vs.

MAGNETIC F IELD FREQUENCY (Hz)

c Field Frequency

Magneti

6021-027

Rev. A | Page 15 of 20

ADM2485

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APPLICATIONS INFORMATION

PCB LAYOUT

The ADM2485 isolated RS-485 transceiver requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 33).

Bypass capacitors are most conveniently connected between Pin 3 an V

d Pin 4 for V

. The capacitor value must be between 0.01 μF and 0.1 μF.

DD2

and between Pin 15 and Pin 16 for

DD1

The total lead length between both ends of the capacitor and the input power supply pin must not exceed 20 mm.

Bypassing between Pin 9 and Pin 16 is also recommended

nless the ground wires on the V

u

side are connected close to

DD2

the package.

D1 D2

GND

1

V

DD1

RxD

RE

RTS

TxD

Figure 33. Recommended Printed Circuit Board Layout

ADM2485

V

DD2

GND

2

GND

2

B A GND

2

DE OUT GND

2

6021-029

In applications involving high common-mode transients, care must be taken to ensure that board coupling across the isolation barrier is minimized. Furthermore, the board layout must be designed such that any coupling that does occur equally affects all pins on a given component side.

Failure to ensure this can cause voltage differentials between

ins exceeding the device absolute maximum ratings, thereby

p leading to latch-up or permanent damage.

TRANSFORMER SUPPLIERS

The transformer primarily used with the ADM2485 must be a center-tapped transformer winding. The turns ratio of the transformer must be set to provide the minimum required output voltage at the maximum anticipated load with the minimum input voltage.

ppliers.

su

Tabl e 1 2 shows ADM2485 transformer

APPLICATIONS DIAGRAM

The ADM2485 integrates a transformer driver that, when used with an external transformer and LDO, generates an isolated 5 V power supply, to be supplied between V

D1 and D2 of the ADM2485 drive the center-tapped

ransformer T1. A pair of Schottky diodes and a smoothing

T capacitor is used to create a rectified signal from the secondary winding. The ADP3330 linear voltage regulator provides a regulated 5 V power supply to the ADM2485 bus-side circuitry (V

), as shown in Figure 34.

DD2

When the ADM2485 is powered by 3.3 V on the logic side, a

:2.2CT Transformer T1 is required to step up the 3.3 V to

1CT 6 V, ensuring enough headroom for the ADP3330 LDO to output a regulated 5 V output.

If ADM2485 is powered by 5 V on the logic side, a 1CT:1.5CT T

ransformer T1 is required, ensuring enough headroom for the

ADP3330 LDO to output a regulated 5 V output.

ISOLATION BARRIER

1N5817

V

100nF

CC

10µF

MLC

T1

1N5817

V

CC

V

D1 D2 V

DD1

ADM2485

GND

1

Figure 34. Applications Diagram

DD2

GND

22µF

ISO 5V

2

and GND2.

DD2

ERR NR

IN

OUT

ADP3330

SD

GND

100nF

5V

10µF

06021-030

Table 12. Transformer Suppliers

Manufacturer Primary Voltage 3.3 V Primary Voltage 5 V

Coilcraft DA2304-AL DA2303-AL C&D Technologies 782485/35C 782485/55C

Rev. A | Page 16 of 20

ADM2485

C

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OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

.

2

5

(

0

5

(

0

.

0

2

9

5

)

0

9

8

)

.

1.27 (0.0500)

0.40 (0.0157)

45°

032707-B

0.30 (0.0 118)

0.10 (0.0039)

OPLANARIT Y

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLL ING DIMENSIONS ARE IN MILLI METERS; INCH DIMENSI ONS (IN PARENTHESES) ARE ROUNDED-O FF MILLIMET ER EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE I N DESIGN.

COMPLIANT TO JEDEC STANDARDS MS-013- AA

Figure 35. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Data Rate (Mbps) Temperature Range Package Description Package Option

ADM2485BRWZ ADM2485BRWZ-REEL7

1

Z = RoHS Compliant Part.

1

16 −40°C to +85°C 16-Lead SOIC_W RW-16

1

16 −40°C to +85°C 16-Lead SOIC_W RW-16

Rev. A | Page 17 of 20

ADM2485

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NOTES

Rev. A | Page 18 of 20

ADM2485

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NOTES

Rev. A | Page 19 of 20

ADM2485

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NOTES

Rev. A | Page 20 of 20

Datasheet ADM2485 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

Timing Diagrams

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION

INSULATION AND SAFETY-RELATED SPECIFICATIONS

VDE 0884-2 INSULATION CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

CIRCUIT DESCRIPTION

ELECTRICAL ISOLATION

iCoupler Technology

TRUTH TABLES

THERMAL SHUTDOWN

RECEIVER FAIL-SAFE INPUTS

MAGNETIC FIELD IMMUNITY

APPLICATIONS INFORMATION

PCB LAYOUT

TRANSFORMER SUPPLIERS

APPLICATIONS DIAGRAM

OUTLINE DIMENSIONS

ORDERING GUIDE