Datasheet ADM2484E Datasheet (ANALOG DEVICES)

500 kbps, ESD Protected, Half-/Full-Duplex,

V

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iCoupler, Isolated RS-485 Transceiver

FEATURES

Isolated, RS-485/RS-422 transceiver, configurable as half- or

full-duplex ±15 kV ESD protection on RS-485 input/output pins 500 kbps data rate Complies with ANSI TIA/EIA RS-485-A-1998 and

ISO 8482: 1987(E) Suitable for 5 V or 3.3 V operation (V High common-mode transient immunity: >25 kV/μs True fail-safe receiver inputs 256 nodes on the bus Thermal shutdown protection Safety and regulatory approvals pending

UL recognition

5000 V rms isolation voltage for 1 minute per UL1577

VDE certificate of conformity

DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 Reinforced insulation, V

IORM

Operating temperature range: −40°C to +85°C Wide body, 16-lead SOIC package

)

DD1

= 848 V peak

ADM2484E

FUNCTIONAL BLOCK DIAGRAM

DE

TxD

RxD

RE

DD1

GND

GALVANIC ISOLATION

1

Figure 1.

DD2

ADM2484E

GND

Y

Z

A

B

2

06984-001

APPLICATIONS

Isolated RS-485/RS-422 interfaces Industrial field networks INTERBUS Multipoint data transmission systems

GENERAL DESCRIPTION

The ADM2484E is an isolated data transceiver with ±15 kV ESD protection suitable for high speed, half- or full-duplex communication on multipoint transmission lines. For halfduplex operation, the transmitter outputs and receiver inputs share the same transmission line. Transmitter Output Pin Y links externally to Receiver Input Pin A, and Transmitter Output Pin Z links externally to Receiver Input Pin B.

Designed for balanced transmission lines, the ADM2484E complies with ANSI TIA/EIA RS-485-A-1998 and ISO 8482: 1987(E). The device employs Analog Devices, Inc., iCoupler®

technology to combine a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single package.

The differential transmitter outputs and receiver inputs feature electrostatic discharge circuitry that provides protection up to ±15 kV using the human body model (HBM). The logic side of the device can be powered with either a 5 V or a 3.3 V supply, whereas the bus side requires an isolated 3.3 V supply.

The device has current-limiting and thermal shutdown features to protect against output short circuits and situations where bus contention causes excessive power dissipation.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

5/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

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SPECIFICATIONS

All voltages are relative to their respective grounds, 3.0 V ≤ V apply over the entire recommended operation range, all typical specifications are at T otherwise noted.

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions

SUPPLY CURRENT

Power Supply Current, Logic Side

TxD/RxD Data Rate = 500 kbps I

2.0 mA Unloaded

DD1

2.0 mA

Power Supply Current, Bus Side

TxD/RxD Data Rate = 500 kbps I

3.0 mA Unloaded

DD2

40 mA

DRIVER

Differential Outputs

Differential Output Voltage |VOD| 2.0 3.6 V

1.5 3.6 V RL = 54 Ω (RS-485), see Figure 14

1.5 3.6 V −7 V ≤ V ∆|VOD| for Complementary Output States ∆|VOD| 0.2 V RL = 54 Ω or 100 Ω, see Figure 14 Common-Mode Output Voltage VOC 3.0 V RL = 54 Ω or 100 Ω, see Figure 14 ∆|VOC| for Complementary Output States ∆|VOC| 0.2 V RL = 54 Ω or 100 Ω, see Figure 14 Output Leakage Current (Y, Z Pins) IO +30 μA DE = 0 V, V

−30 μA DE = 0 V, V Short-Circuit Output Current IOS 250 mA

Logic Inputs (DE, RE, TxD)

Input Threshold Low VIL 0.25 × V Input Threshold High VIH 0.7 × V Input Current II −10 +0.01 +10 μA

RECEIVER

Differential Inputs

Differential Input Threshold Voltage VTH −200 −125 −30 mV −7 V < VCM < +12 V Input Voltage Hysteresis V

15 mV VOC = 0 V

HYS

Input Current (A, B) II +125 μA DE = 0 V, VDD = 0 V or 3.6 V, VIN = +12 V

−100 μA DE = 0 V, VDD = 0 V or 3.6 V, VIN = −7 V Line Input Resistance RIN 96 kΩ −7 V < VCM < +12 V Tristate Leakage Current I

±1 μA V

OZR

Logic Outputs

Output Voltage Low V Output Voltage High V

0.2 0.4 V I

OLRxD

V

OHRxD

Short-Circuit Current 100 mA

COMMON-MODE TRANSIENT IMMUNITY

1

CM is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation. VCM is the common-mode potential

difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

1

25 kV/μs VCM = 1 kV, transient magnitude = 800 V

≤ 5.5 V and 3.0 V ≤ V

DD1

V

DD1

− 0.3 V

DD1

≤ 3.6 V, all minimum/maximum specifications

DD2

= 25°C, V

A

V

DD1

= 5 V, and V

DD1

− 0.2 V I

= 3.3 V, unless

DD2

= 5.5 V, half duplex configuration,

V

DD2

R

TERMINATION

V

DD2

R

TERMINATION

Loaded, R Figure 14

DD1

ORxD

= 120 Ω, see Figure 20

= 5.5 V, half duplex configuration,

= 120 Ω, see Figure 20

= 100 Ω (RS-422), see

L

≤ 12 V, see Figure 15

TEST

= 0 V or 5 V, VIN = +12 V

DD2

= 0 V or 5 V, VIN = −7 V

DD2

= 5 V, 0 V < V

OUT

< V

DD1

= 1.5 mA, VA − VB = −0.2 V = −1.5 mA, VA − VB = +0.2 V

Rev. 0 | Page 3 of 16

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TIMING SPECIFICATIONS

TA = −40°C to +85°C.

Table 2.

Parameter Symbol Min Typ Max Unit Test Conditions

DRIVER

Propagation Delay t Differential Driver Output Skew

(t

− t

DPHL

)

DPLH

Rise Time/Fall Time tDR, tDF 200 450 1100 ns RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and Figure 21 Enable Time tZL, tZH 1.5 μs RL = 110 Ω, CL = 50 pF, see Figure 18 and Figure 22 Disable Time tLZ, tHZ 200 ns RL = 110 Ω, CL = 50 pF, see Figure 18 and Figure 22

RECEIVER

Propagation Delay t Pulse Width Distortion,

PWD = |t

PLH

− t

PHL

| Enable Time tZL, tZH 13 ns RL = 1 kΩ, CL = 15 pF, see Figure 19 and Figure 24 Disable Time tLZ, tHZ 13 ns RL = 1 kΩ, CL = 15 pF, see Figure 19 and Figure 24

PACKAGE CHARACTERISTICS

Table 3.

Parameter Symbol Min Typ Max Unit Test Conditions

RESISTANCE

Resistance (Input-to-Output)1 R

CAPACITANCE

Capacitance (Input-to-Output) Input Capacitance

2

THERMAL RESISTANCE

Input IC Junction-to-Case θ Output IC Junction-to-Case θ

1

Device considered a 2-terminal device: Pin 1 to Pin 8 are shorted together and Pin 9 to Pin16 are shorted together.

2

Input capacitance is from any input data pin to ground.

1

, t

DPLH

t

DSKEW

PLH

t

PWD

C

250 700 ns RL = 54 Ω, CL1 = C

DPHL

100 ns RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 16 and Figure 21

, t

200 ns CL = 15 pF, see Figure 17 and Figure 23

PHL

30 ns CL = 15 pF, see Figure 17 and Figure 23

1012 Ω

I-O

3 pF f = 1 MHz

I-O

= 100 pF, see Figure 16 and Figure 21

L2

CI 4 pF

33 °C/W Thermocouple located at center of package underside

JCI

28 °C/W

JCO

REGULATORY INFORMATION (PENDING)

Table 4.

1

UL

VDE

1577 Component Recognition Program (Pending) To be certified according to DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12

5000 V rms Isolation Voltage Reinforced insulation, 846 V peak

1

In accordance with UL1577, each ADM2484E is proof tested by applying an insulation test voltage ≥ 6000 V rms for 1 second (current leakage detection limit = 10 μA).

2

In accordance with DIN V VDE V 0884-10, each ADM2484E is proof tested by applying an insulation test voltage ≥ 1590 V peak for 1 second (partial discharge detection

limit = 5 pC).

Rev. 0 | Page 4 of 16

2

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INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 5.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 5000 V rms 1-minute duration Minimum External Air Gap (Clearance) L(I01) 7.7 mm min

Minimum External Tracking (Creepage) L(I02) 8.1 mm min

Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1 Isolation Group IIIa Material Group (DIN VDE 0110, 1/89)

VDE 0884 INSULATION CHARACTERISTICS (PENDING)

This isolator is suitable for basic electrical isolation only within the safety limit data. Maintenance of the safety data must be ensured by means of protective circuits.

Table 6.

Description Conditions Symbol Characteristic Unit

CLASSIFICATIONS

Installation Classification per DIN VDE 0110 for Rated Mains Voltage

≤300 V rms I to IV ≤450 V rms I to II

≤600 V rms I to II Climatic Classification 40/105/21 Pollution Degree DIN VDE 0110, see Table 1 2

VOLTAGE

Maximum Working Insulation Voltage V Input-to-Output Test Voltage VPR

Method b1

Method a

After Environmental Tests, Subgroup 1

After Input and/or Safety Test, Subgroup 2/Subgroup 3

Highest Allowable Overvoltage (Transient overvoltage, tTR = 10 sec) VTR 6000 V

SAFETY-LIMITING VALUES

Case Temperature TS 150 °C Input Current IS, Output Current IS, Insulation Resistance at TS V

× 1.875 = VPR, 100% production tested,

V

IORM

t

= 1 sec, partial discharge < 5 pC

m

× 1.6 = VPR, tm = 60 sec, partial

V

IORM

discharge < 5 pC V

× 1.2 = VPR, tm = 60 sec, partial

IORM

discharge < 5 pC

Maximum value allowed in the event of a failure, see Figure 9

= 500 V RS >109 Ω

IO

Measured from input terminals to output terminals, shortest distance through air

Measured from input terminals to output terminals, shortest distance along body

848 V

IORM

1590 V

1357 V

1018 V

265 mA

INPUT

335 mA

OUTPUT

PEAK

Rev. 0 | Page 5 of 16

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Each voltage is relative to its respective ground.

Table 7.

Parameter Rating

V

−0.5 V to +7 V

DD1

V

−0.5 V to +6 V

DD2

Logic Input Voltages −0.5 V to V Bus Terminal Voltages −9 V to +14 V Logic Output Voltages −0.5 V to V Average Output Current per Pin ±35 mA ESD (Human Body Model) on A, B, Y,

and Z Pins Storage Temperature Range −55°C to +150°C Ambient Operating Temperature Range −40°C to +85°C θJA Thermal Impedance 73°C/W

±15 kV

+ 0.5 V

DD1

+ 0.5 V

DD1

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute maximum ratings apply individually only, not in combination.

ESD CAUTION

Rev. 0 | Page 6 of 16

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

DD1

GND

2

1

RxD

3

ADM2484E

4

RE

(Not to Scale)

DE

5

TxD

6

NC

7

8

GND

1

NC = NO CONNECT

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Power Supply (Logic Side). Decoupling capacitor to GND1 required; capacitor value should be between 0.01 μF and 0.1 μF.

DD1

2 GND1 Ground (Logic Side). 3 RxD Receiver Output. 4

Receiver Enable Input. Active low logic input. When this pin is low, the receiver is enabled; when this pin is high, the

RE

receiver is disabled.

5 DE

Driver Enable Input. Active high logic input. When this pin is high, the driver (transmitter) is enabled; when this pin

is low, the driver is disabled. 6 TxD Transmit Data. 7 NC No Connect. This pin must be left floating. 8 GND1 Ground (Logic Side). 9 GND2 Ground (Bus Side). 10 NC No Connect. This pin must be left floating. 11 Y Driver Noninverting Output. 12 Z Driver Inverting Output. 13 B Receiver Inverting Input. 14 A Receiver Noninverting Input. 15 GND2 Ground (Bus Side). 16 V

Power Supply (Bus Side). Decoupling capacitor to GND2 required; capacitor value should be between 0.01 μF and 0.1 μF.

DD2

TOP VIEW

16

V

DD2

GND

15

2

A

14

13

B

Z

12

Y

11

NC

10

9

GND

2

06984-002

Rev. 0 | Page 7 of 16

ADM2484E

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TYPICAL PERFORMANCE CHARACTERISTICS

1.4

1.2

NO LOAD

1.0

54Ω LOAD 100Ω LOAD

0.8

0.6

SUPPLY CURRENT (mA)

0.4

DD1

I

0.2

0

–40–200 20406080

TEMPERATURE (° C)

Figure 3. I

Supply Current vs. Temperature (See Figure 20)

DD1

DATA RATE = 500kb ps

06984-033

100

90

80

70

60

50

DELAY (ns)

40

30

20

10

0

–40–200 20406080

t

PHL

t

PLH

TEMPERATURE (° C)

Figure 6. Receiver Propagation Delay vs. Temperature

06984-035

45

40

35

30

25

20

15

SUPPLY CURRENT (mA)

DD2

I

10

5

0

–40–200 20406080

Figure 4. I

600

500

400

300

DELAY (ns)

200

Supply Current vs. Temperature (See Figure 20)

DD2

54Ω LOAD

100Ω LOAD

NO LOAD

TEMPERATURE (° C)

t

DPLH

t

DPHL

DATA RATE = 500kbps

T

1

2

06984-034

4

TxD

Z, B

Y, A

CH1 2.00V CH2 2.00V CH3 2.00V CH4 2.00V

RxD

M 200ns A CH2 1.72V

T 47.80%

06984-031

Figure 7. Driver/Receiver Propagation Delay, Low to High

(R

= 54 Ω, CL1 = CL2 = 100 pF)

L

T

1

2

TxD

Z, B

Y, A

100

0

–40–200 20406080

TEMPERATURE (° C)

06984-032

Figure 5. Driver Propagation Delay vs. Temperature

Rev. 0 | Page 8 of 16

4

CH1 2.00V CH2 2.00V CH3 2.00V CH4 2.00V

RxD

M 200ns A CH2 1.72V

T 48.60%

Figure 8. Driver/Receiver Propagation Delay, High to Low

(R

= 54 Ω, CL1 = CL2 = 100 pF)

L

06984-030

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350

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

SIDE 2

SIDE 1

50 100 150 200

CASE TEMPERATURE (°C)

06984-016

Figure 9. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per VDE 0884

0

4.77

4.76

4.75

4.74

4.73

4.72

4.71

VOLTAGE (V)

4.70

4.69

4.68

4.67

4.66 –40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

Figure 12. Receiver Output High Voltage vs. Temperature, I

0.35

= −4 mA

RxD

06984-019

–2

–4

–6

–8

CURRENT (mA)

–10

–12

–14

4.04.24.44.64.85

VOLTAGE (V)

Figure 10. Output Current vs. Receiver Output High Voltage

16

14

12

10

8

6

CURRENT (mA)

4

06984-017

.0

0.30

0.25

0.20

0.15

VOLTAGE (V)

0.10

0.05

0

–40 –20 0 20 40 60 80 100

TEMPERATURE (°C)

Figure 13. Receiver Output Low Voltage vs. Temperature, I

= +4 mA

RxD

06984-022

2

0

0 0.2 0.4 0.6

VOLTAGE (V)

0.8 1.0 1. 2

06984-018

Figure 11. Output Current vs. Receiver Output Low Voltage

Rev. 0 | Page 9 of 16

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TEST CIRCUITS

Figure 14. Driver Voltage Measurement

R

L

V

OD

2

R

L

2

V

OC

06984-003

A

V

B

OUT

C

L

06984-007

Figure 17. Receiver Propagation Delay

375Ω

V

60Ω

OD

375Ω

V

TEST

Figure 15. Driver Voltage Measurement

Y

Z

R

L

C

L1

C

L2

Figure 16. Driver Propagation Delay

V

OUT

Y

0V OR 3V

06984-004

DE

S1

Z

C

L

Figure 18. Driver Enable/Disable

+1.5V

S1

–1.5V

06984-006

RE IN

RE

R

L

C

L

V

OUT

Figure 19. Receiver Enable/Disable

V

CC

R

L

S2

06984-008

V

CC

S2

06984-009

V

DD2

V

DD1

V

DD2

DE

Y

TxD

120Ω

Z

RxD

RE

GND

GALVANIC ISOLATION

1

Figure 20. Supply Current Measurement Test Circuit

Rev. 0 | Page 10 of 16

GND

A

B

2

06984-005

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SWITCHING CHARACTERISTICS

V

DD1

V

/2

DD1

0V

Z

V

O

Y

+V

O

V

DIFF

10% POINT 10% POINT

–V

O

t

DPLH

1/2V

O

90% POINT 90% POINT

t

DR

Figure 21. Driver Propagation Delay, Rise/Fall Timing

DE

Y, Z

0.5V

t

ZL

t

ZH

DD1

2.3V

Figure 22. Driver Enable/Disable Delay

V

/2

DD1

t

DPHL

A, B

V

= V

– V

DIFF

(Y)

(Z)

t

DF

06984-010

RxD

0V 0V

t

PLH

1.5V 1.5V

t

PHL

V

OH

V

OL

Figure 23. Receiver Propagation Delay

V

DD1

t

0.5V

LZ

HZ

DD1

V

+ 0.5V

OL

VOH – 0.5V

0V

V

OL

V

OH

0V

t

LZ

t

HZ

0.5V

DD1

V

+ 0.5V

OL

VOH – 0.5V

V

DD1

0V

V

OL

V

OH

0V

06984-011

RE

RxD

0V

0.5V

t

ZH

DD1

ZL

1.5V

OUTPUT LOW

OUTPUT HIGH

1.5V

Figure 24. Receiver Enable/Disable Delay

06984-012

06984-013

Rev. 0 | Page 11 of 16

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CIRCUIT DESCRIPTION

ELECTRICAL ISOLATION

In the ADM2484E, electrical isolation is implemented on the logic side of the interface. Therefore, the part has two main sections: a digital isolation section and a transceiver section (see Figure 25). The driver input signal, which is applied to the TxD pin and referenced to the logic ground (GND across an isolation barrier to appear at the transceiver section referenced to the isolated ground (GND

). Similarly, the

2

receiver input, which is referenced to the isolated ground in the transceiver section, is coupled across the isolation barrier to appear at the RxD pin referenced to the logic ground.

iCoupler Technology

The digital signals transmit across the isolation barrier using iCoupler technology. This technique uses chip scale transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs are encoded into waveforms that are capable of exciting the primary transformer winding. At the secondary winding, the induced waveforms are decoded into the binary value that was originally transmitted.

Positive and negative logic transitions at the input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than ~1 s, a periodic set of refresh pulses, indicative of the correct input state, are sent to ensure dc correctness at the output. If the decoder receives no internal pulses for more than about 5 s, then the input side is assumed to be unpowered or nonfunctional, in which case the output is forced to a default state (see Tab l e 1 0 ).

V

DD1

ISOLATION

BARRIER

DE

ENCODE

DECODE

V

DD2

), is coupled

1

TRUTH TABLES

The truth tables in this section use the abbreviations shown in Tab l e 9.

Table 9. Truth Table Abbreviations

Letter Description

H High level L Low level I Indeterminate X Irrelevant Z High impedance (off) NC Disconnected

Table 10. Transmitting

Supply Status Inputs Outputs

V

DD1

On On H H H L On On H L L H On On L X Z Z On Off X X Z Z Off On L X Z Z Off Off X X Z Z

Table 11. Receiving

Supply Status Inputs Output

V

DD1

On On > −0.03 On On < −0.2 On On −0.2 < A − B < −0.03 On On Inputs open On On X On Off X Off Off X

DE TxD Y Z

DD2

RxD

A − B (V)

DD2

RE

L or NC L or NC L or NC L or NC H L or NC L or NC

H L I H Z H L

TxD

RxD

RE

GND

D

R

TRANSCEIVERDIGITAL ISOLATION

2

DECODEENCODE

DECODE

GND

1

Figure 25. Digital Isolation and Transceiver Sections

ENCODE

Y

Z

A

B

06984-023

Rev. 0 | Page 12 of 16

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THERMAL SHUTDOWN

The ADM2484E contains thermal shutdown circuitry that protects the part from excessive power dissipation during fault conditions. Shorting the driver outputs to a low impedance source can result in high driver currents. The thermal sensing circuitry detects the increase in die temperature under this condition and disables the driver outputs. This circuitry is designed to disable the driver outputs when a die temperature of 150°C is reached. As the device cools, the drivers re-enable at a temperature of 140°C.

TRUE FAIL-SAFE RECEIVER INPUTS

The receiver inputs have a true fail-safe feature ensuring that the receiver output is high when the inputs are open or shorted. During line-idle conditions, when no driver on the bus is enabled, the voltage across a terminating resistor at the receiver input decays to 0 V. With traditional transceivers, receiver input thresholds specified between −200 mV and +200 mV mean that external bias resistors are required on the A and B pins to ensure that the receiver outputs are in a known state. The true fail-safe receiver input feature eliminates the need for bias resistors by specifying the receiver input threshold between −30 mV and −200 mV. The guaranteed negative threshold means that when the voltage between A and B decays to 0 V; the receiver output is guaranteed to be high.

MAGNETIC FIELD IMMUNITY

The limitation on the magnetic field immunity of the iCoupler is set by the condition in which an induced voltage in the receiving coil of the transformer is large enough to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADM2484E is examined because it represents the most susceptible mode of operation.

The pulses at the transformer output have an amplitude greater then 1 V. The decoder has a sensing threshold of about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated.

The voltage induced across the receiving coil is given by

β−

d

⎞

⎛

=

V

⎜

dt

⎝

where:

β is the magnetic flux density (gauss). N is the number of turns in the receiving coil.

is the radius of the nth turn in the receiving coil (cm).

r

n

Given the geometry of the receiving coil and an imposed requirement that the induced voltage is, at most, 50% of the

0.5 V margin at the decoder, a maximum allowable magnetic field can be determined using Figure 26.

2

π

r

; Nn ,...,2,1=

⎟

∑

n

⎠

100

10

1

0.1

FLUX DENSIT Y (kGAUSS)

0.01

MAXIMUM ALLOWABLE MAG NETIC

0.001

1k 10k 100k 100M1M 10M

Figure 26. Maximum Allowable External Magnetic Flux Density

MAGNETIC FIELD FREQ UENCY (Hz)

06984-024

For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse and is the worst-case polarity, it reduces the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder.

Figure 27 shows the magnetic flux density values in terms of more familiar quantities, such as maximum allowable current flow at given distances away from the ADM2484E transformers.

1000

DISTANCE = 1m

100

DISTANCE = 5mm

10

1

0.1

MAXIMUM ALLOWABLE CURRENT (kA)

0.01

DISTANCE = 100mm

1k 10k 100k 100M1M 10M

MAGNETIC F IELD FREQ UENCY (Hz)

Figure 27. Maximum Allowable Current for

Various Current-to-ADM2484E Spacings

06984-025

With combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error voltages large enough to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.

Rev. 0 | Page 13 of 16

ADM2484E

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

ISOLATED POWER SUPPLY CIRCUIT

The ADM2484E requires isolated power capable of 3.3 V at up to approximately 75 mA (this current is dependent on the data rate and termination resistors used) to be supplied between the

and the GND2 pins. A transformer driver circuit with a

V

DD2

center tapped transformer and LDO can be used to generate the isolated 5 V supply, as shown in Figure 28. The center tapped transformer provides electrical isolation of the 5 V power supply. The primary winding of the transformer is excited with a pair of square waveforms that are 180° out of phase with each other. A pair of Schottky diodes and a smoothing capacitor are used to create a rectified signal from the secondary winding. The ADP3330 linear voltage regulator provides a regulated power supply to the bus-side circuitry (V

V

CC

TRANSFORMER

DRIVER

ISOLATION

BARRIER

SD103C

V

CC

78253

SD103C

V

CC

V

DD1VDD2

ADM2484E

GND1GND

2

Figure 28. Isolated Power Supply Circuit

) of the ADM2484E.

DD2

22µF

IN OUT SD ERR NR

+

ADP3330

GND

5V

+

10µF

PC BOARD LAYOUT

The ADM2484E isolated RS-485 transceiver requires no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 29). Bypass capacitors are conveniently connected between Pin 1 and Pin 2 for V

and between Pin 15 and Pin 16 for V

DD1

Best practice suggests the following:

• A capacitor value between 0.01 µF and 0.1 µF.

• A total lead length between both ends of the capacitor and

the input power supply pin that does not exceed 20 mm.

• Unless the ground pair on each package side is connected

close to the package, consider bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16.

V

GND

RxD

TxD

GND

DD1

1

RE DE

NC

1

ADM2484E

NC = NO CONNECT

Figure 29. Recommended PCB Layout

V GND A B Z Y NC GND

In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout so that any coupling that does occur equally affects all pins on a given component side.

06984-026

Failure to ensure this could cause voltage differentials between pins exceeding the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage.

DD2

.

DD2

2

06984-027

Rev. 0 | Page 14 of 16

ADM2484E

www.BDTIC.com/ADI

TYPICAL APPLICATIONS

Figure 30 and Figure 31 show typical applications of the ADM2484E in half-duplex and full-duplex RS-485 network configurations. Up to 256 transceivers can be connected to the RS-485 bus. To minimize reflections, the line must be terminated

V

CC

A

RxD

RE RE

DE

TxD

R

D

R1

B

R

T

Z

R2

Y

MAXIMUM NUMBER O F TRANSCEIVERS ON BUS = 256

ABZY

at the receiving end in its characteristic impedance, and stub lengths off the main line must be kept as short as possible. For half-duplex operation, this means that both ends of the line must be terminated, because either end can be the receiving end.

ADM2484EADM2484E

ABZY

A

B

R

T

Z

Y

R

RxD

DE

TxD

D

RxD

RE

DE

TxD

R

ADM2484E

RxD DE TxD

NOTES

1. R

IS EQUAL T O THE CHARACTERISTIC IMPEDANCE OF THE CABLE.

T

2. ISOL ATION NOT SHOWN.

D

ADM2484E

RE

R

RxD DE TxD

RE

D

Figure 30. ADM2484E Typical Half-Duplex RS-485 Network

V

MASTER SLAVE

R

D

DD

A

B

R1

R

T

R2

Z

Y

MAXIMUM NUMBER O F NODES = 256

Y

V

DD

Z

R1

B

R

T

A

R2

ADM2484E

SLAVE

ADM2484E

A B Z Y

R

D

A B Z Y

R

D

SLAVE

ADM2484E

06984-028

D

TxD

DE

RE

R

RxD

RxD TxDDE

RE

NOTES

1. R

IS EQUAL T O THE CHARACTERI STIC IMPEDANCE OF THE CABLE.

T

Figure 31. ADM2484E Typical Full -Duplex RS-485 Network

Rev. 0 | Page 15 of 16

RxD TxDDE

RE

06984-029

ADM2484E

C

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

BSC

9

7.60 (0.2992)

7.40 (0.2913)

8

10.65 (0.4193)

10.00 (0.3937)

2.65 (0.1043)

2.35 (0.0925)

SEATING PLANE

8° 0°

0.33 (0.0130)

0.20 (0.0079)

0 0

.

7

.

2

5

(

0

5

(

0

.

0

2

9

5

)

0

9

8

)

.

1.27 (0.0500)

0.40 (0.0157)

45°

032707-B

0.30 (0.0 118)

0.10 (0.0039)

OPLANARITY

0.10

16

1

1.27 (0.0500)

0.51 (0.0201)

0.31 (0.0122)

CONTROLL ING DIMENSIONS ARE IN MILLI METERS; I NCH DI M E NS IONS (IN PARENTHESES) ARE ROUNDED-OFF M ILLIM E TER EQUIVALENTS FOR REFERENCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DE SIGN.

COMPLIANT TO JEDEC STANDARDS MS-013-AA

Figure 32. 16-Lead Standard Small Outline Package [SOIC_W]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADM2484EBRWZ1 −40°C to +85°C 16-Lead Wide Body SOIC_W RW-16 ADM2484EBRWZ-REEL71 −40°C to +85°C 16-Lead Wide Body SOIC_W RW-16

1

Z = RoHS Compliant Part.

Rev. 0 | Page 16 of 16

Datasheet ADM2484E Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

TIMING SPECIFICATIONS

PACKAGE CHARACTERISTICS

REGULATORY INFORMATION (PENDING)

INSULATION AND SAFETY-RELATED SPECIFICATIONS

VDE 0884 INSULATION CHARACTERISTICS (PENDING)

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

SWITCHING CHARACTERISTICS

CIRCUIT DESCRIPTION

ELECTRICAL ISOLATION

iCoupler Technology

TRUTH TABLES

THERMAL SHUTDOWN

TRUE FAIL-SAFE RECEIVER INPUTS

MAGNETIC FIELD IMMUNITY

APPLICATIONS INFORMATION

ISOLATED POWER SUPPLY CIRCUIT

PC BOARD LAYOUT

TYPICAL APPLICATIONS

OUTLINE DIMENSIONS

ORDERING GUIDE