Datasheet ADM2483 Datasheet (Analog Devices)

Half-Duplex, iCoupler

®

FEATURES

RS-485 transceiver with electrical data isolation
Complies with ANSI TIA/EIA RS-485-A and ISO 8482: 1987(E)
500 kbps data rate
Slew rate-limited driver outputs
Low power operation: 2.5 mA max
Suitable for 5 V or 3 V operations (V
High common-mode transient immunity: >25 kV/μs
True fail-safe receiver inputs
Chatter-free power-up/power-down protection
256 nodes on bus
Thermal shutdown protection
Safety and regulatory approvals

UL recognition: 2500 V

for 1 minute per UL 1577

rms

CSA Component Acceptance Notice #5A
VDE Certificate of Conformity

DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000

= 560 V peak

V

IORM

Operating temperature range: −40°C to +85°C

DD1

)

Isolated RS-485 Transceiver

ADM2483

FUNCTIONAL BLOCK DIAGRAM

V

DD1

DE

TxD

PV

RxD

RE

GND

1

GALVANIC ISOLATION

Figure 1.

V

DD2

ADM2483

GND

2

A
B

04736-001

APPLICATIONS

Low power RS-485/RS-422 networks
Isolated interfaces
Building control networks
Multipoint data transmission systems

GENERAL DESCRIPTION

The ADM2483 differential bus transceiver is an integrated,
galvanically isolated component designed for bidirectional data
communication on balanced, multipoint bus transmission lines.
It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E).
Using Analog Devices’ iCoupler technology, the ADM2483
combines a 3-channel isolator, a three-state differential line
driver, and a differential input receiver into a single package.
The logic side of the device is powered with either a 5 V or 3 V
supply, and the bus side uses a 5 V supply only.

The ADM2483 is slew-limited to reduce reflections with
improperly terminated transmission lines. The controlled slew
rate limits the data rate to 500 kbps. The device’s input impedance
is 96 kΩ, allowing up to 256 transceivers on the bus. Its driver
has an active-high enable feature. The driver differential outputs

and receiver differential inputs are connected internally to form
a differential I/O port. When the driver is disabled or when

or V

V

DD1

= 0 V, this imposes minimal loading on the bus.

DD2

An active-high receiver disable feature, which causes the receive
output to enter a high impedance state, is provided as well.

The receiver inputs have a true fail-safe feature that ensures a
logic-high receiver output level when the inputs are open or
shorted. This guarantees that the receiver outputs are in a
known state before communication begins and at the point
when communication ends.

Current limiting and thermal shutdown features protect against
output short circuits and bus contention situations that might
cause excessive power dissipation. The part is fully specified
over the industrial temperature range and is available in a
16-lead, wide body SOIC package.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADM2483

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Package Characteristics ............................................................... 6

Regulatory Information............................................................... 6

Insulation and Safety-Related Specifications............................ 6

VDE 0884 Insulation Characteristics ........................................7

Pin Configuration and Function Descriptions............................. 8

Test Circuits....................................................................................... 9

Switching Characteristics ..............................................................10

Typical Performance Characteristics ........................................... 11

REVISION HISTORY

3/05—Rev. A to Rev. B

Change to Features........................................................................... 1

Change to Package Characteristics................................................. 6

Changes to Pin Function Descriptions.......................................... 8

Changes to Figure 9 and Figure 11............................................... 10

Change to Power_Valid Input Section......................................... 17

Changes to Figure 30...................................................................... 17

Changes to Ordering Guide.......................................................... 18

Circuit Description......................................................................... 14

Electrical Isolation...................................................................... 14

Truth Tables................................................................................. 15

Power-Up/Power-Down Characteristics................................. 15

Thermal Shutdown .................................................................... 15

True Fail-Safe Receiver Inputs.................................................. 15

Magnetic Field Immunity.......................................................... 15

Applications Information.............................................................. 17

Power_Valid Input ..................................................................... 17

Isolated Power Supply Circuit .................................................. 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

1/05—Rev. 0 to Rev. A

Changes to ESD maximum rating specification........................... 5

10/04—Revision 0: Initial Version

Rev. B | Page 2 of 20

ADM2483

SPECIFICATIONS

2.7 ≤ V

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

RECEIVER

POWER SUPPLY CURRENT

COMMON-MODE TRANSIENT IMMUNITY

1

Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation.

V

CM

common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

≤ 5.5 V, 4.75 V ≤ V

DD1

≤ 5.25 V, TA = T

DD2

MIN

to T

, unless otherwise noted.

MAX

Differential Outputs

Differential Output Voltage, VOD 5 V R = ∞, see Figure 3

2.0 5 V R = 50 Ω (RS-422), see Figure 3

1.5 5 V R = 27 Ω (RS-485), see Figure 3

1.5 5 V

= −7 V to +12 V, V

V

TST

≥ 4.75,

DD1

see Figure 4
∆ |VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 3
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 3
∆ |VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 3
Output Short-Circuit Current, V
Output Short-Circuit Current, V

= High −250 +250 mA −7 V ≤ V

OUT

= Low −250 +250 mA −7 V ≤ V

OUT

≤ +12 V

OUT

≤ +12 V

OUT

Logic Inputs

Input High Voltage 0.7 V
Input Low Voltage 0.25 V
CMOS Logic Input Current (TxD, DE, RE, PV)

V

DD1

V

DD1

−10 +0.01 +10 µA

TxD, DE, RE

TxD, DE, RE

TxD, DE, RE, PV = V

, PV
, PV

DD1

or 0 V

Differential Inputs

Differential Input Threshold Voltage, VTH −200 −125 −30 mV −7 V ≤ VCM ≤ +12 V
Input Hysteresis 20 mV −7 V ≤ VCM ≤ +12 V
Input Resistance (A, B) 96 150 kΩ −7 V ≤ VCM ≤ +12 V
Input Current (A, B)

0.125 mA VIN = +12 V

−0.1 mA VIN = −7 V

RxD Logic Output

Output High Voltage V
V
Output Low Voltage 0.1 V I

0.4 V I
Output Short-Circuit Current 7 85 mA V
Three-State Output Leakage Current ±1 µA 0.4 V ≤ V

Logic Side 2.5 mA

1.3 mA

− 0.1 V I

DD1

− 0.4 V

DD1

− 0.2 V I

DD1

= 20 µA, VA − VB = 0.2 V

OUT

= 4 mA, VA − VB = 0.2 V

OUT

= −20 µA, VA − VB = −0.2 V

OUT

= −4 mA, VA − VB = −0.2 V

OUT

= GND or VCC

OUT

OUT

4.5 V ≤ V

RE

2.7 V ≤ V

RE

DD1

= 0 V

DD1

= 0 V

≤ 2.4 V

≤ 5.5 V, outputs unloaded,

≤ 3.3 V, outputs unloaded,

Bus Side 2.0 mA Outputs unloaded, DE = 5 V

1.7 mA Outputs unloaded, DE = 0 V

1

25 kV/µs

TxD = V

or 0 V, VCM = 1 kV,

DD1

transient magnitude = 800 V

is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The

Rev. B | Page 3 of 20

ADM2483

TIMING SPECIFICATIONS

2.7 ≤ V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

RECEIVER

POWER VALID INPUT

≤ 5.5 V, 4.75 V ≤ V

DD1

≤ 5.25 V, TA = T

DD2

MIN

to T

, unless otherwise noted.

MAX

Maximum Data Rate 500 kbps
Propagation Delay, t
Skew, t

40 ns R

SKEW

Rise/Fall Time, tR, tF 200 600 ns R

, t

250 620 ns R

PLH

PHL

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9

LDIFF

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9

LDIFF

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9

LDIFF

Enable Time 1050 ns RL = 500 Ω, CL = 100 pF, see Figure 6 and Figure 11
Disable Time 1050 ns RL = 500 Ω, CL = 15 pF, see Figure 6 and Figure 11

Propagation Delay, t
Differential Skew, t

, t

400 1050 ns CL = 15 pF, see Figure 7 and Figure 10

PLH

PHL

250 ns CL = 15 pF, see Figure 7 and Figure 10

SKEW

Enable Time 25 70 ns RL = 1 kΩ, CL = 15 pF, see Figure 8 and Figure 12
Disable Time 40 70 ns RL = 1 kΩ, CL = 15 pF, see Figure 8 and Figure 12

Enable Time 1 2 µs
Disable Time 3 5 µs

Rev. B | Page 4 of 20

ADM2483

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.

Table 3.

Parameter Rating
V

−0.5 V to +7 V

DD1

V

−0.5 V to +6 V

DD2

Digital Input Voltage (DE, RE, TxD)
Digital Output Voltage

RxD −0.5 V to V
Driver Output/Receiver Input Voltage −9 V to +14 V
ESD Rating: Contact (Human Body

Model) (A, B Pins)
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −55°C to +150°C
Average Output Current per Pin −35 mA to +35 mA
θJA Thermal Impedance 73°C/W
Lead Temperature

Soldering (10 sec) 260°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−0.5 V to V

±2 kV

DD1

DD1

+ 0.5 V

+ 0.5 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada­tion or loss of functionality.

Rev. B | Page 5 of 20

ADM2483

PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output)1 R
Capacitance (Input-Output)1 C
Input Capacitance2 C
Input IC Junction-to-Case Thermal Resistance θ

Output IC Junction-to-Case Thermal Resistance θ

1

Device considered a 2-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADM2483 has been approved by the following organizations:

Table 5.

UL1 CSA VDE2

Recognized under 1577 component
recognition program

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL1577, each ADM2483 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).

2

In accordance with VDE 0884, each ADM2483 is proof tested by applying an insulation test voltage ≥1050 V

1012 Ω

I-O

3 pF f = 1 MHz

I-O

4 pF

I

33 °C/W

JCI

Thermocouple located at center of package
underside

28 °C/W

JCO

Thermocouple located at center of package
underside

Approved under CSA Component
Acceptance Notice #5A

for 1 sec (partial discharge detection limit = 5 pC).

PEAK

Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-01

Complies with DIN EN 60747-5-2

(VDE 0884 Part 2): 2003-01,

DIN EN 60950 (VDE 0805): 2001-12;

EN 60950:2000

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.45 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (Table 1 in DIN VDE 0110,1/89)

Measured from input terminals to output
terminals, shortest distance through air

Measured from input terminals to output
terminals, shortest distance along body

Rev. B | Page 6 of 20

ADM2483

VDE 0884 INSULATION CHARACTERISTICS

This isolator is suitable for basic electrical isolation only within this safety limit data. Maintenance of this safety data shall be ensured by
means of protective circuits.

An asterisk (*) on the physical package denotes VDE 0884 approval for 560 V peak working voltage.

Table 7.

Description Symbol Characteristic Unit

Installation Classification per DIN VDE 0110 for Rated Mains Voltage

≤150 V rms I to IV

≤300 V rms I to III

≤400 V rms I to II
Climatic Classification 40/85/21
Pollution Degree (Table 1 in DIN VDE 0110) 2
Maximum Working Insulation Voltage V
Input to Output test Voltage, Method b1 VPR 1050 V

V

× 1.875 = VPR, 100% Production Tested

IORM

tm = 1 sec, Partial Discharge <5 pC
Input-to-Output Test Voltage, Method a

(After Environmental Tests, Subgroup 1)

V

× 1.6 = VPR, tm = 60 sec, Partial Discharge <5 pC 896 V

IORM

(After Input and/or Safety Test, Subgroup 2/3)

V

× 1.2 = VPR, tm = 60 sec, Partial Discharge <5 pC VPR 672 V

IORM

Highest Allowable Overvoltage
(Transient Overvoltage, tTR = 10 sec) VTR 4000 V
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure. See Figure 23.)

Case Temperature TS 150 °C

Input Current I

Output Current I
Insulation Resistance at TS, VIO = 500 V RS >109 Ω

560 V

IORM

265 mA

S, INPUT

335 mA

S, OUTPUT

PEAK

PEAK

PEAK

PEAK

PEAK

Rev. B | Page 7 of 20

ADM2483

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

V

DD1

1

2

GND

1

RxD

3

ADM2483

4

RE

TOP VIEW

(Not to Scale)

DE

5

TxD

6
7

PV

1

8

GND

1

1

PIN 2 AND PIN 8 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND
PIN 9 AND PIN 15 ARE INTERNALLY CONNECTED.
EITHER OR BOTH MAY BE USED FOR GND

NC = NO CONNECT

16

V

DD2

1

15

GND

2

NC

14
13

B
A

12

NC

11
10

NC

1

9

GND

2

.

1

.

04736-002

2

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

Power Supply (Logic Side).

DD1

2, 8 GND1 Ground (Logic Side).
3 RxD

4

Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and

RE

Receiver Output Data. When enabled, if (A − B) ≥ −30 mV, then RxD = high. If (A − B) ≤ −200 mV, then
RxD = low. This is a tristate output when the receiver is disabled, that is, when RE

is driven high.

driving it high disables the receiver.
5 DE Driver Enable Input. Driving the input high enables the driver, and driving it low disables the driver.
6 TxD Transmit Data Input. Data to be transmitted by the driver is applied to this input.
7 PV Power_Valid. Used during power-up and power-down. See the Applications Information section.
9, 15 GND2 Ground (Bus Side).
10, 11, 14 NC No Connect.
12 A

Noninverting Driver Output/Receiver Input. When the driver is disabled, or when V

DD1

or V

DD2

is

powered down, Pin A is put into a high impedance state to avoid overloading the bus.
13 B

Inverting Driver Output/Receiver Input. When the driver is disabled, or when V

DD1

or V

is powered

DD2

down, Pin B is put into a high impedance state to avoid overloading the bus.
16 V

Power Supply (Bus Side).

DD2

Rev. B | Page 8 of 20

ADM2483

TEST CIRCUITS

V

CC

V

OD

R

R

Figure 3. Driver Voltage Measurement

375Ω

V

OD3

60Ω

375Ω

V

TEST

Figure 4. Driver Voltage Measurement

A

0V OR 3V

V

OC

04736-003

DE IN

DE

S1

B

Figure 6. Driver Enable/Disable

A

RE

B

04736-004

Figure 7. Receiver Propagation Delay

R

L

04736-007

S2

04736-006

C

L

V

OUT

V

OUT

C

L

A

R

B

LDIFF

C

L1

C

L2

Figure 5. Driver Propagation Delay

04736-005

V

+1.5V

–1.5V

RE IN

S1

RE

R

C

L

V

OUT

CC

L

S2

04736-008

Figure 8. Receiver Enable/Disable

Rev. B | Page 9 of 20

ADM2483

V

A

SWITCHING CHARACTERISTICS

DD1

V

A, B
V

RxD

0V

B

A

OH

OL

– B

0.5V

PLH

DD1

–

t

|

PHL

1/2VO

VO

90% POINT

10% POINT

0.5V

t

DD1

t

PLH

t

= |

t

SKEW

R

Figure 9. Driver Propagation Delay, Rise/Fall Timing

0V0V

t

PLH

t

= |

t

SKEW

PLH

t

PHL

–

t

|

PHL

Figure 10. Receiver Propagation Delay

t

PHL

1.5V1.5V

90% POINT

10% POINT

t

F

0.7V

DD1

04736-009

DE

A, B

A, B

0.5V

t

ZL

t

ZH

DD1

2.3V

2.3V

t

LZ

t

HZ

0.5V

DD1

VOL + 0.5V

VOH– 0.5V

0.3V

DD1

V

OL

V

OH

0V

04736-011

Figure 11. Driver Enable/Disable Timing

0.7V

DD1

t

t

0.5V

LZ

HZ

DD1

VOL + 0.5V

VOH– 0.5V

0.3V

DD1

V

OL

V

OH

04736-012

0.5V

RE

RxD

V

OH

RxD

V

OL

04736-010

0V

DD1

t

ZL

1.5V
O/P LOW

t

ZH

O/P HIGH

1.5V

Figure 12. Receiver Enable/Disable Timing

Rev. B | Page 10 of 20

ADM2483

TYPICAL PERFORMANCE CHARACTERISTICS

1.6
I

_RCVR_ENABLE @ 5.5V

1.4

1.2

1.0

0.8

0.6

SUPPLY CURRENT (mA)

0.4

0.2

0

DD1

I

_DE_ENABLE @ 5.5V

DD2

TEMPERATURE (°C)

Figure 13. Unloaded Supply Current vs. Temperature

8525–40

04736-038

0.32

0.30

0.28

0.26

0.24

OUTPUT VOLTAGE (V)

0.22

0.20
–40 80655035205–10–25

TEMPERATURE (°C)

Figure 16. Receiver Output Low Voltage vs. Temperature, I = –4mA

04736-031

120

100

80

60

40

OUTPUT CURRENT (mA)

20

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

OUTPUT VOLTAGE (V)

Figure 14. Output Current vs. Driver Output Low Voltage

–10

–30

–50

–70

OUTPUT CURRENT (mA)

–90

–110

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

OUTPUT VOLTAGE (V)

Figure 15. Output Current vs. Driver Output High Voltage

04736-014

04736-015

4.78

4.76

4.74

4.72

4.70

OUTPUT VOLTAGE (V)

4.68

4.66
–40 80655035205–10–25

TEMPERATURE (°C)

Figure 17. Receiver Output High Voltage vs. Temperature, I = 4 mA

90

80

70

60

50

40

30

20

DRIVER OUTPUT CURRENT (mA)

10

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

DIFFERENTIAL OUTPUT VOLTAGE (V)

Figure 18. Driver Output Current vs. Differential Output Voltage

04736-032

04736-013

Rev. B | Page 11 of 20

ADM2483

460

440

420

t

P_BLH

V

DD1

= V

@

= 5.0V

DD2

t

P_AHL

V

DD1

= V

@

= 5.0V

DD2

1

400

TIME (ns)

380

360

340

t

P_BHL

V

DD1

@

= V

= 5.0V

DD2

TEMPERATURE (°C)

t

P_ALH

V

DD1

= V

@

Figure 19. Driver Propagation Delay vs. Temperature

800

700

600

500

400

TIME (ns)

300

200

100

0

R

PROP

CVR

= V

HL/V

DD1

DD2

PROP

R

CVR

= V

LH/V

DD1

DD2

TEMPERATURE (°C)

= 5.0V

= 5.0V

Figure 20. Receiver Propagation Delay vs. Temperature

DD2

= 5.0V

2

8525–40

04736-034

4

CH1 5.00V CH2 1.00V
CH3 1.00V CH4 5.00V

M200ns A CH1 3.10V

T 1.33600µs

04736-022

Figure 21. Driver/Receiver Propagation Delay High to Low

1

2

8525–40

04736-035

4

CH1 5.00V CH2 1.00V
CH3 1.00V CH4 5.00V

M200ns A CH1 3.10V

T 360.000ns

04736-023

Figure 22. Driver/Receiver Propagation Delay Low to High

Rev. B | Page 12 of 20

ADM2483

350

35

300

250

200

150

100

SAFETY-LIMITING CURRENT (mA)

50

0

0 50 100 150 200

BUS SIDE

LOGIC SIDE

CASE TEMPERATURE (°C)

04736-024

Figure 23. Thermal Derating Curve, Dependence of Safety-Limiting Values

with Case Temperature per VDE 0884

0

–5

–10

–15

30

25

20

15

10

OUTPUT CURRENT (mA)

5

0

OUTPUT VOLTAGE (V)

04736-037

2.252.001.751.501.251.000.750.500.250

Figure 25. Output Current vs. Receiver Output Low Voltage

–20

OUTPUT CURRENT (mA)

–25

–30

OUTPUT VOLTAGE (V)

Figure 24. Output Current vs. Receiver Output High Voltage

04736-036

5.03.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8

Rev. B | Page 13 of 20

ADM2483

CIRCUIT DESCRIPTION

ELECTRICAL ISOLATION

In the ADM2483, electrical isolation is implemented on the
logic side of the interface. Therefore, the part has two main
sections: a digital isolation section and a transceiver section (see
Figure 26). Driver input and data enable signals, applied to the
TxD and DE pins, respectively, and referenced to logic ground

), are coupled across an isolation barrier to appear at the

(GND

1

transceiver section referenced to isolated ground (GND
Similarly, the receiver output, referenced to isolated ground in
the transceiver section, is coupled across the isolation barrier to
appear at the RxD pin referenced to logic ground.

V

DD1

).

2

ISOLATION

BARRIER

iCoupler Technology

The digital signals are transmitted across the isolation barrier
using iCoupler technology. This technique uses chip-scale
transformer windings to couple the digital signals magnetically
from one side of the barrier to the other. Digital inputs are
encoded into waveforms that are capable of exciting the
primary transformer winding. At the secondary winding, the
induced waveforms are then decoded into the binary value that
was originally transmitted.

V

DD2

TxD

DE

RxD

RE

DECODEENCODE

DECODEENCODE

DECODEENCODE

DIGITAL ISOLATION TRANSCEIVER

GND

1

Figure 26. ADM2483 Digital Isolation and Transceiver Sections

GND

D

R

2

A
B

04736-025

Rev. B | Page 14 of 20

ADM2483

=

β

N

TRUTH TABLES

The following truth tables use these abbreviations:

Letter Description

H High level
L Low level
X Irrelevant
Z High impedance (off)
NC Disconnected

Table 9. Transmitting

Supply Status Inputs Outputs

V

V

DD1

On On H H H L
On On H L L H
On On L X Z Z
On Off X X Z Z
Off On X X Z Z
Off Off X X Z Z

Table 10. Receiving

Supply Status Inputs Outputs

V

V

DD1

On On >−0.03 L or NC H
On On <−0.2 L or NC L

On On
On On Inputs open L or NC H
On On X H Z
On Off X L or NC H
Off On X L or NC H
Off Off X L or NC L

DE TxD A B

DD2

A − B (V)

DD2

RE

RxD

−0.2 < A − B <

−0.03 L or NC Indeterminate

THERMAL SHUTDOWN

The ADM2483 contains thermal shutdown circuitry that
protects the part from excessive power dissipation during fault
conditions. Shorting the driver outputs to a low impedance
source can result in high driver currents. The thermal sensing
circuitry detects the increase in die temperature under this
condition and disables the driver outputs. This circuitry is
designed to disable the driver outputs when a die temperature
of 150°C is reached. As the device cools, the drivers are re-enabled
at a temperature of 140°C.

TRUE FAIL-SAFE RECEIVER INPUTS

The receiver inputs have a true fail-safe feature, which ensures
that the receiver output is high when the inputs are open or
shorted. During line-idle conditions, when no driver on the bus
is enabled, the voltage across a terminating resistance at the
receiver input decays to 0 V. With traditional transceivers,
receiver input thresholds specified between −200 mV and
+200 mV mean that external bias resistors are required on the
A and B pins to ensure that the receiver outputs are in a known
state. The true fail-safe receiver input feature eliminates the
need for bias resistors by specifying the receiver input threshold
between −30 mV and −200 mV. The guaranteed negative
threshold means that when the voltage between A and B decays
to 0 V, the receiver output is guaranteed to be high.

MAGNETIC FIELD IMMUNITY

Because iCouplers use a coreless technology, no magnetic
components are present, and the problem of magnetic
saturation of the core material does not exist. Therefore,
iCouplers have essentially infinite dc field immunity. The
analysis that follows defines the conditions under which this
might occur. The ADM2483’s 3 V operating condition is
examined because it represents the most susceptible mode of
operation.

POWER-UP/POWER-DOWN CHARACTERISTICS

The power-up/power-down characteristics of the ADM2483 are
in accordance with the supply thresholds shown in Table 11.
Upon power-up, the ADM2483 output signals (A, B, and RxD)
reach their correct state once both supplies exceed their
thresholds. Upon power-down, the ADM2483 output signals
retain their correct state until at least one of the supplies drops
below its power-down threshold. When the V
threshold is crossed, the ADM2483 output signals reach their
unpowered states within 4 µs.

Table 11. Power-Up/Power-Down Thresholds

Supply Transition Threshold (V)

V

Power-up 2.0

DD1

V

Power-down 1.0

DD1

V

Power-up 3.3

DD2

V

Power-down 2.4

DD2

power-down

DD1

The limitation on the iCoupler’s ac magnetic field immunity is
set by the condition in which the induced error voltage in the
receiving coil (the bottom coil in this case) is made sufficiently
large, either to falsely set or reset the decoder. The voltage
induced across the bottom coil is given by

d

β−

⎞

⎛

V ∑

=

⎜

dt

⎝

2

Nn ,...,2,1

;π

r

⎟

n

⎠

where if the pulses at the transformer output are greater than

1.0 V in amplitude:
= magnetic flux density (gauss)
= number of turns in receiving coil

r

= radius of nth turn in receiving coil (cm)

n

The decoder has a sensing threshold of about 0.5 V; therefore,
there is a 0.5 V margin in which induced voltages can be
tolerated.

Rev. B | Page 15 of 20

ADM2483

Given the geometry of the receiving coil and an imposed
requirement that the induced voltage is, at most, 50% of the

0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated, as shown in Figure 27.

100.000

1000.00

DISTANCE = 1m

100.00

DISTANCE = 5mm

10.00

10.000

1.000

0.100

FLUX DENSITY (kGAUSS)

0.010

MAXIMUM ALLOWABLE MAGNETIC

0.001
1k 10k 100k 1M 10M 100M

MAGNETIC FIELD FREQUENCY (Hz)

04736-027

Figure 27. Maximum Allowable External Magnetic Flux Density

For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kGauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse and
is the worst-case polarity, it reduces the received pulse from
>1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold
of the decoder.

These magnetic flux density values are shown in Figure 28,
using more familiar quantities such as maximum allowable
current flow, at given distances away from the ADM2483
transformers.

1.00

0.10

MAXIMUM ALLOWABLE CURRENT (kA)

0.01

DISTANCE = 100mm

1k 10k 100k 1M 10M 100M

MAGNETIC FIELD FREQUENCY (Hz)

Figure 28. Maximum Allowable Current for Various

Current-to-ADM2483 Spacings

At combinations of strong magnetic field and high frequency,
any loops formed by printed circuit board traces could induce
large enough error voltages to trigger the thresholds of
succeeding circuitry. To avoid this possibility, care should be
taken in the layout of such traces.

04736-028

Rev. B | Page 16 of 20

ADM2483

V

APPLICATIONS INFORMATION

POWER_VALID INPUT

To avoid chatter on the A and B outputs caused by slow power­up and power-down transients on V
ADM2483 features a power_valid (PV) digital input. This pin
should be driven low until V

DD1

greater than 2.0 V, the pin should be driven high. Conversely,
upon power-down, the PV should be driven low before V
reaches 2.0 V.

The power_valid input can be driven, for example, by the
output of a system reset circuit such as the ADM809Z, which
has a threshold voltage of 2.32 V.

DD1

ADM809Z

2.0V

V

DD1

RESET

2.32V

(>100 µs/V), the

DD1

exceeds 2.0 V. When V

V

DD1

ADM2483

PV

GND

1

2.32V

2.0V

DD1

is

DD1

ISOLATED POWER SUPPLY CIRCUIT

The ADM2483 requires isolated power capable of 5 V at
100 mA to be supplied between the V
suitable integrated power supply is available, a discrete circuit,
such as the one in Figure 30, can be used. A center-tapped
transformer provides electrical isolation. The primary winding
is excited with a pair of square waveforms that are 180° out of
phase with each other. A pair of Schottky diodes and a
smoothing capacitor are used to create a rectified signal from
the secondary winding. The ADP667 linear voltage regulator
provides a regulated power supply to the ADM2483’s bus-side
circuitry.

To create the pair of square waves, a D-type flip-flop with
complementary Q/

outputs is used. The flip-flop can be

Q

connected so that output Q follows the clock input signal. If no
local clock signal is available, a simple digital oscillator can be
implemented with a hex-inverting Schmitt trigger and a resistor
and capacitor. In this case, values of 3.9 kΩ and 1 nF generate a
364 kHz square wave. A pair of discrete NMOS transistors,
switched by the Q/

flip-flop outputs, conduct current through

Q

the center tap of the primary transformer, winding in an
alternating fashion.

and GND2 pins. If no

DD2

RESET

POR

04736-029

t

Figure 29. Driving PV with ADM809Z

V

1nF

V

CC

3.9kΩ

100nF

74HC14

CC

100nF

PR CLR

DQ

74HC74A

CLK Q

Figure 30. Isolated Power Supply Circuit

BS107A

BS107A

ISOLATION

BARRIER

V

CC

78253

SD103C

SD103C

IN OUT

22µF

SET SHDNGND

ADP667

V

CC

V

DD1

ADM2483

GND

1

5V

V

GND

DD2

2

04736-030

Rev. B | Page 17 of 20

ADM2483

OUTLINE DIMENSIONS

10.50 (0.4134)

10.10 (0.3976)

16

1

1.27 (0.0500)
BSC

0.30 (0.0118)

0.10 (0.0039)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

0.51 (0.0201)

0.31 (0.0122)

COMPLIANT TO JEDEC STANDARDS MS-013AA

9

7.60 (0.2992)

7.40 (0.2913)

8

2.65 (0.1043)

2.35 (0.0925)

SEATING
PLANE

10.65 (0.4193)

10.00 (0.3937)

0.33 (0.0130)

0.20 (0.0079)

0.75 (0.0295)

0.25 (0.0098)

8°
0°

× 45°

1.27 (0.0500)

0.40 (0.0157)

Figure 31. 16-Lead Standard Small Outline Package [SOIC]

Wide Body

(RW-16)

Dimensions shown in millimeters and (inches)

ORDERING GUIDE

Model Data Rate (kbps) Temperature Range Package Description Package Option

ADM2483BRW 500 −40°C to +85°C 16-Lead, Wide Body SOIC RW-16
ADM2483BRW-REEL
ADM2483BRWZ2 500 −40°C to +85°C 16-Lead, Wide Body SOIC RW-16
ADM2483BRWZ-REEL

1

A -REEL suffix designates a 13-inch (1,000 units) tape-and-reel option.

2

Z = Pb-free part.

1

500 −40°C to +85°C 16-Lead, Wide Body SOIC RW-16

1, 2

500 −40°C to +85°C 16-Lead, Wide Body SOIC RW-16

Rev. B | Page 18 of 20

ADM2483

NOTES

Rev. B | Page 19 of 20

ADM2483

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04736–0–3/05(B)

Rev. B | Page 20 of 20