ANALOG DEVICES ADM2483 Service Manual

Half-Duplex, iCoupler

www.BDTIC.com/ADI

®

FEATURES

RS-485 transceiver with electrical data isolation
Complies with ANSI TIA/EIA RS-485-A and ISO 8482: 1987(E)
500 kbps data rate
Slew rate-limited driver outputs
Low power operation: 2.5 mA max
Suitable for 5 V or 3 V operations (V
High common-mode transient immunity: >25 kV/μs
True fail-safe receiver inputs
Chatter-free power-up/power-down protection
256 nodes on bus
Thermal shutdown protection
Safety and regulatory approvals

UL recognition: 2500 V

for 1 minute per UL 1577

rms

CSA Component Acceptance Notice #5A
VDE Certificate of Conformity

DIN EN 60747-5-2 (VDE 0884 Rev. 2): 2003-01
DIN EN 60950 (VDE 0805): 2001-12; EN 60950: 2000

= 560 V peak

V

IORM

Operating temperature range: −40°C to +85°C

DD1

)

Isolated RS-485 Transceiver

ADM2483

FUNCTIONAL BLOCK DIAGRAM

V

DD1

DE

TxD

PV

RxD

RE

GND

1

GALVANIC ISOLATION

Figure 1.

V

DD2

ADM2483

GND

2

A
B

04736-001

APPLICATIONS

Low power RS-485/RS-422 networks
Isolated interfaces
Building control networks
Multipoint data transmission systems

GENERAL DESCRIPTION

The ADM2483 differential bus transceiver is an integrated,
galvanically isolated component designed for bidirectional data
communication on balanced, multipoint bus transmission lines.
It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E).
Using Analog Devices’ iCoupler technology, the ADM2483
combines a 3-channel isolator, a three-state differential line
driver, and a differential input receiver into a single package.
The logic side of the device is powered with either a 5 V or 3 V
supply, and the bus side uses a 5 V supply only.

The ADM2483 is slew-limited to reduce reflections with
improperly terminated transmission lines. The controlled slew
rate limits the data rate to 500 kbps. The device’s input impedance
is 96 kΩ, allowing up to 256 transceivers on the bus. Its driver
has an active-high enable feature. The driver differential outputs

and receiver differential inputs are connected internally to form
a differential I/O port. When the driver is disabled or when
V

DD1

or V

= 0 V, this imposes minimal loading on the bus.

DD2

An active-high receiver disable feature, which causes the receive
output to enter a high impedance state, is provided as well.

The receiver inputs have a true fail-safe feature that ensures a
logic-high receiver output level when the inputs are open or
shorted. This guarantees that the receiver outputs are in a
known state before communication begins and at the point
when communication ends.

Current limiting and thermal shutdown features protect against
output short circuits and bus contention situations that might
cause excessive power dissipation. The part is fully specified
over the industrial temperature range and is available in a
16-lead, wide body SOIC package.

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

ADM2483

www.BDTIC.com/ADI

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Specifications....................................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Package Characteristics ............................................................... 6

Regulatory Information............................................................... 6

Insulation and Safety-Related Specifications............................ 6

VDE 0884 Insulation Characteristics ........................................ 7

Pin Configuration and Function Descriptions............................. 8

Test Circuits....................................................................................... 9

Switching Characteristics ..............................................................10

Typical Performance Characteristics ........................................... 11

REVISION HISTORY

3/05—Rev. A to Rev. B

Change to Features........................................................................... 1

Change to Package Characteristics................................................. 6

Changes to Pin Function Descriptions.......................................... 8

Changes to Figure 9 and Figure 11............................................... 10

Change to Power_Valid Input Section......................................... 17

Changes to Figure 30...................................................................... 17

Changes to Ordering Guide.......................................................... 18

Circuit Description......................................................................... 14

Electrical Isolation...................................................................... 14

Truth Tables................................................................................. 15

Power-Up/Power-Down Characteristics................................. 15

Thermal Shutdown .................................................................... 15

True Fail-Safe Receiver Inputs.................................................. 15

Magnetic Field Immunity.......................................................... 15

Applications Information.............................................................. 17

Power_Valid Input ..................................................................... 17

Isolated Power Supply Circuit .................................................. 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

1/05—Rev. 0 to Rev. A

Changes to ESD maximum rating specification........................... 5

10/04—Revision 0: Initial Version

Rev. B | Page 2 of 20

ADM2483

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SPECIFICATIONS

2.7 ≤ V

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

RECEIVER

POWER SUPPLY CURRENT

COMMON-MODE TRANSIENT IMMUNITY

1

Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation.

V

CM

common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.

≤ 5.5 V, 4.75 V ≤ V

DD1

≤ 5.25 V, TA = T

DD2

MIN

to T

, unless otherwise noted.

MAX

Differential Outputs

Differential Output Voltage, VOD 5 V R = ∞, see Figure 3

2.0 5 V R = 50 Ω (RS-422), see Figure 3

1.5 5 V R = 27 Ω (RS-485), see Figure 3

1.5 5 V

= −7 V to +12 V, V

V

TST

≥ 4.75,

DD1

see Figure 4
∆ |VOD| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 3
Common-Mode Output Voltage, VOC 3 V R = 27 Ω or 50 Ω, see Figure 3
∆ |VOC| for Complementary Output States 0.2 V R = 27 Ω or 50 Ω, see Figure 3
Output Short-Circuit Current, V
Output Short-Circuit Current, V

= High −250 +250 mA −7 V ≤ V

OUT

= Low −250 +250 mA −7 V ≤ V

OUT

≤ +12 V

OUT

≤ +12 V

OUT

Logic Inputs

Input High Voltage 0.7 V
Input Low Voltage 0.25 V
CMOS Logic Input Current (TxD, DE, RE, PV)

V

DD1

V

DD1

−10 +0.01 +10 µA

TxD, DE, RE

TxD, DE, RE

TxD, DE, RE, PV = V

, PV
, PV

DD1

or 0 V

Differential Inputs

Differential Input Threshold Voltage, VTH −200 −125 −30 mV −7 V ≤ VCM ≤ +12 V
Input Hysteresis 20 mV −7 V ≤ VCM ≤ +12 V
Input Resistance (A, B) 96 150 kΩ −7 V ≤ VCM ≤ +12 V
Input Current (A, B)

0.125 mA VIN = +12 V

−0.1 mA VIN = −7 V

RxD Logic Output

Output High Voltage V
V
Output Low Voltage 0.1 V I

0.4 V I
Output Short-Circuit Current 7 85 mA V
Three-State Output Leakage Current ±1 µA 0.4 V ≤ V

Logic Side 2.5 mA

1.3 mA

− 0.1 V I

DD1

− 0.4 V

DD1

− 0.2 V I

DD1

= 20 µA, VA − VB = 0.2 V

OUT

= 4 mA, VA − VB = 0.2 V

OUT

= −20 µA, VA − VB = −0.2 V

OUT

= −4 mA, VA − VB = −0.2 V

OUT

= GND or VCC

OUT

OUT

4.5 V ≤ V

RE

2.7 V ≤ V

RE

DD1

= 0 V

DD1

= 0 V

≤ 2.4 V

≤ 5.5 V, outputs unloaded,

≤ 3.3 V, outputs unloaded,

Bus Side 2.0 mA Outputs unloaded, DE = 5 V

1.7 mA Outputs unloaded, DE = 0 V

1

25 kV/µs

TxD = V

or 0 V, VCM = 1 kV,

DD1

transient magnitude = 800 V

is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The

Rev. B | Page 3 of 20

ADM2483

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TIMING SPECIFICATIONS

2.7 ≤ V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

DRIVER

RECEIVER

POWER VALID INPUT

≤ 5.5 V, 4.75 V ≤ V

DD1

≤ 5.25 V, TA = T

DD2

MIN

to T

, unless otherwise noted.

MAX

Maximum Data Rate 500 kbps
Propagation Delay, t
Skew, t

40 ns R

SKEW

Rise/Fall Time, tR, tF 200 600 ns R

, t

250 620 ns R

PLH

PHL

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9

LDIFF

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9

LDIFF

= 54 Ω, CL1 = CL2 = 100 pF, see Figure 5 and Figure 9

LDIFF

Enable Time 1050 ns RL = 500 Ω, CL = 100 pF, see Figure 6 and Figure 11
Disable Time 1050 ns RL = 500 Ω, CL = 15 pF, see Figure 6 and Figure 11

Propagation Delay, t
Differential Skew, t

, t

400 1050 ns CL = 15 pF, see Figure 7 and Figure 10

PLH

PHL

250 ns CL = 15 pF, see Figure 7 and Figure 10

SKEW

Enable Time 25 70 ns RL = 1 kΩ, CL = 15 pF, see Figure 8 and Figure 12
Disable Time 40 70 ns RL = 1 kΩ, CL = 15 pF, see Figure 8 and Figure 12

Enable Time 1 2 µs
Disable Time 3 5 µs

Rev. B | Page 4 of 20

ADM2483

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.

Table 3.

Parameter Rating
V

−0.5 V to +7 V

DD1

V

−0.5 V to +6 V

DD2

Digital Input Voltage (DE, RE, TxD)
Digital Output Voltage

RxD −0.5 V to V
Driver Output/Receiver Input Voltage −9 V to +14 V
ESD Rating: Contact (Human Body

Model) (A, B Pins)
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −55°C to +150°C
Average Output Current per Pin −35 mA to +35 mA
θJA Thermal Impedance 73°C/W
Lead Temperature

Soldering (10 sec) 260°C

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

−0.5 V to V

±2 kV

DD1

DD1

+ 0.5 V

+ 0.5 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degrada­tion or loss of functionality.

Rev. B | Page 5 of 20

ADM2483

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PACKAGE CHARACTERISTICS

Table 4.

Parameter Symbol Min Typ Max Unit Test Conditions

Resistance (Input-Output)1 R
Capacitance (Input-Output)1 C
Input Capacitance2 C
Input IC Junction-to-Case Thermal Resistance θ

Output IC Junction-to-Case Thermal Resistance θ

1

Device considered a 2-terminal device: Pins 1, 2, 3, 4, 5, 6, 7, and 8 shorted together, and Pins 9, 10, 11, 12, 13, 14, 15, and 16 shorted together.

2

Input capacitance is from any input data pin to ground.

REGULATORY INFORMATION

The ADM2483 has been approved by the following organizations:

Table 5.

UL1 CSA VDE2

Recognized under 1577 component
recognition program

File E214100 File 205078 File 2471900-4880-0001

1

In accordance with UL1577, each ADM2483 is proof tested by applying an insulation test voltage ≥3000 V rms for 1 sec (current leakage detection limit = 5 µA).

2

In accordance with VDE 0884, each ADM2483 is proof tested by applying an insulation test voltage ≥1050 V

1012 Ω

I-O

3 pF f = 1 MHz

I-O

4 pF

I

33 °C/W

JCI

Thermocouple located at center of package
underside

28 °C/W

JCO

Thermocouple located at center of package
underside

Approved under CSA Component
Acceptance Notice #5A

for 1 sec (partial discharge detection limit = 5 pC).

PEAK

Certified according to DIN EN 60747-5-2
(VDE 0884 Part 2): 2003-01

Complies with DIN EN 60747-5-2

(VDE 0884 Part 2): 2003-01,

DIN EN 60950 (VDE 0805): 2001-12;

EN 60950:2000

INSULATION AND SAFETY-RELATED SPECIFICATIONS

Table 6.

Parameter Symbol Value Unit Conditions

Rated Dielectric Insulation Voltage 2500 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 7.45 min mm

Minimum External Tracking (Creepage) L(I02) 8.1 min mm

Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (Table 1 in DIN VDE 0110,1/89)

Measured from input terminals to output
terminals, shortest distance through air

Measured from input terminals to output
terminals, shortest distance along body

Rev. B | Page 6 of 20