Isolated RS-485 Transceiver
ADM2481
Rev. A
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ADM2481
DE
GALVANIC ISOLA
TION
TxD
RxD
A
B
RE
GND
1
GND
2
V
DD1
V
DD2
08920-001
Data Sheet
FEATURES
RS-485 transceiver with electrical data isolation
Complies with ANSI TIA/EIA-485-A and ISO 8482: 1987(E)
500 kbps data rate
Slew rate-limited driver outputs
Low power operation: 2.5 mA maximum
Suitable for 5 V or 3.3 V operations (V
High common-mode transient immunity: >25 kV/μs
True fail-safe receiver inputs
Chatter-free power-up/power-down protection
256 nodes on bus
Thermal shutdown protection
Safety and regulatory approvals
UL recognition: 2500 V rms for 1 minute per
UL 1577
VDE certificates of conformity
DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12
V
= 560 V peak
IORM
Operating temperature range: −40°C to +85°C
DD1
)
Half-Duplex, iCoupler
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
APPLICATIONS
Low power RS-485/RS-422 networks
Isolated interfaces
Building control networks
Multipoint data transmission systems
GENERAL DESCRIPTION
The ADM2481 differential bus transceiver is an integrated,
galvanically isolated component designed for bidirectional data
communication on balanced, multipoint bus transmission lines.
It complies with ANSI EIA/TIA-485-A and ISO 8482: 1987(E).
Using iCoupler® technology from Analog Devices, Inc., the
ADM2481 combines a 3-channel isolator, a three-state differential line driver, and a differential input receiver into a single
package. The logic side of the device is powered with either a
5 V or 3 V supply, and the bus side uses a 5 V supply only.
The ADM2481 is slew-limited to reduce reflections with improperly terminated transmission lines. The controlled slew rate
limits the data rate to 500 kbps. The input impedance of the
device is 96 kΩ, allowing up to 256 transceivers on the bus. Its
driver has an active-high enable feature. The driver differential
outputs and receiver differential inputs are connected internally
to form a differential I/O port. When the driver is disabled or
when V
DD1
or V
= 0 V, this imposes minimal loading on
DD2
the bus. An active-high receiver disable feature, which causes
the receiver output to enter a high impedance state, is provided
as well.
The receiver inputs have a true fail-safe feature that ensures a
logic-high receiver output level when the inputs are open or
shorted. This guarantees that the receiver outputs are in a
known state before communication begins and at the point
when communication ends.
Current limiting and thermal shutdown features protect against
output short circuits and bus contention situations that might
cause excessive power dissipation. The part is fully specified
over the industrial temperature range of −40°C to +85°C and is
available in a 16-lead, wide body SOIC package.
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license i s granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
ADM2481 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 4
Package Characteristics ............................................................... 4
Regulatory Information ............................................................... 4
Insulation and Safety-Related Specifications ............................ 4
VDE 0884 Insulation Characteristics ........................................ 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ..............................................8
Test Circuits ..................................................................................... 11
Switching Characteristics .............................................................. 12
Circuit Description......................................................................... 13
Electrical Isolation ...................................................................... 13
Truth Tables................................................................................. 14
Thermal Shutdown .................................................................... 14
True Fai l -Safe Receiver Inputs .................................................. 14
Magnetic Field Immunity.......................................................... 14
Applications Information .............................................................. 16
Printed Circuit Board (PCB) Layout ....................................... 16
Isolated Power Supply Circuit .................................................. 16
Outline Dimensions ....................................................................... 17
Ordering Guide .......................................................................... 17
REVISION HISTORY
6/12—Rev. 0 to Rev. A
Updated Safety and Regulatory Approvals (Throughout) .......... 1
Updated Outline Dimensions ....................................................... 17
Changes to Ordering Guide .......................................................... 17
7/10—Revision 0: Initial Version
Rev. A | Page 2 of 20
Data Sheet ADM2481
SPECIFICATIONS
3.0 V ≤ V
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Differential Outputs
Logic Inputs
RECEIVER
Differential Inputs
RxD Logic Output
POWER SUPPLY CURRENT
Logic Side I
1.3 mA 3.0 V ≤ V
Bus Side I
1.7 mA Outputs unloaded, DE = 0 V
COMMON-MODE TRANSIENT IMMUNITY
1
Common-mode transient immunity is the maximum common-mode voltage slew rate that can be sustained while maintaining specification-compliant operation.
is the common-mode potential difference between the logic and bus sides. The transient magnitude is the range over which the common mode is slewed. The
V
CM
common-mode voltage slew rates apply to both rising and falling common-mode voltage edges.
≤ 5.5 V, 4.75 V ≤ V
DD1
≤ 5.25 V, TA = T
DD2
MIN
to T
, unless otherwise noted.
MAX
Differential Output Voltage 5 V RL = ∞, see Figure 16
V
V
V
2.0 5 V RL = 50 Ω (RS-422), see Figure 16
OD
1.5 5 V RL = 27 Ω (RS-485), see Figure 16
OD
1.5 5 V V
OD3
= −7 V to +12 V, V
TEST
≥ 4.75,
DD1
see Figure 17
Δ |VOD| for Complementary Output States 0.2 V RL = 27 Ω or 50 Ω, see Figure 16
Common-Mode Output Voltage VOC 3 V RL = 27 Ω or 50 Ω, see Figure 16
Δ |VOC| for Complementary Output States 0.2 V RL = 27 Ω or 50 Ω, see Figure 16
Output Short-Circuit Current, ISC
V
= High −250 +250 mA −7 V ≤ V
OUT
V
= Low −250 +250 mA −7 V ≤ V
OUT
Input High Voltage VIH 0.7 V
Input Low Voltage VIL 0.25 V
−10 +0.01 +10 μA
CMOS Logic Input Current (TxD, DE, RE)
I
I
V
DD1
V
DD1
TxD, DE,
TxD, DE,
TxD, DE,
≤ +12 V
OUT
≤ +12 V
OUT
RE
RE
RE
= V
DD1
or 0 V
Differential Input Threshold Voltage VTH −200 −125 −30 mV −7 V ≤ VCM ≤ +12 V
Input Hysteresis V
20 mV −7 V ≤ VCM ≤ +12 V
HYS
Input Resistance (A, B) 96 150 kΩ −7 V ≤ VCM ≤ +12 V
Input Current (A, B)
Output High Voltage VOH V
V
Output Low Voltage VOL 0.1 V I
0.4 V I
Output Short-Circuit Current ISC 7 85 mA V
Three-State Output Leakage Current ±1 μA 0.4 V ≤ V
0.125 mA VIN = 12 V
−0.1 mA VIN = −7 V
− 0.1 V I
DD1
− 0.4 V
DD1
1
2.5 mA 4.5 V ≤ V
DD1
2.0 mA Outputs unloaded, DE = 5 V
DD2
VCM 25 kV/μs TxD = V
− 0.2 V I
DD1
= 20 μA, VA − VB = 0.2 V
OUT
= 4 mA, VA − VB = 0.2 V
OUT
= −20 μA, VA − VB = −0.2 V
OUT
= −4 mA, VA − VB = −0.2 V
OUT
= GND or VCC
OUT
≤ 2.4 V
OUT
≤ 5.5 V, outputs
DD1
RE
unloaded,
unloaded,
= 0 V
≤ 3.6 V, outputs
DD1
RE
= 0 V
or 0 V, VCM = 1 kV,
DD1
transient magnitude = 800 V
Rev. A | Page 3 of 20
ADM2481 Data Sheet
Propagation Delay
t
, t
400 1050
ns
CL = 15 pF, see Figure 20 and Figure 23
Parameter
Symbol
Value
Unit
Conditions
Rated Dielectric Insulation Voltage
2500
V rms
1-minute duration
TIMING SPECIFICATIONS
3.0 V ≤ V
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
DRIVER
Maximum Data Rate 500 kbps
Propagation Delay t
Skew t
Rise/Fall Time tR, tF 200 600 ns RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22
Enable Time 1050 ns RL = 500 Ω, CL = 100 pF, see Figure 19 and Figure 24
Disable Time 1050 ns RL = 500 Ω, CL = 15 pF, see Figure 19 and Figure 24
RECEIVER
Differential Skew t
Enable Time 25 70 ns RL = 1 kΩ, CL = 15 pF, see Figure 21 and Figure 25
Disable Time 40 70 ns RL = 1 kΩ, CL = 15 pF, see Figure 21 and Figure 25
PACKAGE CHARACTERISTICS
Table 3.
Parameter Symbol Min Typ Max Unit Test Conditions
Resistance (Input-Output)1 R
Capacitance (Input-Output)1 C
Input Capacitance2 CI 4 pF
1
Device is considered a 2-terminal device: Pin 1 to Pin 8 are shorted together, and Pin 9 to Pin16 are shorted together.
2
Input capacitance is from any input data pin to ground.
≤ 5.5 V, 4.75 V ≤ V
DD1
≤ 5.25 V, TA = T
DD2
, t
250 620 ns RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22
PLH
PHL
40 ns RL = 54 Ω, CL1 = CL2 = 100 pF, see Figure 18 and Figure 22
SKEW
PLH
PHL
250 ns CL = 15 pF, see Figure 20 and Figure 23
SKEW
1012 Ω
I-O
3 pF f = 1 MHz
I-O
MIN
to T
, unless otherwise noted.
MAX
REGULATORY INFORMATION
Table 4. ADM2481 Approvals
Organization Approval Type Notes
UL Recognized under the Component Recognition
Program of Underwriters Laboratories, Inc.
In accordance with UL 1577, each ADM2481 is proof tested by
applying an insulation test voltage of ≥ 3000 V rms for 1 second
(current leakage detection limit = 5 µA).
VDE Certified according to DIN V VDE V 0884-10
(VDE V 0884-10): 2006-12
In accordance with DIN V VDE V 0884-10, each ADM2481 is proof
tested by applying an insulation test voltage of ≥ 1050 V peak for
1 second (partial discharge detection limit = 5 pC).
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Minimum External Air Gap (Clearance) L(I01) 7.7 mm Measured from input terminals to output
terminals, shortest distance through air
Minimum External Tracking (Creepage) L(I02) 7.6 mm Measured from input terminals to output
terminals, shortest distance along body
Minimum Internal Gap (Internal Clearance) 0.017 min mm Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >175 V DIN IEC 112/VDE 0303 Part 1
Isolation Group IIIa Material Group (Table 1 in DIN VDE 0110,1/89)
Rev. A | Page 4 of 20
Data Sheet ADM2481
Input-to-Output Test Voltage, Method a
VDE 0884 INSULATION CHARACTERISTICS
This isolator is suitable for basic electrical isolation only within this safety limit data. Maintenance of this safety data shall be ensured by
means of protective circuits.
Table 6.
Description Symbol Characteristic Unit
Installation Classification per DIN VDE 0110 for Rated Mains Voltage
≤150 V rms I to IV
≤300 V rms I to III
≤400 V rms I to II
Climatic Classification 40/85/21
Pollution Degree (Table 1 in DIN VDE 0110) 2
Maximum Working Insulation Voltage V
Input to Output Test Voltage, Method b1 VPR 1050 V
V
× 1.875 = VPR, 100% Production Tested
IORM
tm = 1 sec, Partial Discharge of < 5 pC
(After Environmental Tests, Subgroup 1)
V
× 1.6 = VPR, tm = 60 sec, Partial Discharge of < 5 pC 896 V
IORM
(After Input and/or Safety Test, Subgroup 2/3)
V
× 1.2 = VPR, tm = 60 sec, Partial Discharge of < 5 pC VPR 672 V
IORM
Highest Allowable Overvoltage
(Transient Overvoltage, tTR = 10 sec) VTR 4000 V
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure; see Figure 13)
Case Temperature TS 150 °C
Input Current I
Output Current I
Insulation Resistance at TS, VIO = 500 V RS >109 Ω
560 V
IORM
265 mA
S, INPUT
335 mA
S, OUTPUT
PEAK
PEAK
PEAK
PEAK
PEAK
Rev. A | Page 5 of 20
ADM2481 Data Sheet
V
−0.5 V to +7 V
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. All voltages are relative to
their respective ground.
Table 7.
Parameter Rating
DD1
V
−0.5 V to +6 V
DD2
Digital Input Voltage (DE, RE, TxD) −0.5 V to V
Digital Output Voltage (RxD) −0.5 V to V
Driver Output/Receiver Input Voltage −9 V to +14 V
ESD Rating: Contact (Human Body
Model) (A, B Pins)
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −55°C to +150°C
Average Output Current per Pin −35 mA to +35 mA
θJA Thermal Impedance 65°C/W
Lead Temperature
Soldering (10 sec) 260°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
±2 kV
DD1
DD1
+ 0.5 V
+ 0.5 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 20
Data Sheet ADM2481
NC = NO CONNECT
ADM2481
TOP VIEW
(Not to S cale)
V
DD1
1
V
DD2
16
GND
1
1
2
GND
2
1
15
RxD
3
NC
14
RE
4
B
13
DE
5
A
12
TxD
6
NC
11
GND
1
1
7
GND
2
1
10
GND
1
1
8
GND
2
1
9
1
PIN 2, PI N 7, AND PIN 8 MUST BE CONNECTED TO GND1.
PIN 9, PI N 10, AND PIN 15 MUST BE CONNECTED TO GND
2
.
08920-002
9, 10, 15
GND2
Ground (Bus Side).
down, Pin B is put into a high impedance state to avoid overloading the bus.
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 2. Pin Configuration
Table 8. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
Power Supply (Logic Side).
DD1
2, 7, 8 GND1 Ground (Logic Side).
3 RxD Receiver Output Data. When enabled, if (A − B) ≥ −30 mV, then RxD = high; if (A − B) ≤ −200 mV, then
RxD = low. This is a tristate output when the receiver is disabled, that is, when
4
Receiver Enable Input. This is an active-low input. Driving this input low enables the receiver, and
RE
is driven high.
RE
driving it high disables the receiver.
5 DE Driver Enable Input. Driving the input high enables the driver, and driving it low disables the driver.
6 TxD Transmit Data Input. Data to be transmitted by the driver is applied to this input.
11, 14 NC No Connect.
12 A Noninverting Driver Output/Receiver Input. When the driver is disabled, or when V
DD1
or V
DD2
is
powered down, Pin A is put into a high impedance state to avoid overloading the bus.
13 B Inverting Driver Output/Receiver Input. When the driver is disabled, or when V
16 V
Power Supply (Bus Side).
DD2
DD1
or V
is powered
DD2
Rev. A | Page 7 of 20
ADM2481 Data Sheet
1.6
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
8525–40
08920-038
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
I
DD1
_RCVR_ENABLE @ 5.5V
I
DD2
_DE_ENABLE @ 5.5V
120
100
80
60
40
20
0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (mA)
08920-014
–10
–30
–50
–70
–90
–110
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (mA)
08920-015
0.32
0.30
0.28
0.26
0.24
0.22
0.20
–40 80655035205–10–25
08920-031
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
4.78
4.76
4.74
4.72
4.70
4.68
4.66
–40 80655035205–10–25
08920-032
TEMPERATURE (°C)
OUTPUT VOLTAGE (V)
90
0
10
20
30
40
50
60
70
80
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
DIFFERENTIAL OUTPUT VOLTAGE (V)
DRIVER OUT P UT CURRENT (mA)
08920-013
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 3. Unloaded Supply Current vs. Temperature
Figure 4. Output Current vs. Driver Output Low Voltage
Figure 6. Receiver Output Low Voltage vs. Temperature, I
Figure 7. Receiver Output High Voltage vs. Temperature, I
= –4 mA
OUT
= 4 mA
OUT
Figure 5. Output Current vs. Driver Output High Voltage
Figure 8. Driver Output Current vs. Differential Output Voltage
Rev. A | Page 8 of 20
Data Sheet ADM2481
600
500
400
300
200
100
0
60 8535–15 10–40
08920-034
TEMPERATURE (°C)
TIME (ns)
t
PLHA
t
PHLA
t
PLHB
t
PHLB
800
0
100
200
300
400
500
600
700
08920-035
TIME (ns)
t
PLH
t
PHL
60 8535–15 10–40
TEMPERATURE (°C)
CH1 5.00V CH2 1.00V
CH3 1.00V CH4 5.00V
M200ns A CH1 3.10V
1
2
4
T 1.33600µs
08920-022
CH1 5.00V CH2 1.00V
CH3 1.00V CH4 5.00V
M200ns A CH1 3.10V
1
2
4
T 360.000ns
08920-023
Figure 9. Driver Propagation Delay vs. Temperature
Figure 10. Receiver Propagation Delay vs. Temperature
Figure 11. Driver/Receiver Propagation Delay, High to Low
Figure 12. Driver/Receiver Propagation Delay, Low to High
Rev. A | Page 9 of 20
ADM2481 Data Sheet
350
300
250
200
150
100
50
0
0 50 100 150 200
CASE TEMPERATURE (°C)
SAFETY-LIMITI NG CURRENT (mA)
BUS SIDE
LOGIC SIDE
08920-024
35
0
5
10
15
20
25
30
2.252.001.751.501.251.000.750.500.250
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (mA)
08920-037
0
–30
–25
–20
–15
–10
–5
5.03.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8
OUTPUT VOLTAGE (V)
OUTPUT CURRE NT (mA)
08920-036
Figure 13. Thermal Derating Curve, Dependence of Safety-Limiting Values
with Case Temperature per VDE 0884
Figure 14. Output Current vs. Receiver Output Low Voltage
Figure 15. Output Current vs. Receiver Output High Voltage
Rev. A | Page 10 of 20
Data Sheet ADM2481
Ω
V
V
A
V
TEST CIRCUITS
CC
R
V
L
OD
R
L
V
OC
08920-003
Figure 16. Driver Voltage Measurement
375
V
OD3
60Ω
375Ω
V
TEST
08920-004
Figure 17. Driver Voltage Measurement over Common-Mode Range
0V OR 3
DE IN
A
DE
S1
B
Figure 19. Driver Enable/Disable
RE
B
C
Figure 20. Receiver Propagation Delay
R
L
C
L
V
OUT
V
OUT
L
S2
08920-006
08920-007
CC
R
L
S2
8920-008
A
R
B
L
C
L1
C
L2
Figure 18. Driver Propagation Delay
+1.5V
S1
–1.5V
8920-005
RE IN
RE
C
L
V
OUT
Figure 21. Receiver Enable/Disable
Rev. A | Page 11 of 20
ADM2481 Data Sheet
V
V
V
SWITCHING CHARACTERISTICS
DD1
0V
V
OH
A, B
V
OL
A – B
RxD
0.5V
= |
t
–
t
PLH
PHL
B
A
1/2V
V
OD
10% POINT
0.5V
OD
90% POINT
DD1
t
PLH
t
SKEW
t
R
Figure 22. Driver Propagation Delay, Rise/Fall Timing
t
PLH
t
= |
t
–
PLH
t
PHL
SKEW
Figure 23. Receiver Propagation Delay
DD1
|
t
PHL
90% POINT
10% POINT
t
F
DE
A, B
A, B
04736-009
0.5V
t
ZL
t
ZH
DD1
2.3V
2.3V
t
LZ
t
HZ
0.5V
DD1
VOL + 0.5V
VOH – 0.5V
0.7
0.3V
DD1
DD1
V
OL
V
OH
0V
08920-011
Figure 24. Driver Enable/Disable Timing
0.7
DD1
t
t
HZ
0.5V
LZ
DD1
VOL + 0.5V
VOH – 0.5V
0.3V
DD1
V
OL
V
OH
08920-012
0.5V
RE
0V0V
RxD
t
PHL
V
OH
1.5V1.5V
|
V
OL
08920-010
RxD
0V
DD1
t
ZL
1.5V
OUTPUT LOW
t
ZH
OUTPUT HIGH
1.5V
Figure 25. Receiver Enable/Disable Timing
Rev. A | Page 12 of 20
Data Sheet ADM2481
V
V
CIRCUIT DESCRIPTION
ELECTRICAL ISOLATION
In the ADM2481, electrical isolation is implemented on the
logic side of the interface. Therefore, the part has two main
sections: a digital isolation section and a transceiver section (see
Figure 26). Driver input and data enable signals, applied to the
TxD and DE pins, respectively, and referenced to logic ground
(GND
), are coupled across an isolation barrier to appear at the
1
transceiver section referenced to isolated ground (GND
Similarly, the receiver output, referenced to isolated ground in
the transceiver section, is coupled across the isolation barrier
to appear at the RxD pin referenced to logic ground (GND
DD1
).
2
).
1
ISOLATION
BARRIER
iCoupler Technology
The digital signals are transmitted across the isolation barrier
using iCoupler technology. This technique uses chip-scale
transformer windings to couple the digital signals magnetically from one side of the barrier to the other. Digital inputs
are encoded into waveforms that are capable of exciting the
primary transformer winding. At the secondary winding, the
induced waveforms are then decoded into the binary value that
was originally transmitted.
DD2
TxD
RxD
DE
RE
DECODEENCODE
DECODEENCODE
ENCODEDECODE
DIGITAL ISOLATION TRANSCEIVER
GND
1
GND
2
Figure 26. Digital Isolation and Transceiver Sections
D
R
A
B
04736-025
Rev. A | Page 13 of 20
ADM2481 Data Sheet
RE
;π
2
n
r
dt
dβ
V ∑
−
=
Nn ,...,2,1=
TRUTH TABLES
The following truth tables use the abbreviations shown in Ta ble 9.
Table 9.
Letter Description
H High level
L Low level
X Don’t care
Z High impedance (off)
NC Disconnected
Table 10. Transmitting
Supply Status Inputs Outputs
V
V
DD1
DE TxD A B
DD2
On On H H H L
On On H L L H
On On L X Z Z
On Off X X Z Z
Off On L L Z Z
Off Off X X Z Z
Table 11. Receiving
Supply Status Inputs Outputs
V
V
DD1
On On >−0.03 L or NC H
On On <−0.2 L or NC L
On On −0.2 < A − B < −0.03 L or NC Indeterminate
On On Inputs open L or NC H
On On X H Z
On Off X L or NC H
Off Off X L or NC L
A − B (V)
DD2
RxD
THERMAL SHUTDOWN
The ADM2481 contains thermal shutdown circuitry that
protects the part from excessive power dissipation during
fault conditions. Shorting the driver outputs to a low impedance
source can result in high driver currents. The thermal sensing
circuitry detects the increase in die temperature under this
condition and disables the driver outputs. This circuitry is
designed to disable the driver outputs when a die temperature
of 150°C is reached. As the device cools, the drivers are re-enabled
at a temperature of 140°C.
TRUE FAIL-SAFE RECEIVER INPUTS
The receiver inputs have a true fail-safe feature that ensures that
the receiver output is high when the inputs are open or shorted.
During line-idle conditions, when no driver on the bus is
enabled, the voltage across a terminating resistance at the
receiver input decays to 0 V. With traditional transceivers,
receiver input thresholds specified between −200 mV and
+200 mV mean that external bias resistors are required on the
A and B pins to ensure that the receiver outputs are in a known
state. The true fail-safe receiver input feature eliminates the
need for bias resistors by specifying the receiver input threshold between −30 mV and −200 mV. The guaranteed negative
threshold means that when the voltage between A and B decays
to 0 V, the receiver output is guaranteed to be high.
MAGNETIC FIELD IMMUNITY
Because iCouplers use a coreless technology, no magnetic
components are present, and the problem of magnetic saturation of the core material does not exist. Therefore, iCouplers
have essentially infinite dc field immunity. The analysis that
follows defines the conditions under which this might occur.
The 3 V operating condition of the ADM2481 is examined
because it represents the most susceptible mode of operation.
The limitation on the ac magnetic field immunity of the
iCoupler is set by the condition in which the induced error
voltage in the receiving coil (the bottom coil in this case) is
made sufficiently large, either to falsely set or reset the decoder.
The voltage induced across the bottom coil is given by
where, if the pulses at the transformer output are greater than
1.0 V in amplitude:
β is the magnetic flux density (gauss).
N is the number of turns in receiving coil.
r
is the radius of nth turn in receiving coil (cm).
n
The decoder has a sensing threshold of about 0.5 V; therefore,
there is a 0.5 V margin in which induced voltages can be
tolerated.
Rev. A | Page 14 of 20
Data Sheet ADM2481
100.000
10.000
1.000
0.100
0.010
0.001
1k 10k 100k 1M 10M 100M
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOWABLE MAGNET IC
FLUX DENSITY (kGAUSS)
08920-027
1000.00
100.00
0.10
1.00
10.00
0.01
1k 10k 100k 1M 10M 100M
MAGNETIC FIELD FREQUENCY (Hz)
MAXIMUM ALLOWABLE CURRENT (kA)
DISTANCE = 1m
DIS
TANCE = 5mm
DISTANCE = 100mm
08920-028
Given the geometry of the receiving coil and an imposed
requirement that the induced voltage is, at most, 50% of the
0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated, as shown in Figure 27.
These magnetic flux density values are shown in Figure 28,
using more familiar quantities such as maximum allowable
current flow, at given distances away from the ADM2481
transformers.
Figure 27. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.2 kGauss induces a
voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
Similarly, if such an event occurs during a transmitted pulse
and is the worst-case polarity, it reduces the received pulse from
>1.0 V to 0.75 V. This is well above the 0.5 V sensing threshold
of the decoder.
Figure 28. Maximum Allowable Current for Various
Current-to-ADM2481 Spacings
At combinations of strong magnetic field and high frequency,
any loops formed by printed circuit board traces could induce
large enough error voltages to trigger the thresholds of succeeding circuitry. To avoid this possibility, take care in the layout of
such traces.
Rev. A | Page 15 of 20
ADM2481 Data Sheet
L
A
APPLICATIONS INFORMATION
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADM2481 signal isolated RS-485 transceiver requires no
external interface circuitry for the logic interfaces. Power supply
bypassing is required at the input and output supply pins (see
Figure 29).
Bypass capacitors are most conveniently connected between
Pin 1 and Pin 2 for V
. The capacitor value must be between 0.01 μF and 0.1 μF.
V
DD2
The total lead length between both ends of the capacitor and
the input power supply pin must not exceed 20 mm.
V
DD1
GND
1
RxD
RE
DE
TxD
GND
1
GND
1
Figure 29. Recommended Printed Circuit Board Layout
and between Pin 15 and Pin 16 for
DD1
V
DD2
GND
NC
ADM2481
NC = NO CONNECT
TRANSFORMER
DRIVER
B
A
NC
GND
GND
V
CC
2
2
2
V
CC
V
CC
8920-127
ISO
BARRIER
78253
TION
SD103C
SD103C
In applications involving high common-mode transients, take
care to ensure that board coupling across the isolation barrier
is minimized. Furthermore, the board layout must be designed
such that any coupling that does occur equally affects all pins
on a given component side.
Failure to ensure this can cause voltage differentials between
pins that exceed the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
ISOLATED POWER SUPPLY CIRCUIT
The ADM2481 requires isolated power capable of 5 V at
100 mA to be supplied between the V
no suitable integrated power supply is available, a discrete
circuit, such as the one in Figure 30, can be used. A centertapped transformer provides electrical isolation. The primary
winding is excited with a pair of square waveforms that are 180°
out of phase with each other. A pair of Schottky diodes and a
smoothing capacitor are used to create a rectified signal from
the secondary winding. The ADP3330 linear voltage regulator
provides a regulated power supply to the bus-side circuitry of
the ADM2481.
5V
22µF
IN
SD
ERR
NR
++
ADP3330
GND
OUT
10µF
and GND2 pins. If
DD2
V
DD1
V
DD2
ADM2481
GND
Figure 30. Isolated Power Supply Circuit
GND
1
2
08920-029
Rev. A | Page 16 of 20
Data Sheet ADM2481
CONTROLLING DIMENSIONSARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTSFOR
REFERENCE ONLY AND ARE NOT APPROPRIATEFOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AA
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10
0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16
9
8
1
1.27 (0.0500)
BSC
03-27-2007-B
ADM2481BRWZ
500
−40°C to +85°C
16-Lead, Wide Body SOIC_W
RW-16
OUTLINE DIMENSIONS
Figure 31. 16-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
1
Model
ADM2481BRWZ-RL7 500 −40°C to +85°C 16-Lead, Wide Body SOIC_W RW-16
EVAL-ADM2481EBZ ADM2481 Evaluation Board
1
Z = RoHS Compliant Part.
Data Rate (kbps) Temperature Range Package Description Package Option
Rev. A | Page 17 of 20
ADM2481 Data Sheet
NOTES
Rev. A | Page 18 of 20
Data Sheet ADM2481
NOTES
Rev. A | Page 19 of 20
ADM2481 Data Sheet
©2010–2012 Analog Devices, Inc. All rights reserved. Trademarks and
NOTES
registered trademarks are the property of their respective owners.
D08920-0-6/12(A)
Rev. A | Page 20 of 20
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