ANALOG DEVICES ADM1276 Service Manual

Hot Swap Controller and Digital Power and

ADM1276

09718-001

GATE

SENSE+

TIMER

TIMER

ADM1276-3

GND

SENSE–

VCC

V

CP

VCAP

ENABLE

IOUT

UV

OV

1.0V

1.0V

VOUT

VOUT

12-BIT

ADC

SCL
SDA
ADR

SENSE+

IOUT

LDO

CHARGE

PUMP

TIMEOUT

GPO2/ALERT2

PWRGD

LATCH

TIMER ON

SS

CURRENT
LIMIT

FLB

ISET

TIMEOUT

CURRENT

LIMIT

CONTROL

REF

SELECT

1.0V

GATE

DRIVE/

LOGIC

LOGIC

AND

PMBus

×50

+

+

+

+

–

–
–

–

FEATURES

Controls supply voltages from 2 V to 20 V
370 ns response time to short circuit
Resistor-programmable 5 mV to 25 mV current limit
±1% accurate, 12-bit ADC for current, V
Charge pumped gate drive for multiple external N-channel FETs
High gate drive voltage to ensure lowest R
Foldback for tighter FET SOA protection
Automatic retry or latch-off on current fault
Programmable current-limit timer for SOA
Programmable, multifunction GPO
Power-good status output
Analog UV and OV protection
ENABLE pin
Reports power and energy consumption over time
Peak detect registers for current and voltage
PMBus fast mode compliant interface
20-lead LFCSP

APPLICATIONS

Power monitoring and control/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers

GENERAL DESCRIPTION

The ADM1276 is a hot swap controller that allows a circuit board
to be removed from or inserted into a live backplane. It also features
current and voltage readback via an integrated 12-bit analog-to­digital converter (ADC), accessed using a PMBus™ interface.

The load current is measured using an internal current sense
amplifier that measures the voltage across a sense resistor in
the power path via the SENSE+ and SENSE− pins. A default
limit of 20 mV is set, but this limit can be adjusted, if required,
using a resistor divider network from the internal reference
voltage to the ISET pin.

The ADM1276 limits the current through the sense resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage—and, therefore,
the load current—is maintained below the preset maximum. The

ADM1276 protects the external FET by limiting the time that the

FET remains on while the current is at its maximum value. This
current-limit time is set by the choice of capacitor connected to
the TIMER pin. In addition, a foldback resistor network can be
used to actively lower the current limit as the voltage across the
FET is increased. This helps to maintain constant power in the
FET and allows the safe operating area (SOA) to be adhered to

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or othe r
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

IN/VOUT

DSON

readback

Energy Monitoring with PMBus Interface

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

in an effective manner.

In case of a short-circuit event, a fast internal overcurrent
detector responds within 370 ns and signals the gate to shut
down. A 1500 mA pull-down device ensures a fast FET response.
The ADM1276 features overvoltage (OV) and undervoltage (UV)
protection, programmed using external resistor dividers on the

UV and OV pins. A PWRGD signal can be used to detect when
the output supply is valid, using the FLB pin to monitor the
output. A GPO pin can be configured as an output signal that
can be asserted when a programmed current or voltage level is
reached.

The 12-bit ADC can measure the current in the sense resistor,
as well as the supply voltage on the SENSE+ pin or the output
voltage. A PMBus interface allows a controller to read current
and voltage data from the ADC. Measurements can be initiated
by a PMBus command. Alternatively, the ADC can run conti­nuously, and the user can read the latest conversion data whenever
required. As many as four unique PMBus addresses can be selected,
depending on the way that the ADR pin is connected.

The ADM1276 is available in a 20-lead LFCSP with a
that can be configured for automatic retry or latch-off when an
overcurrent fault occurs.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

LATCH

pin

www.analog.com

ADM1276

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

Specifications ..................................................................................... 4

Serial Bus Timing Characteristics .............................................. 7

Absolute Maximum Ratings ............................................................ 8

Thermal Characteristics .............................................................. 8

ESD Caution .................................................................................. 8

Pin Configuration and Function Descriptions ............................. 9

Typical Performance Characteristics ........................................... 11

Typical Application Circuit ........................................................... 17

Theory of Operation ...................................................................... 18

Powering the ADM1276 ............................................................ 18

Current Sense Inputs .................................................................. 18

Current-Limit Reference ........................................................... 19

Setting the Current Limit (ISET).............................................. 19

Soft Start ...................................................................................... 20

Foldback ....................................................................................... 20

Timer ............................................................................................ 21

Hot Swap Retry Duty Cycle ...................................................... 21

FET Gate Drive Clamps ............................................................. 21

Fast Response to Severe Overcurrent ...................................... 22

Undervoltage and Overvoltage ................................................. 22

ENABLE Input ............................................................................ 22

Power Good ................................................................................. 22

VOUT Measurement ................................................................. 23

FET Health .................................................................................. 23

Power Monitor ............................................................................ 23

PMBus Interface ............................................................................. 24

Device Addressing ...................................................................... 24

SMBus Protocol Usage ............................................................... 24

Packet Error Checking ............................................................... 24

SMBus Message Formats ........................................................... 25

Group Commands ...................................................................... 26

Hot Swap Control Commands ................................................. 27

ADM1276 Information Commands ........................................ 27

Status Commands ....................................................................... 27

GPO and Alert Pin Setup Commands ..................................... 28

Rev. A | Page 2 of 48

Power Monitor Commands ...................................................... 28

Warning Limit Setup Commands ............................................ 29

PMBus Direct Format Conversion .......................................... 30

Voltage and Current Conversion Using LSB Values .............. 32

ALERT2

GPO2/

Faults and Warnings .................................................................. 33

Generating an Alert ................................................................... 33

Handling/Clearing an Alert ...................................................... 33

SMBus Alert Response Address ............................................... 33

Example Use of SMBus Alert Response Address ................... 34

PMBus Command Reference........................................................ 35

OPERATION .............................................................................. 36

CLEAR_FAULTS ........................................................................ 36

CAPABILITY .............................................................................. 36

VOUT_OV_WARN_LIMIT ..................................................... 36

VOUT_UV_WARN_LIMIT ..................................................... 36

IOUT_OC_WARN_LIMIT ...................................................... 36

IOUT_WARN2_LIMIT ............................................................. 36

VIN_OV_WARN_LIMIT ......................................................... 37

VIN_UV_WARN_LIMIT ......................................................... 37

PIN_OP_WARN_LIMIT .......................................................... 37

STATUS_BYTE .......................................................................... 37

STAT US_WORD ........................................................................ 38

STATUS_VOUT ......................................................................... 38

STATUS_IOUT .......................................................................... 38

STATUS_INPUT ........................................................................ 39

STATUS_MFR_SPECIFIC ........................................................ 39

READ_EIN .................................................................................. 40

READ_VIN ................................................................................. 40

READ_VOUT ............................................................................. 40

READ_IOUT .............................................................................. 40

READ_PIN .................................................................................. 40

PMBUS_REVISION .................................................................. 40

MFR_ID ....................................................................................... 41

MFR_MODEL ............................................................................ 41

MFR_REVISION ........................................................................ 41

PEAK_IOUT ............................................................................... 41

PEAK_VIN.................................................................................. 41

PEAK_VOUT ............................................................................. 42

PMON_CONTROL ................................................................... 42

Pin Behavior ....................................................... 33

ADM1276

PMON_CONFIG ........................................................................ 42

ALERT2_CONFIG ..................................................................... 43

DEVICE_CONFIG ..................................................................... 44

POWER_CYCLE ......................................................................... 44

PEAK_PIN ................................................................................... 44

REVISION HISTORY

7/11—Rev. 0 to Rev. A

Changes to Features Section ............................................................ 1

Changes to General Description Section ...................................... 1

Added Endnote 1 to Table 2 ............................................................. 8

Changes to Figure 3......................................................................... 10

Changes to Table 5 .......................................................................... 10

Changes to Power Monitor Section .............................................. 24

Changes to PMBus Direct Format Conversion Section ............. 31

3/11—Revision 0: Initial Version

READ_PIN_EXT ........................................................................ 44

READ_EIN_EXT ........................................................................ 44

Outline Dimensions ........................................................................ 45

Ordering Guide ........................................................................... 45

Rev. A | Page 3 of 48

ADM1276

HYST

ΔSENSE

ΔSENSE

SENSE+

SENSE−

ISETRSTH

ISET

ISETRS TH

CLREF

SENSE+

GAT E

GAT EDN _SLOW

GAT E

ISET

FLB

SPECIFICATIONS

VCC = 2.95 V to 20 V, VCC ≥ V

Table 1.

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Operating Voltage Range VCC 2.95 20 V
Undervoltage Lockout 2.4 2.7 V VCC rising
Undervoltage Hysteresis 90 120 mV
Quiescent Current ICC 5 mA GATE on and power monitor running

UV PIN

Input Current IUV 100 nA UV ≤ 3.6 V
UV Threshold UVTH 0.97 1.0 1.03 V UV falling
UV Threshold Hysteresis UV
UV Glitch Filter UVGF 2 7 μs 50 mV overdrive
UV Propagation Delay UVPD 5 8 μs UV low to GATE pull-down active

OV PIN

Input Current IOV 100 nA OV ≤ 3.6 V
OV Threshold OVTH 0.97 1.0 1.03 V OV rising
OV Threshold Hysteresis OV
OV Glitch Filter OVGF 0.5 1.5 μs 50 mV overdrive
OV Propagation Delay OVPD 1.0 2 μs OV high to GATE pull-down active

SENSE+ AND SENSE− PINS

Input Current I
Input Imbalance I

VCAP PIN

Internally Regulated

Voltage

ISET PIN

Reference Select Threshold V
Internal Reference V
Gain of Current Sense

Amplifier

Input Current I

GATE PIN Maximum voltage on the gate is always clamped to ≤31 V

Gate Drive Voltage ΔV
10 12 14 V 17 V ≥ VCC ≥ 8 V; I

4.5 13 V 20 V ≥ VCC ≥ 17 V; I
8 10 V V

4.5 6 V V
Gate Pull-Up Current I
Gate Pull-Down Current I

Regulation I
Slow I
Fast I

Gate Holdoff Resistance 20 Ω VCC = 0 V

HOT SWAP SENSE VOLTAGE

Hot Swap Sense Voltage

Current Limit

Foldback Inactive V

24.6 25 25.4 mV V

19.6 20 20.4 mV V

9.6 10 10.4 mV V

4.6 5 5.4 mV V

, V

SENSE+

= 2 V to 20 V, V

SENSE+

SENSE

= (V

SENSE+

− V

) = 0 V, TA = −40°C to +85°C, unless otherwise noted.

SENSE−

40 50 60 mV

50 60 70 mV

HYST

150 μA Per individual pin; SENSE+, SENSE− = 20 V

SENSEx

5 μA I

V

2.66 2.7 2.74 V 0 µA ≤ I

VCAP

1.35 1.5 1.65 V If V

1 V Accuracies included in total sense voltage accuracies

CLREF

AV

50 V/V Accuracies included in total sense voltage accuracies

CSAMP

100 nA V

ISET

ΔV

GAT E

−20 −30 μA V

GAT EU P

GATEDN

GATEDN_REG

45 60 75 μA V

5 10 15 mA V

GATEDN_FAST

V

SENSECL

750 1500 2000 mA V

19.6 20 20.4 mV V

Rev. A | Page 4 of 48

= (I

≤ 100 µA; C

VCAP

> V

≤ V

VCAP

= V

GAT E

ISET

GAT E

= VCC = 5 V; I
= VCC = 2.95 V; I

SENSE+

= 0 V

GAT E

≥ 2 V; V

GAT E

ISET

≥ 2 V
≥ 12 V; VCC ≥ 12 V

GAT E

> 1.65 V; V

ISET

V

≥ 2 V

SS

= (SENSE+) + 3 V; I

GAT E

= 1.25 V; V

ISET

= 1.0 V; V
= 0.5 V; V

ISET

= 0.25 V; V

ISET

) − (I

)

VCAP

= 1 μF

, an internal 1 V reference (V

− V

SENSE+

GAT E

GAT E

≤ 5 μA

≤ 5 μA

≤ 5 μA

≤ 1 μA

GAT E

= 1.0 V; (SENSE+) − (SENSE−) = 30 mV

> 1.12 V; V

FLB

> 1.395 V

FLB

= (SENSE+) + 3 V; I

GAT E

= 0 μA; VSS ≥ 2 V

GAT E

> 1.12 V
> 0.57 V

FLB

> 0.295 V

FLB

) is used

= 0 μA;

GAT E

ADM1276

SS

CBOS

SENSECL

CBOS

TI ME RU PFLT

TIMER

TIMERH

LAT CH

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Foldback Active 3.5 4 4.5 mV V

9.6 10 10.4 mV V

Circuit Breaker Offset V

0.6 0.88 1.12 mV Circuit breaker trip voltage, VCB = V

SEVERE OVERCURRENT

Voltage Threshold V

40 50 mV V

SENSEOC

9.5 13.0 mV V
Short Glitch Filter Duration 90 200 ns V

Long Glitch Filter Duration

530 900 ns V

(Default)

Response Time

With Short Glitch Filter 180 370 ns 2 mV overdrive maximum severe overcurrent threshold
With Long Glitch Filter 645 1020 ns

SOFT START (SS PIN)

SS Pull-Up Current ISS −12 −10 −8 µA VSS = 0 V
Default V

Limit 0.5 1.25 1.8 mV When V

SENSECL

SS Pull-Down Current 100 µA VSS = 1 V

TIMER PIN

Timer Pull-Up Current I

Power-On Reset(POR) I
Overcurrent (OC) Fault I

TIMERUP

TIMERUPPOR

−2 −3 −4 µA Initial power-on reset; V

−57 −60 −63 µA Overcurrent fault; 0.2 V ≤ V

Timer Pull-Down Current

Retry I
Hold I

Timer Retry/OC Fault

1.7 2 2.3 µA After fault when GATE is off; V

TIMERDNRT

TIMERDNHOLD

100 µA Holds TIMER at 0 V when inactive; V

3.33 3.8 % Defines the limits of the autoretry duty cycle

Current Ratio
Timer High Threshold V
Timer Low Threshold V

0.98 1.0 1.02 V

0.18 0.2 0.22 V

TIMERL

FOLDBACK (FLB PIN)

FLB and PWRGD Threshold V
Input Current I

1.08 1.1 1.12 V FLB rising; V

FLBTH

100 nA V

FLB

100 nA V
Hysteresis Current 1.7 2.3 μA
Internal Hysteresis Voltage 1.9 3.1 mV Voltage drop across the internal 1.3 kΩ resistor
Power-Good Glitch Filter PWRGDGF 0.3 0.7 1 μs 50 mV overdrive
Minimum Foldback Clamp 200 mV Accuracies included in total sense voltage accuracies

VOUT PIN

Input Current 20 μA VOUT = 20 V

PIN

LATC H

Output Low Voltage V

0.4 V I

OL_LATC H

1.5 V I
Leakage Current 100 nA V

1 µA V

ENABLE PIN No internal pull-up present on this pin

Leakage Current 100 nA V
1 µA V
Input High Voltage VIH 1.1 V
Input Low Voltage VIL 0.8 V

= 0 V; V

FLB

> 1.0 V; V

ISET

≥ 1 V

V

= 1.0 V; V

ISET

= 0.25 V; V

ISET

> 1.65 V; V

ISET

= (SENSE+) + 3 V; I

GAT E

= 0.5 V; V

FLB

> 1.1 V; VSS ≥ 2 V

FLB

> 1.1 V; VSS ≥ 2 V

FLB

driven from 18 mV to 52 mV; selectable via

SENSE

PMBus

driven from 18 mV to 52 mV

SENSE

reaches this level, ISS is enabled, ramping V

SENSE

V

= 0 V

SS

= 1.0 V

ISET

≤ 1.0 V; V

FLB

≤ V

VCAP

= 1 mA

LAT CH

≤ 20 V

FLB

= 1.25 V

ISET

= 5 mA

LAT CH

LAT CH

GPO2

GPO2

≤ 2 V;
= 20 V;

≤ 2 V
= 20 V

output high-Z

LATC H

LATC H

output high-Z

GAT E

= (SENSE+) + 3 V; I

GAT E

= 0.5 V

TIMER

≤ 1 V

= 0.5 V

TIMER

TIMER

= 0 μA; VSS ≥ 1 V

= 0 μA;

GAT E

− V

= 0.5 V

SENSECL

;

Rev. A | Page 5 of 48

ADM1276

GPO2

PWRGD

SENSE

SENSE

SENSE+

ADR

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

GPO2/

Output Low Voltage V

1.5 V I

Leakage Current 100 nA V
1 µA V
PWRGD PIN

Output Low Voltage V

1.5 V I

VCC That Guarantees Valid

Output

Leakage Current 100 nA V
1 µA V
CURRENT AND VOLTAGE

MONITORING

Current Sense Absolute

Error
±0.2 ±0.7 % V
±0.08 % V
±1.0 % V
±0.08 % V
±0.2 % V
±1.0 % V
±0.08 % V
±0.2 % V
±2.8 % V
±0.09 % V
±0.2 % V
±0.7 % V
±0.04 % V
±0.15 % V
±0.75 % V
±0.8 % V
±1.1 % V
±2.0 % V
±4.3 % V

SENSE+/VOUT Absolute

Error
±1.0 % High input range; input voltage ≥ 10 V

ADC Conversion Time Includes time for power multiplication

237 280 µs 1 sample of VIN and IOUT; from command received to valid

360 426 µs 1 sample of VIN, VOUT, and IOUT; from command received to

3753 4233 µs 16 samples of VIN and IOUT averaged; from command

5545 6570 µs 16 samples of VIN, VOUT, and IOUT averaged; from command

Power Multiplication Time 14 µs

ADR PIN

Address Set to 00 0 0.8 V Connect to GND
Input Current for Address 00 −40 −22 μA V
Address Set to 01 135 150 165 kΩ Resistor to GND
Address Set to 10 −1 +1 μA No connect state; maximum leakage current allowed

PIN

ALERT2

0.4 V I

OL_GPO2

0.4 V I

OL_PWRGD

1 V I

25 mV input range; 128 sample averaging (unless otherwise

±1.0 % Low input range; input voltage ≥ 3 V

= 1 mA

GPO2

= 5 mA

GPO2

≤ 2 V; GPO output high-Z
= 20 V; GPO output high-Z

GPO2

= 1 mA

PWRGD

= 5 mA

PWRGD

= 100 μA; V

SINK

≤ 2 V; PWRGD output high-Z

PWRGD

OL_PWRGD

= 0.4 V

= 20 V; PWRGD output high-Z

noted)

= 20 mV; V

SENSE

= 20 mV; V

SENSE

= 20 mV

SENSE

= 20 mV; TA = 25°C

SENSE

= 20 mV; TA = 0°C to 65°C

SENSE

= 20 mV; 16 sample averaging

SENSE

= 20 mV; 16 sample averaging; TA = 25°C

SENSE

= 20 mV; 16 sample averaging; TA = 0°C to 65°C

SENSE

= 20 mV; 1 sample averaging

SENSE

= 12 V; TA = 0°C to 65°C

SENSE+

= 12 V; TA = 25°C

SENSE+

= 20 mV; 1 sample averaging; TA = 25°C
= 20 mV; 1 sample averaging; TA = 0°C to 65°C

SENSE

= 25 mV; V

SENSE

= 25 mV; V

SENSE

= 25 mV; V

SENSE

= 20 mV; V

SENSE

= 15 mV; V
= 10 mV; V

SENSE

= 5 mV; V

SENSE

= 2.5 mV; V

SENSE

= 12 V

SENSE+

= 12 V; TA = 25°C

SENSE+

= 12 V; TA = 0°C to 65°C

SENSE+

= 12 V

SENSE+

= 12 V
= 12 V

SENSE+

= 12 V

SENSE+

= 12 V

SENSE+

data in register

valid data in register

received to valid data in register

received to valid data in register

= 0 V to 0.8 V

Rev. A | Page 6 of 48

ADM1276

SU;STA

R

t

LOW

t

BUF

t

HD;DAT

t

SU;DAT

t

SU;STA

t

HD;STA

t

HIGH

t

R

t

F

t

SU;STO

PSSP

V

IH

V

IL

V

IH

V

IL

SCL

SDA

09718-002

Parameter Symbol Min Typ Max Unit Test Conditions/Comments

Address Set to 11 2 V Connect to VCAP
Input Current for Address 11 3 10 μA V

SERIAL BUS DIGITAL INPUTS

(SDA, SCL)
Input High Voltage VIH 1.1 V
Input Low Voltage VIL 0.8 V
Output Low Voltage VOL 0.4 V IOL = 4 mA
Input Leakage I

−10 +10 μA

LEAK-PIN

−5 +5 μA Device is not powered
Nominal Bus Voltage VDD 2.7 5.5 V 3 V to 5 V ± 10%
Capacitance for SDA, SCL

C

5 pF

PIN

Pins

Input Glitch Filter tSP 0 50 ns

SERIAL BUS TIMING CHARACTERISTICS

Table 2.

Parameter Description Min Typ Max Unit Test Conditions/Comments

f

Clock frequency 400 kHz

SCLK

t

Bus free time 1.3 µs Following the stop condition of a read transaction

BUF

4.7 µs Following the stop condition of a write transaction
t

Start hold time 0.6 µs

HD ;STA

t

Start setup time 0.6 µs

t

Stop setup time 0.6 µs

SU;STO

t

SDA hold time 300 900 ns

HD ;D AT

t

SDA setup time 100 ns

SU ;D AT

t

SCL low time 1.3 µs

LOW

t

SCL high time 0.6 µs

HIGH

1

t

SCL, SDA rise time 20 300 ns

tF SCL, SDA fall time 20 300 ns

1

Note: tR = (V

Timing Diagram

− 0.15) to (V

IL(MAX )

+ 0.15) and tF = 0.9 VDD to (V

IH3V3

− 0.15); where V

IL(MAX )

= 2.1 V, and VDD = 3.3 V.

IH3V3

= 2.0 V to VCAP; must not exceed the maximum allowable

ADR

current draw from VCAP

Figure 2. Serial Bus Timing Diagram

Rev. A | Page 7 of 48

ADM1276

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VCC Pin −0.3 V to +25 V
UV Pin −0.3 V to +4 V
OV Pin −0.3 V to +4 V
SS Pin −0.3 V to VCAP + 0.3 V
TIMER Pin −0.3 V to VCAP + 0.3 V
VCAP Pin −0.3 V to +4 V
ISET Pin −0.3 V to VCAP + 0.3 V

Pin −0.3 V to +25 V

LATC H
SCL Pin −0.3 V to +6.5 V
SDA Pin −0.3 V to +6.5 V
ADR Pin −0.3 V to VCAP + 0.3 V
ENABLE Pin −0.3 V to +25 V
GPO2/

Pin −0.3 V to +25 V

ALERT2
PWRGD Pin −0.3 V to +25 V
FLB Pin −0.3 V to +25 V
VOUT Pin −0.3 V to +25 V
GAT E Pin (Internal Supply Only)1 −0.3 V to +36 V
SENSE+ Pin −0.3 V to +25 V
SENSE− Pin −0.3 V to +25 V
V

(V

SENSE

SENSE+

− V

) ±0.3 V

SENSE−

Continuous Current into Any Pin ±10 mA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature, Soldering (10 sec) 300°C
Junction Temperature 150°C

1

The GATE pin has internal clamping circuits to prevent the GATE pin voltage

from exceeding the maximum ratings of a MOSFET with V
internal process limits. Applying a voltage source to this pin externally may
cause irreversible damage.

GSMAX

= 20 V and

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θJA Unit

20-lead LFCSP (CP-20-9) 30.4 °C/W

ESD CAUTION

Rev. A | Page 8 of 48

ADM1276

1OV
2VCAP
3ISET
4SS
5TIMER

LATCH

ADR

ENABLE

GPO2/ALERT2

SDA

13

14

15

12
11

FLB

VOUT

GND

PWRGD
SCL

SENSE+

VCC

UV

SENSE–

GATE

6

7

8

01

9

81

91

02

71

61

ADM1276-3

TOP VIEW

(Not to S cale)

PIN 1
INDICATOR

NOTES

1. SOLDER THE EXPOSED PADDLE TO
THE BOARD T O IMPRO V E THERMAL
DISSIPATION. THE EXPOSED PADDLE
CAN BE CONNECTE D TO GRO UND.

09718-003

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

19 VCC Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low supply voltage is

detected. GATE is held low when the supply is below UVLO. During normal operation, this pin should remain
greater than or equal to SENSE+ to ensure that specifications are adhered to. No sequencing is required.

20 UV Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal

comparator to detect whether the supply is under the UV limit.

1 OV Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal

comparator to detect whether the supply is above the OV limit.

2 VCAP Internal Regulated Supply. Place a capacitor with a value of 1 µF or greater on this pin to maintain good

accuracy. This pin can be used as a reference to program the ISET pin voltage.

3 ISET Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin

is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a
resistor divider from VCAP. An external reference can also be used.

4 SS Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the SS pin controls

the current sense voltage limit, which controls the inrush current profile.

5 TIMER Timer Pin. An external capacitor, C

, sets an initial timing cycle delay and a fault delay. The GATE pin is pulled

TIMER

low when the voltage on the TIMER pin exceeds the upper threshold.

6

Latch Pin. This pin signals that the device is latching off after an overcurrent fault. The device can be configured

LATC H

for automatic retry after latch-off by connecting this pin directly to the UV or the ENABLE pin.

7 ADR PMBus Address Pin. This pin can be tied to GND, tied to VCAP, remain floating, or tied low through a resistor to

set four different PMBus addresses (see the Device Addressing section).

8 ENABLE Enable Pin. This pin is a digital logic input. This input must be high to allow the ADM1276 hot swap controller to

begin a power-up sequence. If this pin is held low, the ADM1276 is prevented from powering up. There is no
internal pull-up on this pin.

General-Purpose Digital Output/Alert. This is a dual function pin. There is no internal pull-up on this pin. The

ALERT2

function of this pin can be configured to generate an alert signal when one or more fault or warning

ALERT2
conditions are detected. At power-up,

indicates the FET health mode by default.

ALERT2

present on the FLB pin.

the current limit when the source voltage drops. The foldback feature ensures that the power through the FET is
not increased beyond the SOA limits.

9 GPO2/

10 SDA Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up.
11 SCL Serial Clock Pin. Open-drain input. Requires an external resistive pull-up.
12 PWRGD Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on the voltage

13 FLB Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback is used to reduce

Rev. A | Page 9 of 48

ADM1276

Pin No. Mnemonic Description

14 VOUT Output Voltage. This pin is used to read back the output voltage using the internal ADC. A 1 kΩ resistor should

be inserted in series between the source of a FET and the VOUT pin.
15 GND Ground Pin.
16 GATE Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the FET

drive controller, which uses a charge pump to provide a pull-up current to charge the FET gate pin. The FET drive

controller regulates to a maximum load current by regulating the GATE pin. GATE is held low when the supply is

below UVLO.
17 SENSE− Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog

current limit. The hot swap operation of the ADM1276 controls the external FET gate to maintain the sense

voltage (V

SENSE+

− V

18 SENSE+ Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor between the

SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1276 controls

the external FET gate to maintain the sense voltage (V

input voltage using the ADC.
N/A1 EP Exposed Pad. The exposed pad is located on the underside of the LFCSP package. Solder the exposed pad to the

printed circuit board (PCB) to improve thermal dissipation. The exposed pad can be connected to ground.

1

N/A means not applicable.

). This pin also connects to the FET drain pin.

SENSE−

SENSE+

− V

). This pin is also used to measure the supply

SENSE−

Rev. A | Page 10 of 48

ADM1276

0

1

2

3

4

5

I

CC

(mA)

VCC (V)

2 4 6 8 10 12 14 16 18

20

+25°C

+85°C

–40°C

09718-004

0

1

2

3

4

5

–40

–20

0

I

CC

(mA)

TEMPERATURE (°C)

V

CC

= 20V

V

CC

= 12V

V

CC

= 2.95V

20 40 60 80

09718-005

0

2

4

6

8

10

12

14

2 4 6 8 1210 14 16 18 20

I

GATEDN_SLOW

(mA)

V

CC

(V)

+25°C

–40°C

+85°C

09718-006

0

2

4

6

8

10

12

14

I

GATEDN_SLOW

(mA)

TEMPERATURE (°C)

V

CC

= 12V

–40

–20 0 20 40 60 80

09718-007

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

0 5 10 15 20 25

I

GATEDN_SLOW

(mA)

V

GATE

(V)

09718-008

–40

–35

–30

–25

–20

–15

–10

–5

0

2 4 6 8 10 12 14 16 18 20

I

GATEUP

(µA)

VCC (V)

09718-009

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. Supply Current (ICC) vs. Supply Voltage (VCC)

Figure 7. Gate Pull-Down Current (I

GATEDN_SLOW

) vs. Temperature

Figure 5. Supply Current (I

Figure 6. Gate Pull-Down Current (I

) vs. Temperature

CC

GATEDN_SLOW

) vs. Supply Voltage (VCC)

Rev. A | Page 11 of 48

Figure 8. Gate Pull-Down Current (I

Figure 9. Gate Pull-Up Current (I

GATEDN_SLOW

) vs. Gate Voltage (V

) vs. Supply Voltage (VCC)

GATEUP

GATE

)

ADM1276

0

5

10

15

20

25

30

0 5 10 15 20 25

I

GATEUP

(µA)

V

GATE

(V)

V

CC

= 12V

V

CC

= 2.95V

09718-010

–40

–35

–30

–25

–20

–15

–10

–5

0

I

GATEUP

(µA)

TEMPERATURE (°C)

V

CC

= 12V

–40

–20 0 20 40 60 80

09718-011

0

2

4

6

8

10

12

14

16

2 20

ΔV

GATE

(V)

VCC (V)

+85°C

+25°C

–40°C

4 6 8 10 12 14 16 18

09718-012

0

2

4

6

8

10

12

14

16

ΔV

GATE

(V)

V

CC

(V)

2 4 6 8 10 12 14 16 18 20

+25°C

+85°C

–40°C

09718-013

0

2

4

6

8

10

12

14

16

–40 –20 0 20 40 60

ΔV

GATE

(V)

TEMPERATURE (°C)

V

CC

= 12V

V

CC

= 20V

V

CC

= 2.95V

80

09718-014

–20

–18

–16

–14

–12

–10

–8

–6

–4

–2

0

–40

I

SS

(µA)

TEMPERATURE (°C)

V

CC

= 12V

–20 0 20 40 60 80

09718-015

Figure 10. Gate Pull-Up Current (I

Figure 11. Gate Pull-Up Current (I

) vs. Gate Voltage (V

GATEUP

GATEUP

) vs. Temperature

GATE

)

Figure 13. Gate Drive Voltage (ΔV

Figure 14. Gate Drive Voltage (ΔV

) vs. Supply Voltage (VCC), 5 µA Load

GATE

) vs. Temperature, No Load

GATE

Figure 12. Gate Drive Voltage (ΔV

) vs. Supply Voltage (VCC), No Load

GATE

Figure 15. Soft Start Pull-Up Current (I

) vs. Temperature

SS

Rev. A | Page 12 of 48

ADM1276

–80

–70

–60

–50

–40

–30

–20

–10

0

I

TIMERUPFLT

(µA)

–40

TEMPERATURE (°C)

–20 0 20 40 60 80

VCC = 12V

09718-016

–20 0 20 40 60 80

–10

–8

–6

–4

–2

0

I

TIMERUPPOR

(µA)

–40

TEMPERATURE (°C)

V

CC

= 12V

09718-017

–40

–20 0 20 40 60 80

0

1.5

3.0

4.5

I

TIMERDNRT

(µA)

VCC = 12V

TEMPERATURE (°C)

09718-018

0

100

200

300

400

500

600

700

800

900

1000

1100

TIMER T HRE S HOLD (mV)

–40

TEMPERATURE (°C)

–20 0 20 40

60 80

LOW THRESHOLD (VCC = 12V)

HIGH THRES HOLD (V

CC

= 12V)

09718-019

–40 –20 0

TEMPERATURE (°C)

20 40 60 80

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.

8

0.9

1.0

1.1

1.2

1.3

FOLDBACK T HRE S HOLD (V)

2.95V
12V
20V

09718-020

0

0.5

1.0

1.5

2.0

2.5

3.0

FOLDBACK HYS TERESIS CURRENT (µA)

2.95V
12V
20V

–40 –20 0

TEMPERATURE (°C)

20 40 60 80

09718-021

Figure 16. Timer Pull-Up Current, Overcurrent Fault (I

vs. Temperature

Figure 17. Timer Pull-Up Current, Power-On Reset (I

vs. Temperature

TIMERUPFL T

TIMERUPPOR

)

)

Figure 19. Timer Thresholds vs. Temperature

Figure 20. Foldback Threshold vs. Temperature

Figure 18. Timer Pull-Down Current, Retry (I

) vs. Temperature

TIMERDNRT

Figure 21. Foldback Hysteresis Current vs. Temperature

Rev. A | Page 13 of 48

ADM1276

0

20

40

60

80

100

120

140

160

180

200

220

240

FOLDBACK CL AMP (mV)

TEMPERATURE (°C)

V

CC

= 12V

–40

–20 0 20 40 60 80

09718-022

0

25

50

75

100

125

150

175

200

225

250

275

300

325

350

375

400

2 20

OC RESPONSE TIME (ns)

VCC (V)

4 6 8 10 12 14 16 18

+85°C

–40°C

+25°C

09718-023

0

25

50

75

100

125

150

175

200

225

250

275

300

325

350

375

400

OC RESPONSE TIME (ns)

VCC (V)

2 20

4 6 8 10 12 14 16 18

+85°C

+25°C

–40°C

09718-024

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2 20

V

CBOS

(mV)

VCC (V)

–40°C

+85°C

+25°C

4 6 8 10 12 14 16 18

09718-025

0

5

10

15

20

25

30

V

SENSECL

(mV)

TEMPERATURE (°C)

–40

–20 0 20 40 60 80

V

CC

= 12V

09718-026

0

5

10

15

20

25

30

1.11.

00.90.80.70.60.50.40.30.20.10

V

SENSECL

(mV)

V

FLB

(V)

T

A

= 25°C

09718-027

Figure 22. Foldback Clamp vs. Temperature

Figure 23. Severe Overcurrent Response Time vs. Supply Voltage (VCC),

V

= 0.25 V

ISET

Figure 25. Circuit Breaker Offset (V

) vs. Supply Voltage (VCC)

CBOS

Figure 26. Hot Swap Sense Voltage Current Limit (V

) vs. Temperature

SENSECL

Figure 24. Severe Overcurrent Response Time vs. Supply Voltage (VCC),

V

ISET

= 1 V

Figure 27. Hot Swap Sense Voltage Current Limit (V

vs. Foldback Voltage (V

)

FLB

SENSECL

)

Rev. A | Page 14 of 48

ADM1276

0

5

10

15

20

25

30

35

40

45

50

V

SENSEOC

(mV)

V

CC

(V)

TA = 25°C

2 4 6 8 10 12 14 16 18 20

09718-028

15

10

5

0

20

25

30

35

40

45

50

V

SENSEOC

(mV)

VCC = 12V

TEMPERATURE (°C)

–40 –20 0 20 40 60 80

09718-029

0 1 2 3 4 5 6 7 8 9 10 11 12

0

50

100

150

I

SENSEx

(µA)

V

SENSEx

(V)

09718-030

0

5

10

15

20

0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 –22 –24 –26

ΔV

GATE

(V)

I

GATEUP

(µA)

VCC = 2.95V

V

CC

= 12V

VCC = 20V

09718-031

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

0 1 2 3 4 5 6 7 8 9 10

V

OL_PWRGD

(V)

IOL (mA)

VCC = 2.95V

VCC = 12V

09718-032

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

V

OL

(V)

VCC = 2.95V

VCC = 12V

0 1 2 3 4 5 6 7 8 9 10

I

OL

(mA)

09718-033

Figure 28. Severe Overcurrent Voltage Threshold (V

vs. Supply Voltage (V

), V

= V

CC

ISET

VCAP

Figure 29. Severe Overcurrent Voltage Threshold (V

vs. Temperature, V

ISET

= V

VCAP

SENSEOC

SENSEOC

)

)

Figure 31. Gate Drive Voltage (ΔV

Figure 32. PWRGD Pin, VOL vs. IOL

) vs. Gate Pull-Up Current (I

GATE

GATEUP

)

Figure 30. SENSE+/SENSE− Input Current (I

) vs. Voltage (V

SENSEx

SENSEx

)

Figure 33.

LATCH

and GPO2/

ALERT2

Digital Outputs, VOL vs. IOL

Rev. A | Page 15 of 48