Controls supply voltages from 2 V to 20 V
370 ns response time to short circuit
Resistor-programmable 5 mV to 25 mV current limit
±1% accurate, 12-bit ADC for current, V
Charge pumped gate drive for multiple external N-channel FETs
High gate drive voltage to ensure lowest R
Foldback for tighter FET SOA protection
Automatic retry or latch-off on current fault
Programmable current-limit timer for SOA
Programmable, multifunction GPO
Power-good status output
Analog UV and OV protection
ENABLE pin
Reports power and energy consumption over time
Peak detect registers for current and voltage
PMBus fast mode compliant interface
20-lead LFCSP
APPLICATIONS
Power monitoring and control/power budgeting
Central office equipment
Telecommunication and data communication equipment
PCs/servers
GENERAL DESCRIPTION
The ADM1276 is a hot swap controller that allows a circuit board
to be removed from or inserted into a live backplane. It also features
current and voltage readback via an integrated 12-bit analog-todigital converter (ADC), accessed using a PMBus™ interface.
The load current is measured using an internal current sense
amplifier that measures the voltage across a sense resistor in
the power path via the SENSE+ and SENSE− pins. A default
limit of 20 mV is set, but this limit can be adjusted, if required,
using a resistor divider network from the internal reference
voltage to the ISET pin.
The ADM1276 limits the current through the sense resistor by
controlling the gate voltage of an external N-channel FET in the
power path, via the GATE pin. The sense voltage—and, therefore,
the load current—is maintained below the preset maximum. The
ADM1276 protects the external FET by limiting the time that the
FET remains on while the current is at its maximum value. This
current-limit time is set by the choice of capacitor connected to
the TIMER pin. In addition, a foldback resistor network can be
used to actively lower the current limit as the voltage across the
FET is increased. This helps to maintain constant power in the
FET and allows the safe operating area (SOA) to be adhered to
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or othe r
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
IN/VOUT
DSON
readback
Energy Monitoring with PMBus Interface
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
in an effective manner.
In case of a short-circuit event, a fast internal overcurrent
detector responds within 370 ns and signals the gate to shut
down. A 1500 mA pull-down device ensures a fast FET response.
The ADM1276 features overvoltage (OV) and undervoltage (UV)
protection, programmed using external resistor dividers on the
UV and OV pins. A PWRGD signal can be used to detect when
the output supply is valid, using the FLB pin to monitor the
output. A GPO pin can be configured as an output signal that
can be asserted when a programmed current or voltage level is
reached.
The 12-bit ADC can measure the current in the sense resistor,
as well as the supply voltage on the SENSE+ pin or the output
voltage. A PMBus interface allows a controller to read current
and voltage data from the ADC. Measurements can be initiated
by a PMBus command. Alternatively, the ADC can run continuously, and the user can read the latest conversion data whenever
required. As many as four unique PMBus addresses can be selected,
depending on the way that the ADR pin is connected.
The ADM1276 is available in a 20-lead LFCSP with a
that can be configured for automatic retry or latch-off when an
overcurrent fault occurs.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Operating Voltage Range VCC 2.95 20 V
Undervoltage Lockout 2.4 2.7 V VCC rising
Undervoltage Hysteresis 90 120 mV
Quiescent Current ICC 5 mA GATE on and power monitor running
UV PIN
Input Current IUV 100 nA UV ≤ 3.6 V
UV Threshold UVTH 0.97 1.0 1.03 V UV falling
UV Threshold Hysteresis UV
UV Glitch Filter UVGF 2 7 μs 50 mV overdrive
UV Propagation Delay UVPD 5 8 μs UV low to GATE pull-down active
OV PIN
Input Current IOV 100 nA OV ≤ 3.6 V
OV Threshold OVTH 0.97 1.0 1.03 V OV rising
OV Threshold Hysteresis OV
OV Glitch Filter OVGF 0.5 1.5 μs 50 mV overdrive
OV Propagation Delay OVPD 1.0 2 μs OV high to GATE pull-down active
SENSE+ AND SENSE− PINS
Input Current I
Input Imbalance I
VCAP PIN
Internally Regulated
Voltage
ISET PIN
Reference Select Threshold V
Internal Reference V
Gain of Current Sense
Amplifier
Input Current I
GATE PIN Maximum voltage on the gate is always clamped to ≤31 V
Gate Drive Voltage ΔV
10 12 14 V 17 V ≥ VCC ≥ 8 V; I
4.5 13 V 20 V ≥ VCC ≥ 17 V; I
8 10 V V
4.5 6 V V
Gate Pull-Up Current I
Gate Pull-Down Current I
Regulation I
Slow I
Fast I
Gate Holdoff Resistance 20 Ω VCC = 0 V
HOT SWAP SENSE VOLTAGE
Hot Swap Sense Voltage
Current Limit
Foldback Inactive V
24.6 25 25.4 mV V
19.6 20 20.4 mV V
9.6 10 10.4 mV V
4.6 5 5.4 mV V
, V
SENSE+
= 2 V to 20 V, V
SENSE+
SENSE
= (V
SENSE+
− V
) = 0 V, TA = −40°C to +85°C, unless otherwise noted.
SENSE−
40 50 60 mV
50 60 70 mV
HYST
150 μA Per individual pin; SENSE+, SENSE− = 20 V
SENSEx
5 μA I
V
2.66 2.7 2.74 V 0 µA ≤ I
VCAP
1.35 1.5 1.65 V If V
1 V Accuracies included in total sense voltage accuracies
CLREF
AV
50 V/V Accuracies included in total sense voltage accuracies
CSAMP
100 nA V
ISET
ΔV
GAT E
−20 −30 μA V
GAT EU P
GATEDN
GATEDN_REG
45 60 75 μA V
5 10 15 mA V
GATEDN_FAST
V
SENSECL
750 1500 2000 mA V
19.6 20 20.4 mV V
Rev. A | Page 4 of 48
= (I
≤ 100 µA; C
VCAP
> V
≤ V
VCAP
= V
GAT E
ISET
GAT E
= VCC = 5 V; I
= VCC = 2.95 V; I
SENSE+
= 0 V
GAT E
≥ 2 V; V
GAT E
ISET
≥ 2 V
≥ 12 V; VCC ≥ 12 V
GAT E
> 1.65 V; V
ISET
V
≥ 2 V
SS
= (SENSE+) + 3 V; I
GAT E
= 1.25 V; V
ISET
= 1.0 V; V
= 0.5 V; V
ISET
= 0.25 V; V
ISET
) − (I
)
VCAP
= 1 μF
, an internal 1 V reference (V
− V
SENSE+
GAT E
GAT E
≤ 5 μA
≤ 5 μA
≤ 5 μA
≤ 1 μA
GAT E
= 1.0 V; (SENSE+) − (SENSE−) = 30 mV
> 1.12 V; V
FLB
> 1.395 V
FLB
= (SENSE+) + 3 V; I
GAT E
= 0 μA; VSS ≥ 2 V
GAT E
> 1.12 V
> 0.57 V
FLB
> 0.295 V
FLB
) is used
= 0 μA;
GAT E
ADM1276
SS
CBOS
SENSECL
CBOS
TI ME RU PFLT
TIMER
TIMERH
LAT CH
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
9.5 13.0 mV V
Short Glitch Filter Duration 90 200 ns V
Long Glitch Filter Duration
530 900 ns V
(Default)
Response Time
With Short Glitch Filter 180 370 ns 2 mV overdrive maximum severe overcurrent threshold
With Long Glitch Filter 645 1020 ns
SOFT START (SS PIN)
SS Pull-Up Current ISS −12 −10 −8 µA VSS = 0 V
Default V
Limit 0.5 1.25 1.8 mV When V
SENSECL
SS Pull-Down Current 100 µA VSS = 1 V
TIMER PIN
Timer Pull-Up Current I
Power-On Reset(POR) I
Overcurrent (OC) Fault I
TIMERUP
TIMERUPPOR
−2 −3 −4 µA Initial power-on reset; V
−57 −60 −63 µA Overcurrent fault; 0.2 V ≤ V
Timer Pull-Down Current
Retry I
Hold I
Timer Retry/OC Fault
1.7 2 2.3 µA After fault when GATE is off; V
TIMERDNRT
TIMERDNHOLD
100 µA Holds TIMER at 0 V when inactive; V
3.33 3.8 % Defines the limits of the autoretry duty cycle
Current Ratio
Timer High Threshold V
Timer Low Threshold V
0.98 1.0 1.02 V
0.18 0.2 0.22 V
TIMERL
FOLDBACK (FLB PIN)
FLB and PWRGD Threshold V
Input Current I
1.08 1.1 1.12 V FLB rising; V
FLBTH
100 nA V
FLB
100 nA V
Hysteresis Current 1.7 2.3 μA
Internal Hysteresis Voltage 1.9 3.1 mV Voltage drop across the internal 1.3 kΩ resistor
Power-Good Glitch Filter PWRGDGF 0.3 0.7 1 μs 50 mV overdrive
Minimum Foldback Clamp 200 mV Accuracies included in total sense voltage accuracies
VOUT PIN
Input Current 20 μA VOUT = 20 V
PIN
LATC H
Output Low Voltage V
0.4 V I
OL_LATC H
1.5 V I
Leakage Current 100 nA V
1 µA V
ENABLE PIN No internal pull-up present on this pin
Leakage Current 100 nA V
1 µA V
Input High Voltage VIH 1.1 V
Input Low Voltage VIL 0.8 V
= 0 V; V
FLB
> 1.0 V; V
ISET
≥ 1 V
V
= 1.0 V; V
ISET
= 0.25 V; V
ISET
> 1.65 V; V
ISET
= (SENSE+) + 3 V; I
GAT E
= 0.5 V; V
FLB
> 1.1 V; VSS ≥ 2 V
FLB
> 1.1 V; VSS ≥ 2 V
FLB
driven from 18 mV to 52 mV; selectable via
SENSE
PMBus
driven from 18 mV to 52 mV
SENSE
reaches this level, ISS is enabled, ramping V
SENSE
V
= 0 V
SS
= 1.0 V
ISET
≤ 1.0 V; V
FLB
≤ V
VCAP
= 1 mA
LAT CH
≤ 20 V
FLB
= 1.25 V
ISET
= 5 mA
LAT CH
LAT CH
GPO2
GPO2
≤ 2 V;
= 20 V;
≤ 2 V
= 20 V
output high-Z
LATC H
LATC H
output high-Z
GAT E
= (SENSE+) + 3 V; I
GAT E
= 0.5 V
TIMER
≤ 1 V
= 0.5 V
TIMER
TIMER
= 0 μA; VSS ≥ 1 V
= 0 μA;
GAT E
− V
= 0.5 V
SENSECL
;
Rev. A | Page 5 of 48
ADM1276
GPO2
PWRGD
SENSE
SENSE
SENSE+
ADR
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
GPO2/
Output Low Voltage V
1.5 V I
Leakage Current 100 nA V
1 µA V
PWRGD PIN
Output Low Voltage V
1.5 V I
VCC That Guarantees Valid
Output
Leakage Current 100 nA V
1 µA V
CURRENT AND VOLTAGE
MONITORING
Current Sense Absolute
Error
±0.2 ±0.7 % V
±0.08 % V
±1.0 % V
±0.08 % V
±0.2 % V
±1.0 % V
±0.08 % V
±0.2 % V
±2.8 % V
±0.09 % V
±0.2 % V
±0.7 % V
±0.04 % V
±0.15 % V
±0.75 % V
±0.8 % V
±1.1 % V
±2.0 % V
±4.3 % V
SENSE+/VOUT Absolute
Error
±1.0 % High input range; input voltage ≥ 10 V
ADC Conversion Time Includes time for power multiplication
237 280 µs 1 sample of VIN and IOUT; from command received to valid
360 426 µs 1 sample of VIN, VOUT, and IOUT; from command received to
3753 4233 µs 16 samples of VIN and IOUT averaged; from command
5545 6570 µs 16 samples of VIN, VOUT, and IOUT averaged; from command
Power Multiplication Time 14 µs
ADR PIN
Address Set to 00 0 0.8 V Connect to GND
Input Current for Address 00 −40 −22 μA V
Address Set to 01 135 150 165 kΩ Resistor to GND
Address Set to 10 −1 +1 μA No connect state; maximum leakage current allowed
= 20 mV; 1 sample averaging; TA = 25°C
= 20 mV; 1 sample averaging; TA = 0°C to 65°C
SENSE
= 25 mV; V
SENSE
= 25 mV; V
SENSE
= 25 mV; V
SENSE
= 20 mV; V
SENSE
= 15 mV; V
= 10 mV; V
SENSE
= 5 mV; V
SENSE
= 2.5 mV; V
SENSE
= 12 V
SENSE+
= 12 V; TA = 25°C
SENSE+
= 12 V; TA = 0°C to 65°C
SENSE+
= 12 V
SENSE+
= 12 V
= 12 V
SENSE+
= 12 V
SENSE+
= 12 V
SENSE+
data in register
valid data in register
received to valid data in register
received to valid data in register
= 0 V to 0.8 V
Rev. A | Page 6 of 48
ADM1276
SU;STA
R
t
LOW
t
BUF
t
HD;DAT
t
SU;DAT
t
SU;STA
t
HD;STA
t
HIGH
t
R
t
F
t
SU;STO
PSSP
V
IH
V
IL
V
IH
V
IL
SCL
SDA
09718-002
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Address Set to 11 2 V Connect to VCAP
Input Current for Address 11 3 10 μA V
SERIAL BUS DIGITAL INPUTS
(SDA, SCL)
Input High Voltage VIH 1.1 V
Input Low Voltage VIL 0.8 V
Output Low Voltage VOL 0.4 V IOL = 4 mA
Input Leakage I
−10 +10 μA
LEAK-PIN
−5 +5 μA Device is not powered
Nominal Bus Voltage VDD 2.7 5.5 V 3 V to 5 V ± 10%
Capacitance for SDA, SCL
C
5 pF
PIN
Pins
Input Glitch Filter tSP 0 50 ns
SERIAL BUS TIMING CHARACTERISTICS
Table 2.
Parameter Description Min Typ Max Unit Test Conditions/Comments
f
Clock frequency 400 kHz
SCLK
t
Bus free time 1.3 µs Following the stop condition of a read transaction
BUF
4.7 µs Following the stop condition of a write transaction
t
Start hold time 0.6 µs
HD ;STA
t
Start setup time 0.6 µs
t
Stop setup time 0.6 µs
SU;STO
t
SDA hold time 300 900 ns
HD ;D AT
t
SDA setup time 100 ns
SU ;D AT
t
SCL low time 1.3 µs
LOW
t
SCL high time 0.6 µs
HIGH
1
t
SCL, SDA rise time 20 300 ns
tF SCL, SDA fall time 20 300 ns
1
Note: tR = (V
Timing Diagram
− 0.15) to (V
IL(MAX )
+ 0.15) and tF = 0.9 VDD to (V
IH3V3
− 0.15); where V
IL(MAX )
= 2.1 V, and VDD = 3.3 V.
IH3V3
= 2.0 V to VCAP; must not exceed the maximum allowable
ADR
current draw from VCAP
Figure 2. Serial Bus Timing Diagram
Rev. A | Page 7 of 48
ADM1276
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
VCC Pin −0.3 V to +25 V
UV Pin −0.3 V to +4 V
OV Pin −0.3 V to +4 V
SS Pin −0.3 V to VCAP + 0.3 V
TIMER Pin −0.3 V to VCAP + 0.3 V
VCAP Pin −0.3 V to +4 V
ISET Pin −0.3 V to VCAP + 0.3 V
Pin −0.3 V to +25 V
LATC H
SCL Pin −0.3 V to +6.5 V
SDA Pin −0.3 V to +6.5 V
ADR Pin −0.3 V to VCAP + 0.3 V
ENABLE Pin −0.3 V to +25 V
GPO2/
Pin −0.3 V to +25 V
ALERT2
PWRGD Pin −0.3 V to +25 V
FLB Pin −0.3 V to +25 V
VOUT Pin −0.3 V to +25 V
GAT E Pin (Internal Supply Only)1 −0.3 V to +36 V
SENSE+ Pin −0.3 V to +25 V
SENSE− Pin −0.3 V to +25 V
V
(V
SENSE
SENSE+
− V
) ±0.3 V
SENSE−
Continuous Current into Any Pin ±10 mA
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature, Soldering (10 sec) 300°C
Junction Temperature 150°C
1
The GATE pin has internal clamping circuits to prevent the GATE pin voltage
from exceeding the maximum ratings of a MOSFET with V
internal process limits. Applying a voltage source to this pin externally may
cause irreversible damage.
GSMAX
= 20 V and
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA Unit
20-lead LFCSP (CP-20-9) 30.4 °C/W
ESD CAUTION
Rev. A | Page 8 of 48
ADM1276
1OV
2VCAP
3ISET
4SS
5TIMER
LATCH
ADR
ENABLE
GPO2/ALERT2
SDA
13
14
15
12
11
FLB
VOUT
GND
PWRGD
SCL
SENSE+
VCC
UV
SENSE–
GATE
6
7
8
01
9
81
91
02
71
61
ADM1276-3
TOP VIEW
(Not to S cale)
PIN 1
INDICATOR
NOTES
1. SOLDER THE EXPOSED PADDLE TO
THE BOARD T O IMPRO V E THERMAL
DISSIPATION. THE EXPOSED PADDLE
CAN BE CONNECTE D TO GRO UND.
09718-003
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
19 VCC Positive Supply Input Pin. An undervoltage lockout (UVLO) circuit resets the device when a low supply voltage is
detected. GATE is held low when the supply is below UVLO. During normal operation, this pin should remain
greater than or equal to SENSE+ to ensure that specifications are adhered to. No sequencing is required.
20 UV Undervoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal
comparator to detect whether the supply is under the UV limit.
1 OV Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal
comparator to detect whether the supply is above the OV limit.
2 VCAP Internal Regulated Supply. Place a capacitor with a value of 1 µF or greater on this pin to maintain good
accuracy. This pin can be used as a reference to program the ISET pin voltage.
3 ISET Current Limit. This pin allows the current-limit threshold to be programmed. The default limit is set when this pin
is connected directly to VCAP. To achieve a user defined sense voltage, the current limit can be adjusted using a
resistor divider from VCAP. An external reference can also be used.
4 SS Soft Start Pin. A capacitor is used on this pin to set the soft start ramp profile. The voltage on the SS pin controls
the current sense voltage limit, which controls the inrush current profile.
5 TIMER Timer Pin. An external capacitor, C
, sets an initial timing cycle delay and a fault delay. The GATE pin is pulled
TIMER
low when the voltage on the TIMER pin exceeds the upper threshold.
6
Latch Pin. This pin signals that the device is latching off after an overcurrent fault. The device can be configured
LATC H
for automatic retry after latch-off by connecting this pin directly to the UV or the ENABLE pin.
7 ADR PMBus Address Pin. This pin can be tied to GND, tied to VCAP, remain floating, or tied low through a resistor to
set four different PMBus addresses (see the Device Addressing section).
8 ENABLE Enable Pin. This pin is a digital logic input. This input must be high to allow the ADM1276 hot swap controller to
begin a power-up sequence. If this pin is held low, the ADM1276 is prevented from powering up. There is no
internal pull-up on this pin.
General-Purpose Digital Output/Alert. This is a dual function pin. There is no internal pull-up on this pin. The
ALERT2
function of this pin can be configured to generate an alert signal when one or more fault or warning
ALERT2
conditions are detected. At power-up,
indicates the FET health mode by default.
ALERT2
present on the FLB pin.
the current limit when the source voltage drops. The foldback feature ensures that the power through the FET is
not increased beyond the SOA limits.
9 GPO2/
10 SDA Serial Data Input/Output Pin. Open-drain input/output. Requires an external resistive pull-up.
11 SCL Serial Clock Pin. Open-drain input. Requires an external resistive pull-up.
12 PWRGD Power-Good Signal. Used to indicate that the supply is within tolerance. This signal is based on the voltage
13 FLB Foldback Pin. A foldback resistor divider is placed from the source of the FET to this pin. Foldback is used to reduce
Rev. A | Page 9 of 48
ADM1276
Pin No. Mnemonic Description
14 VOUT Output Voltage. This pin is used to read back the output voltage using the internal ADC. A 1 kΩ resistor should
be inserted in series between the source of a FET and the VOUT pin.
15 GND Ground Pin.
16 GATE Gate Output Pin. This pin is the high-side gate drive of an external N-channel FET. This pin is driven by the FET
drive controller, which uses a charge pump to provide a pull-up current to charge the FET gate pin. The FET drive
controller regulates to a maximum load current by regulating the GATE pin. GATE is held low when the supply is
below UVLO.
17 SENSE− Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog
current limit. The hot swap operation of the ADM1276 controls the external FET gate to maintain the sense
voltage (V
SENSE+
− V
18 SENSE+ Positive Current Sense Input Pin. This pin connects to the main supply input. A sense resistor between the
SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation of the ADM1276 controls
the external FET gate to maintain the sense voltage (V
input voltage using the ADC.
N/A1 EP Exposed Pad. The exposed pad is located on the underside of the LFCSP package. Solder the exposed pad to the
printed circuit board (PCB) to improve thermal dissipation. The exposed pad can be connected to ground.
1
N/A means not applicable.
). This pin also connects to the FET drain pin.
SENSE−
SENSE+
− V
). This pin is also used to measure the supply
SENSE−
Rev. A | Page 10 of 48
ADM1276
0
1
2
3
4
5
I
CC
(mA)
VCC (V)
24681012141618
20
+25°C
+85°C
–40°C
09718-004
0
1
2
3
4
5
–40
–20
0
I
CC
(mA)
TEMPERATURE (°C)
V
CC
= 20V
V
CC
= 12V
V
CC
= 2.95V
20406080
09718-005
0
2
4
6
8
10
12
14
2468121014161820
I
GATEDN_SLOW
(mA)
V
CC
(V)
+25°C
–40°C
+85°C
09718-006
0
2
4
6
8
10
12
14
I
GATEDN_SLOW
(mA)
TEMPERATURE (°C)
V
CC
= 12V
–40
–20020406080
09718-007
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0510152025
I
GATEDN_SLOW
(mA)
V
GATE
(V)
09718-008
–40
–35
–30
–25
–20
–15
–10
–5
0
2468101214161820
I
GATEUP
(µA)
VCC (V)
09718-009
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 4. Supply Current (ICC) vs. Supply Voltage (VCC)
Figure 7. Gate Pull-Down Current (I
GATEDN_SLOW
) vs. Temperature
Figure 5. Supply Current (I
Figure 6. Gate Pull-Down Current (I
) vs. Temperature
CC
GATEDN_SLOW
) vs. Supply Voltage (VCC)
Rev. A | Page 11 of 48
Figure 8. Gate Pull-Down Current (I
Figure 9. Gate Pull-Up Current (I
GATEDN_SLOW
) vs. Gate Voltage (V
) vs. Supply Voltage (VCC)
GATEUP
GATE
)
ADM1276
0
5
10
15
20
25
30
0510152025
I
GATEUP
(µA)
V
GATE
(V)
V
CC
= 12V
V
CC
= 2.95V
09718-010
–40
–35
–30
–25
–20
–15
–10
–5
0
I
GATEUP
(µA)
TEMPERATURE (°C)
V
CC
= 12V
–40
–20020406080
09718-011
0
2
4
6
8
10
12
14
16
220
ΔV
GATE
(V)
VCC (V)
+85°C
+25°C
–40°C
4681012141618
09718-012
0
2
4
6
8
10
12
14
16
ΔV
GATE
(V)
V
CC
(V)
2468101214161820
+25°C
+85°C
–40°C
09718-013
0
2
4
6
8
10
12
14
16
–40–200204060
ΔV
GATE
(V)
TEMPERATURE (°C)
V
CC
= 12V
V
CC
= 20V
V
CC
= 2.95V
80
09718-014
–20
–18
–16
–14
–12
–10
–8
–6
–4
–2
0
–40
I
SS
(µA)
TEMPERATURE (°C)
V
CC
= 12V
–20020406080
09718-015
Figure 10. Gate Pull-Up Current (I
Figure 11. Gate Pull-Up Current (I
) vs. Gate Voltage (V
GATEUP
GATEUP
) vs. Temperature
GATE
)
Figure 13. Gate Drive Voltage (ΔV
Figure 14. Gate Drive Voltage (ΔV
) vs. Supply Voltage (VCC), 5 µA Load
GATE
) vs. Temperature, No Load
GATE
Figure 12. Gate Drive Voltage (ΔV
) vs. Supply Voltage (VCC), No Load
GATE
Figure 15. Soft Start Pull-Up Current (I
) vs. Temperature
SS
Rev. A | Page 12 of 48
ADM1276
–80
–70
–60
–50
–40
–30
–20
–10
0
I
TIMERUPFLT
(µA)
–40
TEMPERATURE (°C)
–20020406080
VCC = 12V
09718-016
–20020406080
–10
–8
–6
–4
–2
0
I
TIMERUPPOR
(µA)
–40
TEMPERATURE (°C)
V
CC
= 12V
09718-017
–40
–20020406080
0
1.5
3.0
4.5
I
TIMERDNRT
(µA)
VCC = 12V
TEMPERATURE (°C)
09718-018
0
100
200
300
400
500
600
700
800
900
1000
1100
TIMER T HRE S HOLD (mV)
–40
TEMPERATURE (°C)
–2002040
6080
LOW THRESHOLD (VCC = 12V)
HIGH THRES HOLD (V
CC
= 12V)
09718-019
–40–200
TEMPERATURE (°C)
20406080
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.
8
0.9
1.0
1.1
1.2
1.3
FOLDBACK T HRE S HOLD (V)
2.95V
12V
20V
09718-020
0
0.5
1.0
1.5
2.0
2.5
3.0
FOLDBACK HYS TERESIS CURRENT (µA)
2.95V
12V
20V
–40–200
TEMPERATURE (°C)
20406080
09718-021
Figure 16. Timer Pull-Up Current, Overcurrent Fault (I
vs. Temperature
Figure 17. Timer Pull-Up Current, Power-On Reset (I
vs. Temperature
TIMERUPFL T
TIMERUPPOR
)
)
Figure 19. Timer Thresholds vs. Temperature
Figure 20. Foldback Threshold vs. Temperature
Figure 18. Timer Pull-Down Current, Retry (I
) vs. Temperature
TIMERDNRT
Figure 21. Foldback Hysteresis Current vs. Temperature
Rev. A | Page 13 of 48
ADM1276
0
20
40
60
80
100
120
140
160
180
200
220
240
FOLDBACK CL AMP (mV)
TEMPERATURE (°C)
V
CC
= 12V
–40
–20020406080
09718-022
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
220
OC RESPONSE TIME (ns)
VCC (V)
4681012141618
+85°C
–40°C
+25°C
09718-023
0
25
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
OC RESPONSE TIME (ns)
VCC (V)
220
4681012141618
+85°C
+25°C
–40°C
09718-024
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
220
V
CBOS
(mV)
VCC (V)
–40°C
+85°C
+25°C
4681012141618
09718-025
0
5
10
15
20
25
30
V
SENSECL
(mV)
TEMPERATURE (°C)
–40
–20020406080
V
CC
= 12V
09718-026
0
5
10
15
20
25
30
1.11.
00.90.80.70.60.50.40.30.20.10
V
SENSECL
(mV)
V
FLB
(V)
T
A
= 25°C
09718-027
Figure 22. Foldback Clamp vs. Temperature
Figure 23. Severe Overcurrent Response Time vs. Supply Voltage (VCC),
V
= 0.25 V
ISET
Figure 25. Circuit Breaker Offset (V
) vs. Supply Voltage (VCC)
CBOS
Figure 26. Hot Swap Sense Voltage Current Limit (V
) vs. Temperature
SENSECL
Figure 24. Severe Overcurrent Response Time vs. Supply Voltage (VCC),
V
ISET
= 1 V
Figure 27. Hot Swap Sense Voltage Current Limit (V
vs. Foldback Voltage (V
)
FLB
SENSECL
)
Rev. A | Page 14 of 48
ADM1276
0
5
10
15
20
25
30
35
40
45
50
V
SENSEOC
(mV)
V
CC
(V)
TA = 25°C
2468101214161820
09718-028
15
10
5
0
20
25
30
35
40
45
50
V
SENSEOC
(mV)
VCC = 12V
TEMPERATURE (°C)
–40–20020406080
09718-029
0123456789 10 11 12
0
50
100
150
I
SENSEx
(µA)
V
SENSEx
(V)
09718-030
0
5
10
15
20
0 –2 –4 –6 –8 –10 –12 –14 –16 –18 –20 –22 –24 –26
ΔV
GATE
(V)
I
GATEUP
(µA)
VCC = 2.95V
V
CC
= 12V
VCC = 20V
09718-031
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
012345678910
V
OL_PWRGD
(V)
IOL (mA)
VCC = 2.95V
VCC = 12V
09718-032
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
V
OL
(V)
VCC = 2.95V
VCC = 12V
012345678910
I
OL
(mA)
09718-033
Figure 28. Severe Overcurrent Voltage Threshold (V
vs. Supply Voltage (V
), V
= V
CC
ISET
VCAP
Figure 29. Severe Overcurrent Voltage Threshold (V
vs. Temperature, V
ISET
= V
VCAP
SENSEOC
SENSEOC
)
)
Figure 31. Gate Drive Voltage (ΔV
Figure 32. PWRGD Pin, VOL vs. IOL
) vs. Gate Pull-Up Current (I
GATE
GATEUP
)
Figure 30. SENSE+/SENSE− Input Current (I
) vs. Voltage (V
SENSEx
SENSEx
)
Figure 33.
LATCH
and GPO2/
ALERT2
Digital Outputs, VOL vs. IOL
Rev. A | Page 15 of 48
ADM1276
0
0.5
1.0
1.5
2.0
2.5
3.0
050100
V
VCAP
(V)
I
VCAP
(µA)
+85°C
+25°C
–40°C
09718-034
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
–40–20204060080
UV THRESHOLD (mV)
TEMPERATURE (°C)
V
CC
= 12V
09718-035
–40
TEMPERATURE (°C)
0
100
200
300
400
500
600
700
800
900
1000
1100
1200
OV THRESHOLD (mV)
V
CC
= 12V
–20204060080
09718-036
0
0.5
1.0
1.5
2.0
2.5
3.0
–25–20–15–10–505
V
ADR
(V)
I
ADR
(µA)
00 DECODE01 DECO DE10 DECODE
11 DECODE
09718-037
0
1
2
3
4
5
6
7
8
9
10
051015202530
ACCURACY (%)
SENSE VOLTAGE(mV)
16× AVERAGING
128× AVERAGING
09718-038
Figure 34. VCAP Voltage (V
) vs. VCAP Load (I
VCAP
VCAP
)
Figure 37. ADR Pin Voltage (V
) vs. Current (I
ADR
ADR
)
Figure 35. UV Threshold (UVTH) vs. Temperature
Figure 36. OV Threshold (OV
) vs. Temperature
TH
Rev. A | Page 16 of 48
Figure 38. Worst-Case Current Sense Power Monitor Error vs. Current Sense
Voltage (V
), 0°C to 65°C, V
SENSE
SENSE+
= 12 V
ADM1276
Q
1
GATE
SENSE+
TIMER
TIMER
ADM1276
GND
R
SENSE
SENSE–
VCC
V
CP
2V TO 20V
2.95V
TO
20V
VCAP
IOUT
UV
OV
1.0V
1.0V
VOUT
VOUT
12-BIT
ADC
SCL
SDA
ADR
SENSE+
IOUT
LDO
CHARGE
PUMP
TIMEOUT
GPO2/ALERT2
PWRGD
LATCH
TIMER
ON
TIMER
ON
V
CBOS
SS
CURRENT
LIMIT
FLB
ISET
TIMEOUT
CURRENT-
LIMIT
CONTROL
REF
SELECT
1.0V
GATE
DRIVE/
LOGIC
LOGIC
AND
PMBus
×50
+
+
–
–
+
–
+
–
09718-039
TYPICAL APPLICATION CIRCUIT
Figure 39. Typical Application Circuit
Rev. A | Page 17 of 48
ADM1276
2.95V TO 20V
R
SENSE
Q
1
SENSE–
GND
GATE
VCC
SENSE+
ADM1276
09718-040
2.95V TO 20V
R
SENSE
Q
1
SENSE–
GND
GATE
VCC
330nF
SENSE+
22Ω
ADM1276
09718-041
R
SENSE
Q
1
SENSE–
GND
GATE
VCC
SENSE+
ADM1276
OVERCURRENT
REFERENCE
×50
+
+––
09718-042
THEORY OF OPERATION
When circuit boards are inserted into a live backplane, discharged
supply bypass capacitors draw large transient currents from the
backplane power bus as they charge. These transient currents can
cause permanent damage to connector pins, as well as dips on
the backplane supply that can reset other boards in the system.
The ADM1276 is designed to control the powering on and off
of a system in a controlled manner, allowing a board to be removed
from, or inserted into, a live backplane by protecting it from excess
currents. The ADM1276 can reside on the backplane or on the
removable board.
POWERING THE ADM1276
A supply voltage from 2.95 V to 20 V is required to power the
ADM1276 via the VCC pin. The VCC pin provides the majority
of the bias current for the device; the remainder of the current
needed to control the gate drive and best regulate the V
supplied by the SENSE+ pin.
To ensure correct operation of the ADM1276, the voltage on
the VCC pin must be greater than or equal to the voltage on
the SENSE+ pin. No sequencing of the VCC and SENSE+ rails
is necessary. The SENSE+ pin can be as low as 2 V for normal
operation provided that a voltage of at least 2.95 V is connected
to the VCC pin. In most applications, both the VCC and SENSE+
pins are connected to the same voltage rail, but they are connected via separate traces to prevent accuracy loss in the sense
voltage measurement (see Figure 40).
Figure 40. Powering the ADM1276
To protect the ADM1276 from unnecessary resets due to transient
supply glitches, an external resistor and capacitor can be added,
as shown in Figure 41. Choose the values of these components so
as to provide a time constant that can filter any expected glitches.
The resistor should, however, be small enough to keep voltage
drops due to quiescent current to a minimum. Unless a resistor
is used to limit the inrush current, do not place a supply decoupling
capacitor on the rail before the FET.
voltage is
GS
Rev. A | Page 18 of 48
Figure 41. Transient Glitch Protection Using an RC Network
CURRENT SENSE INPUTS
The load current is monitored by measuring the voltage drop
across an external sense resistor, R
internal current sense amplifier provides a gain of 50 to the
voltage drop detected across R
SENSE
an internal reference and used by the hot swap control logic to
detect when an overcurrent condition occurs.
Figure 42. Hot Swap Current Sense Amplifier
The SENSE± inputs may be connected to multiple parallel
sense resistors, which can affect the voltage drop detected by
the ADM1276. The current flowing through the sense resistors
creates an offset, resulting in reduced accuracy.
To achieve better accuracy, the averaging resistors sum the current
from the nodes of each sense resistor, as shown in Figure 43. The
typical value for the averaging resistors is 10 Ω. The averaging
resistors are chosen to balance the input current to both sense
pins to within 5 µA. This ensures that the same offset is seen by
both sense inputs.
(see Figure 42). An
SENSE
. The result is compared to
ADM1276
Q
1
SENSE–
GND
GATEVCC
SENSE+
BIAS
CURRENT
2.95V
TO 20V
09718-043
R
SENSE
Q
1
SENSE–
GND
GATE
VCC
ISET
SS
FLB
SENSE+
ADM1276
OVERCURRENT
×50
09718-044
SS
FLB
ISET1V
0.2V
0.1V
V
t
CURRENT-LIMIT
REFERENCE
09718-045
ADM1276
VCAP
ISET
C1
GND
09718-046
Figure 43. Connection of Multiple Sense Resistors to the SENSE± Pins
CURRENT-LIMIT REFERENCE
The current-limit reference voltage determines the load current
level to which the ADM1276 limits the current during an overcurrent event. This reference voltage is compared to the gained-up
current sense voltage to determine whether the limit is reached.
An internal current-limit reference selector block continuously
compares the ISET, soft start, and foldback voltages to determine
which voltage is the lowest at any given time; the lowest voltage
is used as the current-limit reference. This ensures that the programmed current limit, ISET, is used in normal operation, and
that the soft start and foldback features reduce the current limit
when required during startup and/or fault conditions.
Figure 45. Interaction of Soft Start, Foldback, and ISET Current Limits
SETTING THE CURRENT LIMIT (ISET)
The maximum current limit is partially determined by selecting
a sense resistor to match the current sense voltage limit on the
controller for the desired load current. However, as currents
become larger, the sense resistor requirements become smaller,
and resolution can be difficult to achieve when selecting the
appropriate sense resistor. The ADM1276 provides an adjustable
current sense voltage limit to handle this issue. The device allows
the user to program the required current sense voltage limit
from 5 mV to 25 mV.
The default value of 20 mV is achieved by connecting the ISET
pin directly to the VCAP pin. This configures the device to use
an internal 1 V reference, which equates to 20 mV at the sense
inputs (see Figure 46).
Figure 44. Current-Limit Reference Selection
The foldback and soft start voltages vary during different modes
of operation and are, therefore, clamped to minimum levels of
200 mV and 100 mV, respectively, to prevent zero current flow
due to the current limit being too low. Figure 45 provides an
example of how the soft start, foldback, and ISET voltages interact
during startup as the ADM1276 is enhancing the FET and charging
the load capacitances. Depending on how the soft start and foldback features are configured, the hand-off point can vary to
ensure that the FET is being operated within the correct limits.
Figure 46. Fixed 20 mV Current Sense Limit
To program the sense voltage from 5 mV to 25 mV, a resistor
divider is used to set a reference voltage on the ISET pin (see
Figure 47).
Rev. A | Page 19 of 48
ADM1276
ADM1276
GND
VCAP
ISET
C1R1
R2
09718-047
ISET
SS
SS
V
tIC×
=
GATE
SENSE+
ADM1276
GND
SENSE–
×50
SS
CURRENT
LIMIT
FLB
ISET
TIMEOUT
CURRENT
LIMIT
CONTROL
REF
SELECT
1.0V
CURRENT
LIMIT
VCAP
10µA
GATE
DRIVE/
LOGIC
+
+
–
–
V
CP
09718-048
FLB (see Figure 45). This change has minimal impact on startup
because the output voltage rises at a similar rate to the SS voltage.
Figure 47. Adjustable 5 mV to 25 mV Current Sense Limit
The VCAP pin has a 2.7 V internal generated voltage that can
be used to set a voltage at the ISET pin. Assuming that V
ISET
equals the voltage on the ISET pin, size the resistor divider to
set the ISET voltage as follows:
V
where V
ISET
= V
SENSE
× 50
SENSE
is the current sense voltage limit.
The VCAP rail can also be used as the pull-up supply for setting
2
the I
C address. Do not use the VCAP pin for any other purpose.
To guarantee accuracy specifications, do not load the VCAP pin
by more than 100 µA.
SOFT START
A capacitor connected to the SS pin determines the inrush
current profile. Before the FET is enabled, the output voltage of
the current-limit reference selector block is clamped at 100 mV.
This, in turn, holds the hot swap sense voltage current limit,
V
, at approximately 2 mV. When the FET receives a
SENSECL
request to turn on, the SS pin is held at ground until the voltage
between the SENSE+ and SENSE− pins (V
circuit breaker voltage, V
V
where V
CB
= V
CBOS
− V
SENSECL
is typically 0.88 mV, making VCB = 1.12 mV.
CBOS
.
CB
When the load current generates a sense voltage equal to V
a 10 µA current source is enabled, which charges the SS capacitor and results in a linear ramping voltage on the SS pin. The
current-limit reference also ramps up accordingly, allowing the
regulated load current to ramp up while avoiding sudden
transients during power-up. The SS capacitor value is given by
where:
I
= 10 µA.
SS
t = SS ramp time.
For example, a 10 nF capacitor gives a soft start time of 1 ms.
Note that the SS voltage may intersect with the FLB (foldback)
voltage, and the current-limit reference may change to follow
) reaches the
SENSE
FOLDBACK
Foldback is a method to actively reduce the current limit as the
voltage drop across the FET increases. It keeps the power across
the FET to a minimum during power-up, overcurrent, or shortcircuit events. It also avoids the need to oversize the FET to
accommodate worst-case conditions, resulting in board size and
cost savings.
The ADM1276 detects the voltage drop across the FET by
looking at a resistor divided version of the output voltage. It is
assumed that the supply voltage remains constant and within
tolerance. The device, therefore, relies on the principle that the
drain of the FET is at the maximum expected supply voltage,
and that the magnitude of the output voltage is relative to that
of the V
voltage to the FLB pin, a relationship from V
to V
Design the resistor divider to output a voltage equal to ISET
,
CB
Rev. A | Page 20 of 48
when V
below the working tolerance of the supply rail. As V
to drop, the current-limit reference follows V
now the lowest voltage input to the current-limit reference
selector block. This results in a reduction of the current limit
and, therefore, the regulated load current. To prevent complete
current flow restriction, a clamp becomes active when the
current-limit reference reaches 200 mV. The current limit
cannot drop below this level.
To su i t the SOA characteristics of a particular FET, the required
minimum current for this clamp varies from design to design.
However, the current-limit reference fixes this clamp at 200 mV,
which equates to 4 mV at the sense resistor. Therefore, the main
ISET voltage can be adjusted to align this clamp to the required
percentage current reduction. For example, if ISET equals 0.8 V,
the clamp can be set at 25% of the maximum current.
Figure 48. Soft Start
of the FET. Using a resistor divider from the output
DS
, and thus VDS,
OUT
can be derived.
FLB
falls below the desired level. This should be well
OUT
OUT
because it is
FLB
continues
ADM1276
A100
)(
A3µ
×−
+
µ
×
=
TIMERTIMERLTIMERHTIMERTIMERH
INITIAL
CVVCV
t
TIMER
The TIMER pin handles several timing functions with an
external capacitor, C
V
(0.2 V) and V
TIMERL
sources: a 3 μA pull-up, a 60 μA pull-up, a 2 μA pull-down, and
a 100 μA pull-down.
These current and voltage levels, together with the value of
C
chosen by the user, determine the initial timing cycle
TIMER
time, the fault current-limit time, and the hot swap retry duty
cycle. The TIMER pin capacitor value is determined using the
following equation:
C
= (tON × 60 μA)/V
TIMER
where t
is the time that the FET is allowed to spend in regu-
ON
lation at the set current limit.
The choice of FET is based on matching this time with the SOA
requirements of the FET. Foldback can be used to simplify the
selection.
When VCC is connected to the backplane supply, the internal
supply of the ADM1276 must be charged up. In a very short
time, the internal supply is fully charged up and, because the
undervoltage lockout (UVLO) voltage is exceeded at VCC, the
device emerges from reset. During this first short reset period,
the GAT E and TIMER pins are both held low.
The ADM1276 then goes through an initial timing cycle. The
TIMER pin is pulled high with 3 μA. When the TIMER pin
reaches the V
TIMERH
initial timing cycle is complete. The 100 μA current source then
pulls down the TIMER pin until it reaches V
initial timing cycle duration is related to C
equation:
For example, a 100 nF capacitor results in a delay of approximately 34 ms. If the UV and OV inputs indicate that the supply
is within the defined window of operation when the initial timing
cycle terminates, the device is ready to start a hot swap operation.
When the voltage across the sense resistor reaches the circuit
breaker trip voltage, V
activated, and the gate begins to regulate the current at the current
limit. This initiates a ramp-up on the TIMER pin. If the sense
voltage falls below this circuit breaker trip voltage before the
TIMER pin reaches V
the 2 µA pull-down is enabled.
The circuit breaker trip voltage is not the same as the hot swap
sense voltage current limit. There is a small circuit breaker offset,
V
, which means that the timer actually starts a short time
CBOS
before the current reaches the defined current limit.
. The two comparator thresholds are
TIMER
(1 V). There are four timing current
TIMERH
TIMERH
threshold (1.0 V), the first portion of the
(0.2 V). The
TIMERL
by the following
TIMER
, the 60 µA timer pull-up current is
CB
, the 60 µA pull-up is disabled and
TIMERH
However, if the overcurrent condition is continuous and the
sense voltage remains above the circuit breaker trip voltage, the
60 µA pull-up remains active and the FET remains in regulation.
This allows the TIMER pin to reach V
GATE shutdown. On the ADM1276, the
and initiate the
TIMERH
LATCH
pin is pulled
low immediately.
In latch-off mode, the TIMER pin is switched to the 2 µA
pull-down when it reaches the V
threshold. The
TIMERH
LATCH
pin remains low. While the TIMER pin is being pulled down,
the hot swap controller remains off and cannot be turned back on.
When the voltage on the TIMER pin goes below the V
TIMERL
threshold, the hot swap controller can be reenabled by toggling
the UV pin or by using the PMBus OPERATION command to
toggle the on bit from on to off and then on again.
HOT SWAP RETRY DUTY CYCLE
The ADM1276 turns off the FET after an overcurrent fault and
then uses the capacitor on the TIMER pin to provide a delay before
automatically retrying the hot swap operation. To configure the
ADM1276 for autoretry mode, the
LATCH
pin is tied to either
the UV pin or to the ENABLE pin. Note that a pull-up resistor
is required on the
LATCH
pin.
When an overcurrent fault occurs, the capacitor on the TIMER
pin is charged with a 60 μA pull-up current. When the TIMER
pin reaches V
LATCH
pin is tied to the UV pin or the ENABLE pin for auto-
, the GATE pin is pulled down. When the
TIMERH
retry mode, the TIMER pin is pulled down with a 2 μA current
sink. When the TIMER pin reaches V
(0.2 V), it automatically
TIMERL
restarts the hot swap operation.
The duty cycle of this automatic retry cycle is set by the ratio
of 2 µA/60 µA, which approximates to being on about 4% of
the time. The value of the timer capacitor determines the on
time of this cycle, which is calculated as follows:
t
= V
ON
= (V
t
OFF
TIMERH
TIMERH
× (C
− V
TIMER
TIMERL
/60 μA)
) × (C
TIMER
/2 μA)
A 100 nF capacitor on the TIMER pin gives an on time of 1.67 ms
and an off time of 40 ms. The device retries indefinitely in this
manner and can be disabled manually by holding the UV or
ENABLE pin low, or by disconnecting the
LATCH
pin. To p re vent thermal stress, an RC network can be used to extend the
retry time to any desired level.
FET GATE DRIVE CLAMPS
The charge pump used on the GATE pin is capable of driving
the pin to V
above the SENSE± pins and less than 31 V. These clamps ensure
that the maximum V
+ (2 × VCC), but it is clamped to less than 14 V
CC
rating of the FET is not exceeded.
GS
Rev. A | Page 21 of 48
ADM1276
GATE
SENSE+
ADM1276
GND
SENSE–
GATE
DRIVE
R
SENSE
Q1
V
IN
1V
1V
IOUT
UV
OV
VCC
×50
+–
–
+
+
–
09718-049
V
IN
R1
D1
R2
EN
UV
SYSTEM CONTROL
ADM1276
09718-050
V
OUT
FLB
2μA
R1
R2
R3
PWRGD
1.3kΩ
SWITCH IS ON WHEN
COMPARATOR OUTPUT IS HIGH
1.1 × V
ISET
09718-051
FAST RESPONSE TO SEVERE OVERCURRENT
The ADM1276 features a separate high bandwidth current
sense amplifier that is used to detect a severe overcurrent that
is indicative of a short-circuit condition. A fast response time
allows the ADM1276 to handle events of this type that could
otherwise cause catastrophic damage if not detected and acted
on very quickly. The fast response circuit ensures that the
ADM1276 can detect an overcurrent event at approximately
200% to 250% of the normal current limit (ISET) and can
respond to and control the current within 1 µs, in most cases.
UNDERVOLTAGE AND OVERVOLTAGE
The ADM1276 monitors the supply voltage for undervoltage
(UV) and overvoltage (OV) conditions. The UV and OV pins
are connected to the input of an internal voltage comparator,
and its voltage level is internally compared with a 1 V voltage
reference.
Figure 49 illustrates the voltage monitoring input connections.
An external resistor network divides the supply voltage for monitoring. An undervoltage event is detected when the voltage
connected to the UV pin falls below 1 V, and the gate is shut
down using the 10 mA pull-down device. Similarly, when an
overvoltage event occurs and the voltage on the OV pin exceeds
1 V, the gate is shut down using the 10 mA pull-down device.
ENABLE INPUT
The ADM1276 provides a dedicated ENABLE digital input pin.
The ENABLE pin allows the ADM1276 to remain off by using a
hardware signal, even when the voltage on the UV pin is above
1.0 V and the voltage on the OV pin is less than 1.0 V. Although
the UV pin can be used to provide a digital enable signal, using
the ENABLE pin for this purpose means that the ability to
monitor for undervoltage conditions is not lost.
In addition to the conditions for the UV and OV pins, the
ADM1276 ENABLE input pin must be high for the device
to begin a power-up sequence.
A similar function can be achieved using the UV pin directly.
Alternatively, if the UV divider function is still required, the
configuration shown in Figure 50 can be used.
Figure 49. Undervoltage and Overvoltage Supply Monitoring
Rev. A | Page 22 of 48
Figure 50. Using the UV Pin as an Enable
Diode D1 prevents the external driver pull-up from affecting
the UV threshold. Select Diode D1 using the following criteria:
(V
× D1) + (VOL × EN) << 1.0 V (IF = VIN/R1)
F
Ensure that the EN sink current does not exceed the specified V
OL
value. If the open-drain device has no pull-up, the diode is not
required.
POWER GOOD
The power good (PWRGD) output can be used to indicate
whether the output voltage is above a user-defined threshold
and can, therefore, be considered good. The PWRGD output is
derived using the FLB resistor network, composed of R1 and R2
(see Figure 51).
The PWRGD pin is an open-drain output that pulls low when
the voltage at the FLB pin is lower than 1.1 × V
When the voltage at the FLB pin is above this threshold (indicating
that the output voltage has risen), the open-drain pull-down is
disabled, allowing PWRGD to be pulled high. PWRGD is
guaranteed to be in a valid state for VCC ≥ 1 V.
Hysteresis on the FLB pin is provided by a 2 μA internal current
source that is switched on when the V
input voltage exceeds the
FLB
input threshold. The current source is disconnected when V
drops below the foldback threshold voltage minus the hysteresis
voltage. Resistor R3 is internal to the ADM1276. The hysteresis
voltage at the FLB pin can be varied by adjusting the parallel
combination of Resistor R1 and Resistor R2.
Figure 51. Generation of PWRGD Signal
(power bad).
ISET
OUT
ADM1276
VOUT MEASUREMENT
The VOUT pin on the ADM1276 can be used to provide an
alternate voltage for the power monitor to measure. The user
can choose to measure the voltage at the SENSE+ pin or the
voltage at the VOUT pin, using either the low or high input
voltage range.
If the VOUT pin is to be used to measure the output voltage after
the FE T, insert a 1 kΩ resistor in series between the source of
the FET and the VOUT pin. This resistor provides some separation between the ADM1276 and the FET source during a fault
condition; thus, ADM1276 operation is not affected.
FET HEALTH
The ADM1276 provides a method of detecting a shorted pass
FET. The FET health status can be used to generate an alert on
the GPO2/
ALERT2
ated on the GPO2/
pin. By default at power-up, an alert is gener-
ALERT2
pin of the ADM1276 when the FET
health status indicates that a bad FET is present. FET health is
considered bad if all of the following conditions are true:
•The ADM1276 is holding the FET off, for example, during
the initial power-on cycle time.
• V
• V
> 2 mV.
SENSE
< ~1 V, that is, less than the FET gate threshold.
GATE
POWER MONITOR
The ADM1276 features an integrated ADC that accurately measures the current sense voltage, the input voltage, and (optionally)
the output voltage. The measured input voltage and current being
delivered to the load are multiplied to give a power value that can
be read back. Each power value is also added to an accumulator
that can be read back to allow an external device to calculate the
energy consumption of the load.
The ADM1276 can report the measured current, input voltage,
and the output voltage. The PEAK_IOUT, PEAK_VIN, and
PEAK_VOUT commands can be used to read the highest peak
current or voltage since the value was last cleared.
An averaging function is provided for voltage and current that
allows a number of samples to be averaged by the ADM1276.
This function reduces the need for postprocessing of sampled
data by the host processor. The number of samples that can be
averaged is 2
N
, where N is in the range of 0 to 7.
The power monitor current sense amplifier is bipolar and can
measure both positive and negative currents. The power monitor
amplifier has an input range of ±25 mV.
Two input voltage ranges are available and can be selected using
the PMBus interface: 0 V to 6 V (low input range) and 0 V to
20 V (high input range).
The two basic modes of operation for the power monitor are
single shot and continuous. In single shot mode, the power
monitor samples the input voltage and current a number of
times, depending on the averaging value selected by the user.
The ADM1276 returns a single value corresponding to the
average voltage and current measured. When configured for
continuous mode, the power monitor continuously samples
voltage and current, making the most recent sample available
to be read.
The single shot mode can be triggered in a number of ways.
The simplest is by selecting the single shot mode using the
PMON_CONFIG command and writing to the convert bit
using the PMON_CONTROL command. The convert bit can
also be written as part of a PMBus group command. Using a
group command allows multiple devices to be written to as part
of the same I
2
C bus transaction, with all devices executing the
command when the stop condition appears on the bus. In this
way, several devices can be triggered to sample at the same time.
Each time a current sense and input voltage measurements are
taken, a power calculation is performed, multiplying the two
measurements together. This can be read from the device using
the READ_PIN command, returning the input power.
At the same time, the calculated power value is added to a
power accumulator register, that may increment a rollover
counter if the value exceeds the maximum accumulator value,
and that also increments a power sample counter.
The power accumulator and power sample counter are read
using the same READ_EIN command to ensure that the
accumulated value and sample count are from the same point
in time. The bus host reading the data assigns a timestamp to
when the data is read. By calculating the time difference between
consecutive uses of READ_EIN, and determining the delta in
power consumed, it is possible for the host to determine the
total energy consumed over that period.
Rev. A | Page 23 of 48
ADM1276
PMBus INTERFACE
The I2C bus is a common, simple serial bus used by many devices
to communicate. It defines the electrical specifications, the bus
timing, the physical layer, and some basic protocol rules.
SMBus is based on I
fault tolerant bus. Functions such as bus timeout and packet
error checking are added to help achieve this robustness, along
with more specific definitions of the bus messages used to read
and write data to devices on the bus.
PMBus is layered on top of SMBus and, in turn, on I
SMBus defined bus messages, PMBus defines a set of standard
commands that can be used to control a device that is part of a
power chain.
The ADM1276 command set is based upon the PMBus™ Power System Management Protocol Specification, Part I and Part II,
Revision 1.2. This version of the standard is intended to provide
a common set of commands for communicating with dc-to-dc
type devices. However, many of the standard PMBus commands
can be mapped directly to the functions of a hot swap controller.
Part I and Part II of the PMBus standard describe the basic
commands and how they can be used in a typical PMBus setup.
The following sections describe how the PMBus standard and
the ADM1276 specific commands are used.
2
C and aims to provide a more robust and
2
C. Using the
DEVICE ADDRESSING
The ADM1276 is available in one model: the ADM1276-3. The
PMBus address is 7 bits in size. The upper 5 bits (MSBs) of the
address word are fixed. The base address for the ADM1276 is
01000xx (0x20).
The ADM1276 has a single ADR pin that is used to select one of
four possible addresses. The ADR pin connection selects the
lowest two bits (LSBs) of the 7-bit address word (see Tabl e 6).
Table 6. PMBus Addresses and ADR Pin Connection
Value of Address LSBs ADR Pin Connection
00 Connect to GND
01 150 kΩ resistor to GND
10 No connection (floating)
11 Connect to VCAP
SMBus PROTOCOL USAGE
All I2C transactions on the ADM1276 are done using SMBus
defined bus protocols. The following SMBus protocols are
implemented by the ADM1276:
• Send byte
• Receive byte
• Write byte
• Read byte
• Write word
• Read word
• Block read
PACKET ERROR CHECKING
The ADM1276 PMBus interface supports the use of the packet
error checking (PEC) byte that is defined in the SMBus standard.
The PEC byte is transmitted by the ADM1276 during a read
transaction or sent by the bus host to the ADM1276 during a
write transaction. The ADM1276 supports the use of PEC with
all the SMBus protocols that it implements.
The use of the PEC byte is optional. The bus host can decide
whether to use the PEC byte with the ADM1276 on a messageby-message basis. There is no need to enable or disable PEC in
the ADM1276.
The PEC byte is used by the bus host or the ADM1276 to detect
errors during a bus transaction, depending on whether the transaction is a read or a write. If the host determines that the PEC
byte read during a read transaction is incorrect, it can decide to
repeat the read if necessary. If the ADM1276 determines that the
PEC byte sent during a write transaction is incorrect, it ignores
the command (does not execute it) and sets a status flag.
Within a group command, the host can choose to send or not
send a PEC byte as part of the message to the ADM1276.
Rev. A | Page 24 of 48
ADM1276
SPAAWSLAVEADDRESSDATA BYTE
SPAAWSLAVEADDRESSDATA BYTEPEC
A
MASTER TO SLAVE
SLAVE TO MASTER
09718-052
SPAARSLAVEADDRESSDATA BYTE
SPAARSLAVEADDRESSDATA BYTEPEC
MASTER TO SLAVE
SLAVE TO MASTER
A
09718-053
SAAWSLAVE ADDRESSCOMM AND CODEDATA BYTEPA
SAAWSLAVE ADDRESSCOMM AND CODEDATA BYTE
PAPECA
MASTER TO SLAVE
SLAVE TO MASTER
09718-054
A
SLAVEADDRESS
R
DATA BYTE
Sr
A
A
S
A
AWSLAVE ADDRESSCOMMAND CODE
PA
PEC
SAAWSLAVE ADDRESSCOMMAND CODESLAVEADDRESS
PRDATA BYTE
Sr
A
MASTER TO SLAVE
SLAVE TO MASTER
09718-055
P
SAAWSLAVE ADDRESSCOMMAND CODEDATA BYTE LOW
AA
SAAWSLAVE ADDRESSCOMMAND CODEDATA BYTE LOW
ADATA BYTE HIGH
DATA BYTE HIGH
A
PA
PEC
MASTER TO SLAVE
SLAVE TO MASTER
09718-056
W
SMBus MESSAGE FORMATS
Figure 52 to Figure 60 show all the SMBus protocols supported
by the ADM1276, along with the PEC variant. In these figures,
unshaded cells indicate that the bus host is actively driving the
bus; shaded cells indicate that the ADM1276 is driving the bus.
Figure 52 to Figure 60 use the following abbreviations:
S is the start condition.
Sr is the repeated start condition.
P is the stop condition.
R is the read bit.
is the write bit.
A is the acknowledge bit (0).
A
is the acknowledge bit (1).
“A” represents the acknowledge bit. The acknowledge bit is typically active low (Logic 0) if the transmitted byte is successfully
received by a device. However, when the receiving device is the
bus master, the acknowledge bit for the last byte read is a Logic 1,
indicated by
A
.
Figure 52. Send Byte and Send Byte with PEC
Figure 53. Receive Byte and Receive Byte with PEC
Figure 54. Write Byte and Write Byte with PEC
Figure 55. Read Byte and Read Byte with PEC
Figure 56. Write Word and Write Word with PEC
Rev. A | Page 25 of 48
ADM1276
SrASLAVEADDRESSARSAWSLAVEADDRESSCOM M AND CODE
A
DATA BYTE LOW
PA
A
A
DATA BYTE HIGH
SrASLAVEADDRESSARSAWSLAVEADDRESSCOM M AND CODE
A
DATA BYTE LOW
DATA BYTE HIGH
P
PEC
MASTER TO SLAVE
SLAVE TO MASTER
09718-057
SrASLAVEADDRESS
AR
SAWSLAVEADDRESSCOMM AND CODE
A
BYTE COUNT = N
A
DATA BYTE 1
P
DATA BYTE NA
DATA BYTE 2
SrASLAVEADDRESS
ARSAWSLAVEADDRESSCOMMAND CODE
A
BYTE COUNT = N
A
DATA BYTE 1
ADATA BYTE N
PPECA
DATA BYTE 2
MASTER TO SLAVE
SLAVE TO
MASTER
A
A
09718-058
MASTER TO SLAVE
SLAVE TO
MASTER
ALOW DATA BYTEASAWDEVICE 1 ADDRESSCO M M AND CODE 1
AHIGH D
ATA BYTE
ONE OR MO RE DATA BYTES
ALOW DATA BYTEASrAWDEVICE 2 ADDRESSCOMMAND CODE 2
AHIGH DATA BYTE
ONE OR MO RE DATA BYTES
ALOW DATA BYTE
ASrAWDEVICE N ADDRESSCOMMAND CODE N
A PHIGH DATA BYTE
ONE OR MO RE DATA BYTES
09718-059
MASTER TO SLAVE
SLAVE TO MASTER
APEC 1
P
ALOW DATA BY TE
ASAWDEVICE 1 ADDRESSCOMMAND CODE 1
AHIGH DATA BYTE
ONE OR MO RE DATA BYTES
APEC 2
ALOW DATA BY TE
ASrAWDEVICE 2 ADDRESSCOMM AND CODE 2
AHIGH DATA BYTE
ONE OR MO RE DATA BYTES
A
PEC N
ALOW DATA BY TEASrAWDEVICE N ADDRESSCOMM AND CODE N
AHIGH DATA BYTE
ONE OR MO RE DATA BYTES
09718-060
Figure 57. Read Word and Read Word with PEC
Figure 58. Block Read and Block Read with PEC
Figure 59. Group Command
GROUP COMMANDS
The PMBus standard defines what are known as group
commands. Group commands are single bus transactions that
send commands or data to more than one device at the same
time. Each device is addressed separately, using its own address;
there is no special group command address. A group command
transaction can contain only write commands that send data to
a device. It is not possible to use a group command to read data
from devices.
Figure 60. Group Command with PEC
Rev. A | Page 26 of 48
From an I
2
C protocol point of view, a normal write command
consists of the following:
2
•I
C start condition.
•Slave address bits and a write bit (followed by an
acknowledge from the slave device).
•One or more data bytes (each of which is followed by an
acknowledge from the slave device).
2
•I
C stop condition to end the transaction.
ADM1276
A group command differs from a nongroup command in that
after the data is written to one slave device, a repeated start
condition is placed on the bus followed by the address of the
next slave device and data. This continues until all of the
devices have been written to, at which point the stop condition
is placed on the bus by the master device.
The format of a group command and a group command with
PEC is shown in Figure 59 and Figure 60.
Each device that is written to as part of the group command
does not immediately execute the command written. The device
must wait until the stop condition appears on the bus. At that
point, all devices execute their commands at the same time.
Using a group command, it is possible, for example, to turn
multiple PMBus devices on or off simultaneously. In the case of
the ADM1276, it is also possible to issue a power monitor
command that initiates a conversion, causing multiple ADM1276
devices to sample together at the same time.
HOT SWAP CONTROL COMMANDS
OPERATION Command
The GATE pin that drives the FET is controlled by a dedicated
hot swap state machine. The UV and OV input pins, the TIMER
and SS pins, and the current sense all feed into the state machine
and they control when and how strongly the gate is turned off.
It is also possible to control the hot swap GATE output using
commands over the PMBus interface. The OPERATION
command can be used to request the hot swap output to turn
on. However, if the UV pin indicates that the input supply is less
than required, the hot swap output is not turned on, even if the
OPERATION command indicates that the output should be
enabled.
If the OPERATION command is used to disable the hot swap
output, the GATE pin is held low, even if all hot swap state
machine control inputs indicate that it can be enabled.
The default state of Bit 7 (also named the on bit) of the
OPERATION command is 1; therefore, the hot swap output
is always enabled when the ADM1276 emerges from UVLO.
If the on bit is never changed, the UV input or the ENABLE
input is the hot swap master on/off control signal.
By default at power-up, the OPERATION command is disabled
and must be enabled using the DEVICE_CONFIG command.
This prevents inadvertent shutdowns of the hot swap controller
by software.
If the on bit is set to 0 while the UV signal is high, the hot swap
output is turned off. If the UV signal is low or if the OV signal
is high, the hot swap output is already off and the status of the
on bit has no effect.
If the on bit is set to 1, the hot swap output is requested to turn
on. If the UV signal is low or if the OV signal is high, setting the
on bit to 1 has no effect, and the hot swap output remains off.
Rev. A | Page 27 of 48
It is possible to determine at any time whether the hot swap output
is enabled using the STATUS_BYTE or the STATUS_WORD
command (see the Status Commands section).
The OPERATI ON command can also clear any latched faults in
the status registers. To clear latched faults, set the on bit to 0 and
then reset it to 1.
DEVICE_CONFIG Command
The DEVICE_CONFIG command configures certain settings
within the ADM1276, for example, enabling or disabling foldback
in the hot swap controller, or modifying the duration of the
severe overcurrent glitch filter. This command is also used to
configure the polarity of the second IOUT current warnings.
The OPERATION command is disabled at power-up. If the
OPERATION command is received, the ADM1276 responds
with a no acknowledge. To allow use of the OPERATION
command, the OPERATION_CMD_EN bit must be set via
the DEVICE_CONFIG command.
POWER_CYCLE Command
The POWER_CYCLE command can be used to request that the
ADM1276 be turned off for ~4 seconds and then turned back on.
This command can be useful if the processor that controls the
ADM1276 is also powered off when the ADM1276 is turned off.
This command allows the processor to request that the ADM1276
turn off and on again as part of a single command.
ADM1276 INFORMATION COMMANDS
CAPABILITY Command
The CAPABILITY command can be used by host processors
to determine the I
ADM1276. The features that can be reported include the maximum bus speed, whether the device supports the packet error
checking (PEC) byte, and the SMBAlert reporting function.
2
C bus features that are supported by the
PMBUS_REVISION Command
The PMBUS_REVISION command reports the version of Part I
and Part II of the PMBus standard.
MFR_ID, MFR_MODEL, and MFR_REVISION Commands
The MFR_ID, MFR_MODEL, and MFR_REVISION commands
return ASCII strings that can be used to facilitate detection and
identification of the ADM1276 on the bus.
These commands are read using the SMBus block read message
type. This message type requires that the ADM1276 return a
byte count corresponding to the length of the string data that is
to be read back.
STATUS COMMANDS
The ADM1276 provides a number of status bits that are used
to report faults and warnings from the hot swap controller and
the power monitor. These status bits are located in six different
registers that are arranged in a hierarchy. The STATUS_BYTE
and STATUS_WORD commands provide 8 bits and 16 bits of
high level information, respectively. The STATUS_BYTE and
STATUS_WORD commands contain the most important status
ADM1276
bits, as well as pointer bits that indicate whether any of the four
other status registers need to be read for more detailed status
information.
In the ADM1276, a particular distinction is made between
faults and warnings. A fault is always generated by the hot swap
controller and is defined by hardware component values. Three
events can generate a fault:
•Overcurrent condition that causes the hot swap timer to
time out.
• Overvoltage condition on the OV pin.
• Undervoltage condition on the UV pin.
When a fault occurs, the hot swap controller always takes
some action, usually to turn off the GATE pin, which is
driving the FET. A fault can also generate an SMBAlert on
the GPO2/
All warnings in the ADM1276 are generated by the power
monitor, which samples the voltage and current and then
compares these measurements to the threshold values set by the
various limit commands. A warning has no effect on the hot
swap controller, but it may generate an SMBAlert on the
GPO2/
When a status bit is set, it always means that the status condition—
fault or warning—is active or was active at some point in the past.
When a fault or warning bit is set, it is latched until it is explicitly
cleared using either the OPERATION or the CLEAR_FAULTS
command. Some other status bits are live, that is, they always
reflect a status condition and are never latched.
ALERT2
ALERT2
pin.
output pin.
STATUS_BYTE and STATUS_WORD Commands
The STATUS_BYTE and STATUS_WORD commands can
be used to obtain a snapshot of the overall part status. These
commands indicate whether it is necessary to read more
detailed information using the other status commands.
The low byte of the word returned by the STAT U S _ WORD
command is the same byte returned by the STATUS_BYTE
command. The high byte of the word returned by the
STATUS_WORD command provides a number of bits that
can be used to determine which of the other status commands
needs to be issued to obtain all active status bits.
STATUS_INPUT Command
The STATUS_INPUT command returns a number of bits
relating to voltage faults and warnings on the input supply.
STATUS_VOUT Command
The STATUS_VOUT command returns a number of bits
relating to voltage faults and warnings on the output supply.
STATUS_IOUT Command
The STATUS_IOUT command returns a number of bits
relating to current faults and warnings on the output supply.
STATUS_MFR_SPECIFIC Command
The STATUS_MFR_SPECIFIC command is a standard PMBus
command, but the contents of the byte returned are specific to
the ADM1276.
CLEAR_FAULTS Command
The CLEAR_FAULTS command is used to clear fault and
warnings bits when they are set. Fault and warnings bits are
latched when they are set. In this way, a host can read the bits
any time after the fault or warning condition occurs and
determine which problem actually occurred.
If the CLEAR_FAULTS command is issued and the fault or
warning condition is no longer active, the status bit is cleared.
If the condition is still active—for example, if an input voltage
is below the undervoltage threshold of the UV pin—the
CLEAR_FAULTS command attempts to clear the status bit, but
that status bit is immediately set again.
GPO AND ALERT PIN SETUP COMMANDS
A multipurpose pin is provided on the ADM1276:
ALERT2
GPO2/
over the PMBus in one of three output modes, as follows:
• General-purpose digital output.
• Output for generating an SMBAlert when one or more
fault/warning status bits become active in the PMBus
status registers.
•Digital comparator.
In digital comparator mode, the current, voltage, and power
warning thresholds are compared to the values read or
calculated by the ADM1276. The comparison result sets the
output high or low according to whether the value is greater or less
than the warning threshold that has been set.
For an example of how to configure this pin to generate an
SMBAlert and how to respond and clear the condition, see the
Example Use of SMBUS Alert Response Address section.
. The GPO2/
ALERT2
pin can be configured
ALERT2_CONFIG Command
Using combinations of bit masks, the ALERT2_CONFIG
command can be used to select the status bits that, when set,
generate an SMBAlert signal to a processor, or control the
digital comparator mode. They can also be used to set a GPO
mode on the GPO2/
control. If this mode is set, the SMBAlert masking bits are
ignored.
ALERT2
pin, so that it is under software
POWER MONITOR COMMANDS
The ADM1276 provides a high accuracy, 12-bit current and
voltage power monitor. The power monitor can be configured
in a number of different modes of operation and can run in
either continuous mode or single shot mode with a number
of different sample averaging options.
Rev. A | Page 28 of 48
ADM1276
The power monitor can measure the following quantities:
• Input voltage (VIN).
• Output voltage (VOUT).
• Output current (IOUT).
The following quantities are then calculated:
• Input power (PIN).
• Input energy (EIN).
PMON_CONFIG Command
The power monitor can run in a number of different modes with
different input voltage range settings. The PMON_CONFIG
command is used to set up the power monitor.
The settings that can be configured are as follows:
• Single shot or continuous sampling.
• VOUT sampling enable/disable.
• Volt a ge input range.
• Current and voltage sample averaging.
Modifying the power monitor settings while the power monitor
is sampling is not recommended. To ensure correct operation of
the device and to avoid any potential spurious data or the
generation of status alerts, stop the power monitor before any of
these settings are changed.
PMON_CONTROL Command
Power monitor sampling can be initiated via hardware or via
software using the PMON_CONTROL command. This command
can be used with single shot or continuous mode.
READ_VIN, READ_VOUT, and READ_IOUT Commands
The ADM1276 power monitor measures the voltage developed
across the sense resistor to provide a current measurement. The
input voltage from the SENSE+ pin is always measured, and the
output voltage present on the VOUT pin is available if enabled
with the PMON_CONFIG command.
READ_PIN, READ_PIN_EXT, READ_EIN, and
READ_EIN_EXT Commands
The 12-bit VIN input voltage and 12-bit IOUT current measurement values are multiplied by the ADM1276 to give the input
power value. This is accomplished by using fixed point
arithmetic, and produces a 24-bit value. It is assumed that the
numbers are in the 12.0 format, meaning that there is no
fractional part. Note that only positive IOUT values are used to
avoid returning a negative power.
This 24-bit value can be read from the ADM1276 using the
READ_PIN_EXT command, where the most significant bit
(MSB) is always a zero because PIN_EXT is a twos complement
binary value that is always positive.
The sixteen most significant bits of the 24-bit value are used as
the value for PIN. The MSB of the 16-bit PIN word is always
zero, as PIN is a twos complement binary value, that is always
positive.
Each time a power calculation is done, the 24-bit power value is
added to a 24-bit energy accumulator register. This is a twos
complement representation as well, so the MSB is always zero.
Each time this energy accumulator register rolls over from
0x7FFFFF to 0x000000, a 16-bit rollover counter is
incremented. The rollover counter is straight binary, with a
maximum value of 0xFFFF before it rolls over.
A 24-bit straight binary power sample counter is also
incremented by 1 each time a power value is calculated and
added to the energy accumulator.
These registers can be read back using one of two commands,
depending on the level of accuracy required for the energy
accumulator and the desire to limit the frequency of reads from
the ADM1276.
A bus host can read these values, and by calculating the delta in
the energy accumulated, the delta in the number of samples,
and the time delta since the last read, the host can calculate the
average power since the last read, as well as the energy
consumed since then.
The time delta is calculated by the bus host based on when it
sends its commands to read from the device, and is not
provided by the ADM1276.
To avoid loss of data, the bus host must read at a rate that
ensures the rollover counter does not wrap around more than
once, and if the counter does wrap around that the next value
read for PIN is less than the previous one.
The READ_EIN command returns the top 16
accumulator, the lower eight bits of the rollover counter, and the
full 24 bits of the sample counter.
The READ_EIN_EXT command returns the full 24 bits of the
energy accumulator, the full 16 bits of the rollover counter, and
the full 24 bits of the sample counter. The use of the longer
rollover counter means that the time interval between reads of
the part can be increased from seconds to minutes, without
losing any data.
bits of the energy
PEAK_IOUT, PEAK_VIN, PEAK_VOUT, and PEAK_PIN
Commands
In addition to the standard PMBus commands for reading
voltage and current, the ADM1276 provides commands that
can report the maximum peak voltage, current, or power value
since the peak value was last cleared.
The peak values are updated only after the power monitor has
sampled and averaged the current and voltage measurements.
Individual peak values are cleared by writing a 0 value with the
corresponding command.
WARNING LIMIT SETUP COMMANDS
The ADM1276 power monitor can monitor a number of
different warning conditions simultaneously and report any
current or voltage values that exceed the user-defined
thresholds using the status commands.
Rev. A | Page 29 of 48
ADM1276
All comparisons performed by the power monitor require the
measured value to be strictly greater or less than the threshold
value.
At power-up, all threshold limits are set to either minimum
scale (for undervoltage or undercurrent conditions) or to
maximum scale (for overvoltage or overcurrent or overpower
conditions). This effectively disables the generation of any
status warnings by default; warning bits are not set in the status
registers until the user explicitly sets the threshold values.
VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT
Commands
The VIN_OV_WARN_LIMIT and VIN_UV_WARN_LIMIT
commands are used to set the OV and UV thresholds on the
input voltage, as measured at the SENSE+ pin.
VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_LIMIT
Commands
The VOUT_OV_WARN_LIMIT and VOUT_UV_WARN_
LIMIT commands are used to set the OV and UV thresholds
on the output voltage, as measured at the VOUT pin.
IOUT_OC_WARN_LIMIT Command
The IOUT_OC_WARN_LIMIT command sets the OC
threshold for the current flowing through the sense resistor.
IOUT_WARN2_LIMIT Command
The IOUT_WARN2_LIMIT command provides a second
current warning threshold that can be programmed. The
polarity of this warning can be set to overcurrent or
undercurrent using the DEVICE_CONFIG command.
PIN_OP_WARN_LIMIT Command
The PIN_OP_WARN_LIMIT command is used to set the
overpower threshold for the power delivered to the load.
PMBus DIRECT FORMAT CONVERSION
The ADM1276 uses the PMBus direct format to represent realworld quantities such as voltage, current, and power values. A
direct format number takes the form of a 2-byte, twos complement,
binary integer value.
It is possible to convert between direct format value and realworld quantities using the following equations. Equation 1
converts from real-world quantities to PMBus direct values, and
Equation 2 converts PMBus direct format values to real-world
values.
Y = (mX + b) × 10
X = 1/m × (Y × 10
where:
Y is the value in PMBus direct format.
X is the real-world value.
m is the slope coefficient, a 2-byte, twos complement integer.
b is the offset, a 2-byte, twos complement integer.
R is a scaling exponent, a 1-byte, twos complement integer.
R
(1)
−R
− b) (2)
The same equations are used for voltage, current, and power
conversions, the only difference being the values of the m, b,
and R coefficients that are used.
Table 7 lists all the coefficients required for the ADM1276. The
current and power coefficients shown are dependent on the
value of the external sense resistor used in a given application.
This means that an additional calculation must be performed to
take the sense resistor value into account to obtain the coefficients
for a specific sense resistor value.
The sense resistor value used in the calculations to obtain the
coefficients is expressed in milliohms. The m coefficients are
defined as 2-byte twos complement numbers in the PMBus
standard, therefore the maximum positive value that can be
represented is 32,767. If the m value is greater than that, and is
to be stored in PMBus standard form, then the m coefficients
should be divided by 10, and the R coefficient increased by a
value of 1. For example, if on the 20 V range, a 10 milliohm
sense resistor is used, the m coefficient is 6043, and the R
coefficient is −1.
Example 1: IOUT_OC_WARN_LIMIT requires a current-limit
value expressed in direct format.
If the required current limit is 10 A, and the sense resistor is
2 mΩ, then the first step is to determine the voltage coefficient.
This is simply m = 807 × 2, giving 1614.
Using Equation 1, and expressing X, in units of Amps
Y = ((1614 × 10
) + 20,475) × 10−1
Y = 3661.5 = 3662 (rounded up to integer form)
Writing a value of 3662 with the IOUT_OC_WARN_LIMIT
command sets an overcurrent warning at 10 A.
Example 2: The READ_IOUT command returns a direct format
value of 3339 representing the current flowing through a sense
resistor of 1 mΩ.
To convert this value to the current flowing, use Equation 2, with
m = 807 × 1.
X = 1/807 × (3339 × 10
1
− 20,475)
X = 16.00 A
This means that when READ_IOUT returns a value of 3339,
16.00 A is flowing in the sense resistor.
There are two input voltage ranges, so there are also two sets of
coefficients for converting to and from the power value, depending
on which voltage range is selected.
Note the following:
•The same calculations that are used to convert power
values also apply to the energy accumulator value returned
by the READ_EIN command because the energy
accumulator is a summation of multiple power values.
•The READ_PIN_EXT and READ_EIN_EXT commands
return 24-bit extended precision versions of the 16-bit
values returned by READ_PIN and READ_EIN. The direct
Rev. A | Page 30 of 48
ADM1276
ing Equation 1, and working with the 0 V to 20 V range,
format values must be divided by 256 prior to being
converted with the coefficients shown in Tabl e 7.
Example 3: The PIN_OP_WARN_LIMIT command requires a
power limit value expressed in direct format.
If the required power limit is 350 W and the sense resistor is
1 mΩ, the first step is to determine the m coefficient. Assuming
the 0 V to 20 V range, m = 6043 × 1,
which is 6043.
Table 7. PMBus Conversion to Real-World Coefficients
Voltage (V) Power (W)
Coefficient Current (A)
m 807 × R
SENSE
6720 19,199 2115 × R
0 V to 6 V Range 0 V to 20 V Range 0 V to 6 V Range 0 V to 20 V Range
b 20,475 0 0 0 0
R −1 −1 −2 −1 −2
Us
Y = ((6043 × 350) × 10
-2
Y = 21,150.5 = 21,151 (rounded up to integer form)
Writing a value of 21,151 with the PIN_OP_WARN_LIMIT
command sets an overpower warning at 350 W.
6043 × R
SENSE
SENSE
Rev. A | Page 31 of 48
ADM1276
VOLTAGE AND CURRENT CONVERSION USING
LSB VALUES
The direct format voltage and current values returned by the
READ_VIN, READ_VOUT, and READ_IOUT commands, and
the corresponding peak versions, are the data output directly by
the ADM1276 ADC. Because the voltages and currents are 12-bit
ADC output codes, they can also be converted to real-world values
when there is knowledge of the size of the LSB on the ADC.
The m, b, and R coefficients defined for the PMBus conversion
are required to be whole integers by the standard and have,
therefore, been rounded slightly. Using this alternative method,
with the exact LSB values, can provide somewhat more accurate
numerical conversions.
To convert an ADC code to current in amperes, the following
formulas can be used:
V
= LSB
SENSE
I
= V
OUT
SENSE
where:
V
= (V
SENSE
LSB
I
ADC
I
OUT
R
SENSE
SENSE+
= 12.4 µV.
25 mV
is the 12-bit ADC code.
is the measured current value in amperes.
is the value of the sense resistor in milliohms.
To convert an ADC code to a voltage, the following formula can
be used:
V
= LSBxV × (V
M
25 mV
/(R
) − (V
× (I
SENSE
SENSE−
ADC
− 2048)
ADC
× 0.001)
).
+ 0.5)
where:
V
is the measured value in volts.
M
V
is the 12-bit ADC code.
ADC
LSB
values are based on the voltage range (see Table 8).
xV
Table 8. Voltage Ranges and LSB Values
Voltage Range, LSB
xV
LSB Magnitude
0 V to 6 V 1.488 mV
0 V to 20 V 5.208 mV
To convert a current in amperes to a 12-bit value, the following
formula can be used (round the result to the nearest integer):
V
SENSE
I
= 2048 + (V
CODE
= IA × R
SENSE
× 0.001
/LSB
SENSE
25 mV
)
where:
V
= (V
SENSE
I
is the current value in amperes.
A
R
is the value of the sense resistor in milliohms.
SENSE
I
is the 12-bit ADC code.
CODE
LSB
= 12.4 µV.
25 mV
SENSE+
) − (V
SENSE−
).
To convert a voltage to a 12-bit value, the following formula can
be used (round the result to the nearest integer):
V
= (VA/LSBxV) − 0.5
CODE
where:
V
is the 12-bit ADC code.
CODE
V
is the voltage value in volts.
A
LSB
values are based on the voltage range (see Table 8).
xV
Rev. A | Page 32 of 48
ADM1276
GPO2/
The ADM1276 provides a very flexible alert system, whereby
one or more fault/warning conditions can be indicated to an
external device.
ALERT2
PIN BEHAVIOR
FAULTS AND WARNINGS
A PMBus fault on the ADM1276 is always generated due to an
analog event and causes a change in state in the hot swap output,
turning it off. The three defined fault sources are as follows:
• Undervoltage (UV) event detected on the UV pin.
• Overvoltage (OV) event detected on the OV pin.
• Overcurrent (OC) event that causes a hot swap timeout.
Faults are continuously monitored, and, as long as power is
applied to the device, they cannot be disabled. When a fault
occurs, a corresponding status bit is set in one or more
STAT US_xxx registers.
A value of 1 in a status register bit field always indicates a fault
or warning condition. Fault and warning bits in the status
registers are latched when set to 1. To clear a latched bit to 0—
provided that the fault condition is no longer active—use the
CLEAR_FAULTS command or use the OPERATION command
to turn the hot swap output off and then on again.
A warning is less severe than a fault and never causes a change
in the state of the hot swap controller. The sources of a warning
are defined as follows:
• CML: a communications error occurred on the I
• HS timer was active ( H STA ) : the current regulation was
active, but did not necessarily shut the system down.
• IOUT OC warning from the ADC.
• IOUT Warni ng 2 from the ADC.
• VIN UV warning from the ADC.
• VIN OV warning from the ADC.
• VOUT UV warning from the ADC.
• VOUT OV warning from the ADC.
• PIN OP warning from the VIN × IOUT calculation.
2
C bus.
GENERATING AN ALERT
A host device can periodically poll the ADM1276 using the
status commands to determine whether a fault/warning is
active. However, this polling is very inefficient in terms of
software and processor resources. The ADM1276 has a
ALERT2
GPO2/
interrupts to a host processor.
By default at power-up, the open-drain GPO2/
output is high impedance, so the pin can be pulled high
through a resistor. The FET health bad warning is active by
default on the GPO2/
Any one or more of the faults and warnings listed in the Faults
and Warnings section can be enabled and cause an alert, making
output pin that can be used to generate
ALERT2
ALERT2
pin at power-up.
the GPO2/
GPO2/
For example, to use GPO2/
warning from the ADC, the followings steps must be
performed:
1. Set a threshold level with the VOUT_UV_WARN_LIMIT
2. Start the power monitor sampling on VOUT.
If a VOUT sample is taken that is below the configured
VOUT UV value, the GPO2/
an interrupt to a processor.
ALERT2
ALERT2
command.
pin active. By default, the active state of the
pin is low.
ALERT2
to monitor the VOUT UV
ALERT2
pin is taken low, signaling
HANDLING/CLEARING AN ALERT
When faults/warnings are configured on the GPO2/
the pin becomes active to signal an interrupt to the processor.
(The pin is active low, unless inversion is enabled.) The
ALERT2
SMBAlert.
A processor can respond to the interrupt in one of two basic ways:
• If there is only one device on the bus, the processor can
• If there are several devices on the bus, the processor can
signal on the GPO2/
simply read the status bytes and issue a CLEAR_FAULTS
command to clear all the status bits, which causes the deassertion of the GPO2/
fault—for example, an undervoltage on the input—the
status bits remain set after the CLEAR_FAULTS command
is executed because the fault has not been removed. However,
the GPO2/
or warning becomes active. If the cause of the SMBAlert is
a power monitor generated warning and the power monitor
is running continuously, the next sample generates a new
SMBAlert after the CLEAR_FAU LT S command is issued.
issue an SMBus alert response address command to find
out which device asserted the SMBAlert line. The processor
can read the status bytes from that device and issue a
CLEAR_FAULTS command.
ALERT2
ALERT2
ALERT2
line is not pulled low unless a new fault
pin functions as an
line. If there is a persistent
ALERT2
pin,
SMBus ALERT RESPONSE ADDRESS
The SMBus alert response address (ARA) is a special address
that can be used by the bus host to locate any devices that need
to talk to it. A host typically uses a hardware interrupt pin to
monitor the SMBus alert pins of a number of devices. When the
host interrupt occurs, the host issues a message on the bus using
the SMBus receive byte or receive byte with PEC protocol.
The special address used by the host is 0x0C. Any devices that
have an SMBAlert signal return their own 7-bit address as the
seven MSBs of the data byte. The LSB value is not used and can
be either 1 or 0. The host reads the device address from the
received data byte and proceeds to handle the alert condition.
Rev. A | Page 33 of 48
ADM1276
More than one device may have an active SMBAlert signal and
attempt to communicate with the host. In this case, the device
with the lowest address dominates the bus and succeeds in
transmitting its address to the host. The device that succeeds
disables its SMBus alert signal. If the host sees that the SMBus
alert signal is still low, it continues to read addresses until all
devices that need to talk to it have successfully transmitted their
addresses.
EXAMPLE USE OF SMBus ALERT RESPONSE
ADDRESS
The full sequence of steps that occurs when an SMBAlert is
generated and cleared is as follows:
1. A fault or warning is enabled using the ALERT2_CONFIG
command, and the corresponding status bit for the fault or
warning changes from 0 to 1, indicating that the fault or
warning has just become active.
2. The GPO2/
an SMBAlert is active.
ALERT2
pin becomes active (low) to signal that
3. The host processor issues an SMBus alert response address
command to determine which device has an active alert.
4. If there are no other active alerts from devices with lower
2
I
C addresses, this device makes the GPO2/
inactive (high) during the no acknowledge bit period after
it sends its address to the host processor.
5. If the GPO2/
continue to issue SMBus alert response address commands
to devices to find out the addresses of all devices whose
status it must check.
6. The ADM1276 continues to operate with the GPO2/
pin inactive and the contents of the status bytes unchanged
until the host reads the status bytes and clears them, or until
a new fault occurs. That is, if a status bit for a fault/warning
that is enabled on the GPO2/
already active (equal to 1) changes from 0 to 1, a new alert
is generated, causing the GPO2/
active again.
ALERT2
pin stays low, the host processor must
ALERT2
ALERT2
ALERT2
pin and that was not
pin to become
pin
ALERT2
Rev. A | Page 34 of 48
ADM1276
PMBus COMMAND REFERENCE
Command codes are in hexadecimal format.
Table 9. PMBus Command Summary
Command Code Command Name SMBus Transaction Type Number of Data Bytes Default Value at Reset
Code: 0x01, read/write byte. Value after reset: 0x80.
Table 10. Bit Descriptions for OPERATION Command
Bits Bit Name Settings Description
[7] On 0 Hot swap output is disabled.
1 Default. Hot swap output is enabled.
[6:0] Reserved 0000000 Always reads as 0000000.
CLEAR_FAULTS
Code: 0x03, send byte, no data.
CAPABILITY
Code: 0x19, read byte. Value after reset: 0xB0.
Table 11. Bit Descriptions for CAPABILITY Command
Bits Bit Name Settings Description
[7] Packet error checking 1 Always reads as 1. Packet error checking (PEC) is supported.
[6:5] Maximum bus speed 01 Always reads as 01. Maximum supported bus speed is 400 kHz.
[4] SMBALERT# 1 Always reads as 1. Device supports SMBAlert and alert response address (ARA).
[3:0] Reserved 0000 Always reads as 0000.
VOUT_OV_WARN_LIMIT
Code: 0x42, read/write word. Value after reset: 0x0FFF.
Table 12. Bit Descriptions for VOUT_OV_WARN_LIMIT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] VOUT_OV_WARN_LIMIT Overvoltage threshold for the VOUT pin measurement, expressed in ADC codes.
VOUT_UV_WARN_LIMIT
Code: 0x43, read/write word. Value after reset: 0x0000.
Table 13. Bit Descriptions for VOUT_UV_WARN_LIMIT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] VOUT_UV_WARN_LIMIT Undervoltage threshold for the VOUT pin measurement, expressed in ADC codes.
IOUT_OC_WARN_LIMIT
Code: 0x4A, read/write word. Value after reset: 0x0FFF.
Table 14. Bit Descriptions for IOUT_OC_WARN_LIMIT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] IOUT_OC_WARN_LIMIT Overcurrent threshold for the IOUT measurement through the sense resistor,
expressed in ADC codes.
IOUT_WARN2_LIMIT
Code: 0xD7, read/write word. Value after reset: 0x0000.
Table 15. Bit Descriptions for IOUT_WARN2_LIMIT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] IOUT_WARN2_LIMIT Threshold for the IOUT measurement through the sense resistor, expressed in ADC
codes. This value can be either an undercurrent or an overcurrent, depending on the
state of the IOUT_WARN2_SELECT bit that is set using the DEVICE_CONFIG command.
Rev. A | Page 36 of 48
ADM1276
VIN_OV_WARN_LIMIT
Code: 0x57, read/write word. Value after reset: 0x0FFF.
Table 16. Bit Descriptions for VIN_OV_WARN_LIMIT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] VIN_OV_WARN_LIMIT Overvoltage threshold for the SENSE+ pin measurement, expressed in ADC codes.
VIN_UV_WARN_LIMIT
Code: 0x58, read/write word. Value after reset: 0x0000.
Table 17. Bit Descriptions for VIN_UV_WARN_LIMIT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] VIN_UV_WARN_LIMIT Undervoltage threshold for the SENSE+ pin measurement, expressed in ADC codes.
PIN_OP_WARN_LIMIT
Code: 0x6B, read/write word. Value after reset: 0x7FFF.
Table 18. Bit Descriptions for PIN_OP_WARN_LIMIT Command
Bits Bit Name Settings Description
[15] Reserved 0 Always reads as 0.
[14:0] PIN_OP_WARN_LIMIT Overpower threshold for the VIN × IOUT power calculation.
STATUS_BYTE
Code: 0x78, read byte. Value after reset: 0x00.
Table 19. Bit Descriptions for STATUS_BYTE Command
Bits Bit Name Behavior Settings Description
[7] Reserved 0 Always reads as 0.
[6] HOTSWAP_OFF Live 0 The hot swap gate drive output is enabled.
1 The hot swap gate drive output is disabled, and the GATE pin is pulled
down. This can be due to, for example, an overcurrent fault that causes
the ADM1276 to latch off, an undervoltage condition on the UV pin, or
the use of the OPERATION command to turn the output off.
[5] Reserved 0 Always reads as 0.
[4] IOUT_OC_FAULT Latched 0 No overcurrent output fault detected.
1 The hot swap controller detected an overcurrent condition and the time
limit set by the capacitor on the TIMER pin has elapsed, causing the hot
swap gate drive to shut down.
[3] VIN_UV_FAULT Latched 0 No undervoltage input fault detected on the UV pin.
1 An undervoltage input fault was detected on the UV pin.
[2] Reserved 0 Always reads as 0.
[1] CML_ERROR Latched 0 No communications error detected on the I2C/PMBus interface.
1 An error was detected on the I2C/PMBus interface. Errors detected are an
unsupported command, an invalid PEC byte, and an incorrectly
structured message.
[0] NONE_OF_THE_ABOVE Live 0 No other active status bit to be reported by any other status command.
1 Active status bits are waiting to be read by one or more status commands.
Rev. A | Page 37 of 48
ADM1276
STATUS_WORD
Code: 0x79, read word. Value after reset: 0x0000.
Table 20. Bit Descriptions for STATUS_WORD Command
Bits Bit Name Behavior Settings Description
[15] VOUT_STATUS Live 0 There are no active status bits to be read by STATUS_VOUT.
1 There are one or more active status bits to be read by STATUS_VOUT.
[14] IOUT_STATUS Live 0 There are no active status bits to be read by STATUS_IOUT.
1 There are one or more active status bits to be read by STATUS_IOUT.
[13] INPUT_STATU S Live 0 There are no active status bits to be read by STATUS_INPUT.
1 There are one or more active status bits to be read by STATUS_INPUT.
[12] MFR_STATUS Live 0 There are no active status bits to be read by STATUS_MFR_SPECIFIC.
1 There are one or more active status bits to be read by STATUS_MFR_SPECIFIC.
[11] POWER_GOOD# Live 0 The voltage on the FLB pin is above the required threshold, indicating
that output power is considered good. This bit is the logical inversion of
the PWRGD pin on the part.
1 The voltage on the FLB pin is below the required threshold, indicating
that output power is considered bad.
[10:8] Reserved 000 Always reads as 000.
[7:0] STATUS_BYTE This byte is the same as the byte returned by the STATUS_BYTE command.
STATUS_VOUT
Code: 0x7A, read byte. Value after reset: 0x00.
Table 21. Bit Descriptions for STATUS_VOUT Command
Bits Bit Name Behavior Settings Description
[7] Reserved 0 Always reads as 0.
[6] VOUT_OV_WARN Latched 0 No overvoltage condition on the output supply detected by the power
monitor.
1 An overvoltage condition on the output supply was detected by the
power monitor.
[5] VOUT_UV_WARN Latched 0 No undervoltage condition on the output supply detected by the power
monitor.
1 An undervoltage condition on the output supply was detected by the
power monitor.
[4:0] Reserved 00000 Always reads as 00000.
STATUS_IOUT
Code: 0x7B, read byte. Value after reset: 0x00.
Table 22. Bit Descriptions for STATUS_IOUT Command
Bits Bit Name Behavior Settings Description
[7] IOUT_OC_FAULT Latched 0 No overcurrent output fault detected.
1 The hot swap controller detected an overcurrent condition and the time
limit set by the capacitor on the TIMER pin has elapsed, causing the hot
swap gate drive to shut down.
[6] Reserved 0 Always reads as 0.
[5] IOUT_OC_WARN Latched 0 No overcurrent condition on the output supply detected by the power
monitor using the IOUT_OC_WARN_LIMIT command.
1 An overcurrent condition was detected by the power monitor using the
IOUT_OC_WARN_LIMIT command.
[4:0] Reserved 00000 Always reads as 00000.
Rev. A | Page 38 of 48
ADM1276
STATUS_INPUT
Code: 0x7C, read byte. Value after reset: 0x00.
Table 23. Bit Descriptions for STATUS_INPUT Command
Bits Bit Name Behavior Settings Description
[7] VIN_OV_FAULT Latched 0 No overvoltage detected on the OV pin.
1 An overvoltage was detected on the OV pin.
[6] VIN_OV_WARN Latched 0 No overvoltage condition on the input supply detected by the power
monitor.
1 An overvoltage condition on the input supply was detected by the power
monitor.
[5] VIN_UV_WARN Latched 0 No undervoltage condition on the input supply detected by the power
monitor.
1 An undervoltage condition on the input supply was detected by the
power monitor.
[4] VIN_UV_FAULT Latched 0 No undervoltage detected on the UV pin.
1 An undervoltage was detected on the UV pin.
[3:1] Reserved 000 Always reads as 000.
[0] PIN_OP_WARN Latched 0 No overpower condition on the input supply detected by the power
monitor.
1 An overpower condition on the input supply was detected by the power
monitor.
STATUS_MFR_SPECIFIC
Code: 0x80, read byte. Value after reset: 0x00.
Table 24. Bit Descriptions for STATUS_MFR_SPECIFIC Command
Bits Bit Name Behavior Settings Description
[7] FET_HEALTH_BAD Latched 0 FET behavior appears to be as expected.
1 FET behavior suggests that the FET may be shorted.
[6] UV_CMP_OUT Live 0 Input voltage to UV pin is above threshold.
1 Input voltage to UV pin is below threshold.
[5] OV_CMP_OUT Live 0 Input voltage to OV pin is below threshold.
1 Input voltage to OV pin is above threshold.
[4] Reserved 0 Always reads as 0.
[3] HS_INLIM Latched 0 The ADM1276 has not actively limited the current into the load.
1 The ADM1276 has actively limited current into the load. This bit differs
from the IOUT_OC_FAULT bit in that the HS_INLIM bit is set immediately,
whereas the IOUT_OC_FAULT bit is not set unless the time limit set by the
capacitor on the TIMER pin elapses.
[2:1] HS_SHUTDOWN_CAUSE Latched 00 The ADM1276 is either enabled and working correctly, or has been shut
down using the OPERATION command.
01 An IOUT_OC_FAULT condition occurred that caused the ADM1276 to shut
down.
10 A VIN_UV_FAULT condition occurred that caused the ADM1276 to shut down.
11 A VIN_OV_FAULT condition occurred that caused the ADM1276 to shut down.
[0] IOUT_WARN2 Latched 0 No overcurrent condition on the output supply detected by the power
monitor using the IOUT_WARN2_LIMIT command.
1 An undercurrent or overcurrent condition on the output supply was
detected by the power monitor using the IOUT_WARN2_LIMIT command.
The polarity of the threshold condition is set by the IOUT_WARN2_SELECT
bit using the DEVICE_CONFIG command.
Rev. A | Page 39 of 48
ADM1276
READ_EIN
Code: 0x86, block read. Value after reset: 0x06, 0x0000, 0x00, 0x000000.
Table 25. Byte Descriptions for READ_EIN Command
Byte Byte Name Value Description
[0] Byte count 0x06 Always reads as 0x06, the number of data bytes that the block read command
should expect to read.
[2:1] Energy count 0x0000 Energy accumulator value in direct format. Byte 2 is the high byte, and Byte 1 is the
low byte. Internally, the energy accumulator is a 24-bit value, but only the most
significant 16 bits are returned with this command. Use the READ_EIN_EXT
command to access the nontruncated version.
[3] Rollover count 0x00 Number of times that the energy count has rolled over from 0x7FFF to 0x0000. This
is a straight 8-bit binary value.
[6:4] Sample count 0x000000 This is the total number of PIN samples acquired and accumulated in the energy
count accumulator. Byte 6 is the high byte, Byte 5 is the middle byte, and Byte 4 is
the low byte. This is a straight 24-bit binary value.
READ_VIN
Code: 0x88, read word. Value after reset: 0x0000.
Table 26. Bit Descriptions for READ_VIN Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] VIN Input voltage from the SENSE+ pin measurement, expressed in ADC codes.
READ_VOUT
Code: 0x8B, read word. Value after reset: 0x0000.
Table 27. Bit Descriptions for READ_VOUT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] VOUT Output voltage from the VOUT pin measurement, expressed in ADC codes.
READ_IOUT
Code: 0x8C, read word. Value after reset: 0x0000.
Table 28. Bit Descriptions for READ_IOUT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] IOUT Output current from the measurement through the sense resistor, expressed in ADC codes.
READ_PIN
Code: 0x97, read word. Value after reset: 0x0000.
Table 29. Bit Descriptions for READ_PIN Command
Bits Bit Name Settings Description
[15] Reserved 0 Always reads as 0.
[14:0] PIN Input power from the VIN × IOUT calculation.
PMBUS_REVISION
Code: 0x98, read byte. Value after reset: 0x22.
Table 30. Bit Descriptions for PMBUS_REVISION Command
Bits Bit Name Settings Description
[7:4] Part I revision 0010 Always reads as 0010, PMBus Specification Part I, Revision 1.2.
[3:0] Part II revision 0010 Always reads as 0010, PMBus Specification Part II, Revision 1.2.
Rev. A | Page 40 of 48
ADM1276
MFR_ID
Code: 0x99, block read. Value after reset: 0x03 + ASCII “ADI.”
Table 31. Byte Descriptions for MFR_ID Command
Byte Byte Name Value Description
[0] Byte count 0x03 Always reads as 0x03, the number of data bytes that the block read command
expects to read.
[1] Character 1 0x41 or “A” Always reads as 0x41.
[2] Character 2 0x44 or “D” Always reads as 0x44.
[3] Character 3 0x49 or “I” Always reads as 0x49.
MFR_MODEL
Code: 0x9A, block read. Value after reset: 0x09 + ASCII “ADM1276-3.”
Table 32. Byte Descriptions for MFR_MODEL Command
Byte Byte Name Value Description
[0] Byte count 0x09 Always reads as 0x09, the number of data bytes that the block read command
expects to read.
[1] Character 1 0x41 or “A” Always reads as 0x41.
[2] Character 2 0x44 or “D” Always reads as 0x44.
[3] Character 3 0x4D or “M” Always reads as 0x4D.
[4] Character 4 0x31 or “1” Always reads as 0x31.
[5] Character 5 0x32 or “2” Always reads as 0x32.
[6] Character 6 0x37 or “7” Always reads as 0x37.
[7] Character 7 0x36 or “6” Always reads as 0x36.
[8] Character 8 0x2D or “–“ Always reads as 0x2D.
[9] Character 9 0x33 or “3” Always reads as 0x33.
MFR_REVISION
Code: 0x9B, block read. Value after reset: 0x01 + ASCII “0.”
Table 33. Byte Descriptions for MFR_REVISION Command
Byte Byte Name Value Description
[0] Byte count 0x01 Always reads as 0x01, the number of data bytes that the block read command
expects to read.
[1] Character 1 0x30 or “0” Always reads as 0x30, Revision 0 of the ADM1276.
PEAK_IOUT
Code: 0xD0, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value).
Table 34. Bit Descriptions for PEAK_IOUT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] PEAK_IOUT Returns the peak IOUT current since the register was last cleared.
PEAK_VIN
Code: 0xD1, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value).
Table 35. Bit Descriptions for PEAK_VIN Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] PEAK_VIN Returns the peak VIN voltage since the register was last cleared.
Rev. A | Page 41 of 48
ADM1276
PEAK_VOUT
Code: 0xD2, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value).
Table 36. Bit Descriptions for PEAK_VOUT Command
Bits Bit Name Settings Description
[15:12] Reserved 0000 Always reads as 0000.
[11:0] PEAK_VOUT Returns the peak VOUT voltage since the register was last cleared.
PMON_CONTROL
Code: 0xD3, read/write byte. Value after reset: 0x01.
Table 37. Bit Descriptions for PMON_CONTROL Command
Bits Bit Name Settings Description
[7:1] Reserved 0000000 Always reads as 0000000.
[0] Convert 0 Power monitor is not running.
1 Default. Start the sampling of current and voltage with the power monitor. In single shot
mode, this bit clears itself after one complete cycle. In continuous mode, this bit must
be written to 0 to stop sampling.
PMON_CONFIG
Code: 0xD4, read/write byte. Value after reset: 0xAF.
Modifying the power monitor settings while the power monitor is sampling is not supported. The power monitor must be stopped before
any setting in Ta b l e 38 is changed to ensure correct operation and to prevent the generation of any potential spurious data and status alerts.
Table 38. Bit Descriptions for PMON_CONFIG Command
Bits Bit Name Settings Description
[7] PMON_MODE 0 This setting selects single shot sampling mode.
1 Default. This setting selects continuous sampling mode.
[6] VOUT_SELECT 0 Default. The power monitor samples the input voltage on the SENSE+ pin and IOUT.
1 The power monitor samples the input voltage on the SENSE+ pin, IOUT, and the
voltage on the VOUT pin.
[5] VRANGE 0 Sets the voltage input range from 0 V to 6 V (low input voltage range).
1 Default. Sets the voltage input range from 0 V to 20 V (high input voltage range).
[4] Reserved 0 Reserved. This bit must always be written as 0.
[3] Reserved 1 Default. This bit must be set to 1 for the power monitor current sense to operate
correctly.
[2:0] Averaging 000 Disables sample averaging for current and voltage.
001 Sets sample averaging for current and voltage to two samples.
010 Sets sample averaging for current and voltage to four samples.
011 Sets sample averaging for current and voltage to eight samples.
100 Sets sample averaging for current and voltage to 16 samples.
101 Sets sample averaging for current and voltage to 32 samples.
110 Sets sample averaging for current and voltage to 64 samples.
111 Default. Sets sample averaging for current and voltage to 128 samples.
Rev. A | Page 42 of 48
ADM1276
ALERT2_CONFIG
Code: 0xD6, read/write word. Value after reset: 0x8000.
Table 39. Bit Descriptions for ALERT2_CONFIG Command
Bits Bit Name Settings Description
[15] FET_HEALTH_BAD_EN2 0 Disables generation of an SMBAlert when the FET_HEALTH_BAD bit is set.
1 Default. Generates SMBAlert when the FET_HEALTH_BAD bit is set. This bit is active
from power-up for a FET problem to be detected and flagged immediately without the
need for software to set this bit.
[14] IOUT_OC_FAULT_EN2 0 Default. Disables generation of an SMBAlert when the IOUT_OC_FAULT bit is set.
1 Generates an SMBAlert when the IOUT_OC_FAULT bit is set.
[13] VIN_OV_FAULT_EN2 0 Default. Disables generation of an SMBAlert when the VIN_OV_FAULT bit is set.
1 Generates an SMBAlert when the VIN_OV_FAULT bit is set.
[12] VIN_UV_FAULT_EN2 0 Default. Disables generation of an SMBAlert when the VIN_UV_FAULT bit is set.
1 Generates an SMBAlert when the VIN_UV_FAULT bit is set.
[11] CML_ERROR_EN2 0 Default. Disables generation of an SMBAlert when the CML_ERROR bit is set.
1 Generates an SMBAlert when the CML_ERROR bit is set.
[10] IOUT_OC_WARN_EN2 0 Default. Disables generation of an SMBAlert when the IOUT_OC_WARN bit is set.
1 Generates an SMBAlert when the IOUT_OC_WARN bit is set.
[9] IOUT_WARN2_EN2 0 Default. Disables generation of an SMBAlert when the IOUT_WARN2 bit is set.
1 Generates an SMBAlert when the IOUT_WARN2 bit is set.
[8] VIN_OV_WARN_EN2 0 Default. Disables generation of an SMBAlert when the VIN_OV_WARN bit is set.
1 Generates an SMBAlert when the VIN_OV_WARN bit is set.
[7] VIN_UV_WARN_EN2 0 Default. Disables generation of an SMBAlert when the VIN_UV_WARN bit is set.
1 Generates an SMBAlert when the VIN_UV_WARN bit is set.
[6] VOUT_OV_WARN_EN2 0 Default. Disables generation of an SMBAlert when the VOUT_OV_WARN bit is set.
1 Generates an SMBAlert when the VOUT_OV_WARN bit is set.
[5] VOUT_UV_WARN_EN2 0 Default. Disables generation of an SMBAlert when the VOUT_UV_WARN bit is set.
1 Generates an SMBAlert when the VOUT_UV_WARN bit is set.
[4] HS_INLIM_EN2 0 Default. Disables generation of an SMBAlert when the HS_INLIM bit is set.
1 Generates an SMBAlert when the HS_INLIM bit is set.
[3] PIN_OP_WARN_EN2 0 Default. Disables generation of an SMBAlert when the PIN_OP_WARN bit is set.
1 Generates an SMBAlert when the PIN_OP_WARN bit is set.
[2:1] GPO2_MODE 00 Default. GPO2 is configured to generate SMBAlerts.
01 GPO2 can be used as a general-purpose digital output pin. The GPO2_INVERT bit is
used to change the output state.
10 Reserved.
11 GPO2 is configured for digital comparator mode. The output pin continuously shows
for the selected warning(s) if the relevant warning threshold has been exceeded. In
effect, this is an unlatched SMBAlert. If multiple bits are selected, the output values are
OR’ed together. Only warning threshold comparisons affect the pin in this mode. If
other bits such as VIN_UV_FAULT_EN2 are set, they are ignored in this mode of
operation.
[0] GPO2_INVERT 0 Default. The GPO2 pin is active low.
1 GPO2 is active high.
Rev. A | Page 43 of 48
ADM1276
DEVICE_CONFIG
Code: 0xD8, read/write byt e . Val ue after reset: 0x00.
Table 40. Bit Descriptions for DEVICE_CONFIG Command
Bits Bit Name Settings Description
[7] OC_GLITCH_TIME 0 Default. The long duration glitch filter is used when a severe overcurrent fault is
detected.
1 The short duration glitch filter is used when a severe overcurrent fault is detected.
[6] FLB_DISABLE 0 Default. Foldback is enabled and can affect the hot swap current sense limit.
1 Foldback is disabled and does not affect the hot swap current sense limit. This setting
can be useful if the sole purpose of the FLB pin is to act as a power-good input.
[5] OPERATION_CMD_EN 0 Default. The OPERATION command is disabled, and the ADM1276 issues a no
acknowledge if the command is received. This setting provides some protection
against a card accidentally turning itself off.
1 The OPERATION command is enabled, and the ADM1276 responds to it.
[4] IOUT_WARN2_SELECT 0 Default. Configures IOUT_WARN2_LIMIT as an undercurrent threshold.
1 Configures IOUT_WARN2_LIMIT as an overcurrent threshold.
[3:0] Reserved 0000 Always reads as 0000.
POWER_CYCLE
Code: 0xD9, send byte, no data.
PEAK_PIN
Code: 0xDA, read/write word. Value after reset: 0x0000 (writing 0x0000 clears the peak value).
Table 41. Bit Descriptions for PEAK_PIN Command
Bits Bit Name Settings Description
[15] Reserved 0 Always reads as 0.
[14:0] PEAK_PIN Returns the peak input power since the register was last cleared.
READ_PIN_EXT
Code: 0xDB, block read. Value after reset: 0x03, 0x000000.
Table 42. Byte Descriptions for READ_PIN_EXT Command
Byte Byte Name Value Description
[0] Byte count 0x03 Always reads as 0x03, the number of data bytes that the block read command
expects to read.
[3:1] PIN extended 0x000000 Result of the VIN × IOUT calculation that has not been truncated. Byte 3 is the high
byte, Byte 2 is the middle byte, and Byte 1 is the low byte.
READ_EIN_EXT
Code: 0xDC, block read. Value after reset: 0x08, 0x000000, 0x0000, 0x000000.
Table 43. Byte Descriptions for READ_EIN_EXT Command
Byte Byte Name Value Description
[0] Byte count 0x08 Always reads as 0x08, the number of data bytes that the block read command
expects to read.
[3:1] Energy count extended 0x000000 24-bit energy accumulator in direct format. Byte 3 is the high byte, Byte 2 is the
middle byte, and Byte 1 is the low byte.
[5:4] Rollover count extended 0x0000 Number of times that the energy counter has rolled over from 0x7FFF to 0x0000.
This is a straight 16-bit binary value. Byte 5 is the high byte, and Byte 4 is the low
byte.
[8:6] Sample count 0x000000 Total number of PIN samples acquired and accumulated in the energy count
accumulator. Byte 8 is the high byte, Byte 7 is the middle byte, and Byte 6 is the
low byte.
Rev. A | Page 44 of 48
ADM1276
COMPLIANT
TO
JEDEC STANDARDS M O-220-WHHC.
111908-A
0.65
BSC
0.70
0.60
0.40
0.35
0.28
0.23
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
SEATING
PLANE
0.80
0.75
0.70
0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
3.25
3.10 SQ
2.95
FOR PRO P E R CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIG URATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
15
16
5
OUTLINE DIMENSIONS
Figure 61. 20-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
5 mm × 5 mm Body, Very Very Thin Quad
(CP-20-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADM1276-3ACPZ −40°C to +85°C 20-Lead LFCSP_WQ CP-20-9
ADM1276-3ACPZ-RL −40°C to +85°C 20-Lead LFCSP_WQ CP-20-9
1
Z = RoHS Compliant Part.
Rev. A | Page 45 of 48
ADM1276
NOTES
Rev. A | Page 46 of 48
ADM1276
NOTES
Rev. A | Page 47 of 48
ADM1276
NOTES
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).