ANALOG DEVICES ADM1186 Service Manual

Quad Voltage Up and Down Sequencer

V

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and Monitor with Programmable Timing

FEATURES

Powered from 2.7 V to 5.5 V on the VCC pin Monitors four supplies via 0.8% accurate comparators Digital core supports up and down supply sequencing Multiple devices can be cascaded (ADM1186-1) Four inputs can be programmed to monitor different voltage

le

vels with resistor dividers

Capacitor programmable supply sequence time delays

and a tim Four open-drain enable outputs Open-drain power-good output Open-drain sequence complete pin and bidirectional

open-

APPLICATIONS

Monitor and alarm functions Up and down power supply sequencing Telecommunication and data communication equipment PCs, servers, and notebook PCs

eout delay to 5% accuracy at 25°C

drain fault pin (ADM1186-1 only)

ADM1186

GENERAL DESCRIPTION

The ADM1186-1 and ADM1186-2 are integrated, four-channel voltage monitoring and sequencing devices. A 2.7 V to 5.5 V power supply is required on the VCC pin for power.

Four precision comparators, VIN1 to VIN4, monitor four

age rails. All four comparators share a 0.6 V reference and

volt have a worst-case accuracy of 0.8%. Resistor networks that are external to the VIN1, VIN2, VIN3, and VIN4 pins set the undervoltage (UV) trip points for the monitored supply rails.

The ADM1186-1 and ADM1186-2 have four open-drain enable

utputs, OUT1 to OUT4, that are used to enable power supplies.

o An open-drain power-good output, PWRGD, indicates whether the four VINx inputs are above their UV thresholds.

DO

A state machine monitors the state of the UP and on the ADM1186-1 or the UP/

DOWN

pin on the ADM1186-2

to control the supply sequencing direction (see Figure 2). In the

AIT START state, a rising edge transition on the UP or

W

DOWN

UP/ transition on the

pin triggers a power-up sequence. A falling edge

DOWN

or UP/

DOWN

pin in the POWER-UP

DONE state triggers a power-down sequence.

WN

pins

3.3V AUX

SEQUENCE CONTRO L

3.3V AUX

1µF

100nF

VCC OUT1 OUT2

FAU LT

UP

DOWN

DLY_EN_OUT1

DLY_EN_OUT2

DLY_EN_OUT3

DLY_EN_OUT4

BLANK_DLY

APPLICATION DIAGRAM

ADP1706

EN OUT

5V

GND

5

IN

ADP2107

EN OUT

3.3V AUX

OUT3 OUT4

PWRGD

SEQ_DONE

Figure 1.

5V

IN

5V

VIN1

VIN2

VIN3

VIN4

3.3V AUX

ADP1821

EN OUT

2.5V AUX

5V

ADM1186-1

IN

5V

IN

ADP1706

EN OUT

2.5V

1.8V

1.2V

3.3V

3.3V AUX

07153-003

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

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REVISION HISTORY

5/08—Revision 0: Initial Version

UVLO Behavior.......................................................................... 13

Power-Up Sequencing and Monitoring................................... 13

Operation in POWER-UP DONE State.................................. 14

Power-Down Sequencing and Monitoring............................. 14

Input Glitch Filtering................................................................. 14

Fault Conditions and Fault Handling...................................... 14

Defining Time Delays................................................................ 15

Sequence Control Using a Supply Rail.................................... 16

Cascading Multiple Devices.......................................................... 23

Outline Dimensions....................................................................... 26

Ordering Guide .......................................................................... 26

Rev. 0 | Page 2 of 28

ADM1186

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During a power-up sequence, the state machine enables each power supply in turn. The supply output voltage is monitored to determine whether it rises above the UV threshold level within a user defined duration called the blanking time. If a supply rises above the UV threshold, the next enable output in the sequence is turned on. In addition to the blanking time, the user can also define a sequence time delay before each enable output is turned on.

The ADM1186-1 provides an open-drain pin, SEQ_DONE, th

at is asserted high to provide an indication that a power-up sequence is complete. The SEQ_DONE pin allows multiple cascaded ADM1186-1 devices to perform controlled power-up and power-down sequences.

During a power-down sequence, the enable outputs turn off

n reverse order. The same sequence time delays used during

i the power-up sequence are also used during the power-down sequence as each enable output is turned off; no blanking time is used during a power-down sequence. At the end of a powerdown sequence, the SEQ_DONE pin is brought low.

POWER-DOWN

DONE

WAIT STAR T

During sequencing and when powered up, the state machine co

ntinuously monitors the part for any fault conditions. Faults include a UV condition on any of the inputs or an unexpected control input. Any fault causes the state machine to enter a fault handler, which immediately turns off all enable outputs and then ensures that the device is ready to start a new power-up sequence.

ULT

FA

The ADM1186-1 has a bidirectional pin,

, that facilitates fault handling when using multiple devices. If an ADM1186-1 experiences a fault condition, the

FAU LT

pin is driven low, causing other connected ADM1186-1 devices to enter their own fault handling states.

The ADM1186-1 is available in a 20-lead QSOP package, and th

e ADM1186-2 is available in a 16-lead QSOP package.

SEQUENCE UP

TRIGGER

SEQUENCE

SUPPLY 1 ON

SEQUENCE

SUPPLY 1 OFF

SEQUENCE

SUPPLY 2 OFF

SEQUENCE

SUPPLY 3 OFF

SEQUENCE

SUPPLY 4 OFF

FAULT HANDLER

FAULT CONDITION OCCURS

IN ANY STATE

SEQUENCE DOWN TRIGGER

Figure 2. Simplified State Machine Diagram

SEQUENCE

SUPPLY 2 ON

SEQUENCE

SUPPLY 3 ON

SEQUENCE

SUPPLY 4 ON

POWER-UP DONE

07153-004

Rev. 0 | Page 3 of 28

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SPECIFICATIONS

V

= 2.7 V to 5.5 V, TA = −40°C to +85°C; typical values at TA = 25°C, unless otherwise noted.

VCC

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

VCC PIN

Operating Voltage Range, V Undervoltage Lockout, V Undervoltage Lockout Hysteresis 50 mV Supply Current, I

146 210 µA Steady state; sequence complete

VCC

VIN1 TO VIN4 (VINx) PINS

Input Current −25 +25 nA V

−100 +100 nA V Input Threshold

1

Input Glitch Immunity

Positive Glitch Duration 19.9 26.6 33.2 µs 50 mV input overdrive Negative Glitch Duration 2.75 4.7 6.6 µs 50 mV input overdrive

UP, DOWN, AND UP/DOWN PINS

Input Current −100 +100 nA V

Input Threshold

1

Input Glitch Immunity 3.3 6.8 9.7 µs 100 mV input overdrive

2.7 4.9 7.9 µs 1 V input overdrive

DLY_EN_OUTx AND BLANK_DLY PINS

Time Delay Accuracy 5 9 %

Time Delay Charge Current 14 µA Time Delay Threshold 1.4 V Time Delay Discharge Resistor 450 Ω

OUT1 TO OUT4 (OUTx) PINS

Output Low Voltage, V Leakage Current V

That Guarantees Valid Outputs 1 V

VCC

PWRGD PIN

Output Low Voltage, V Leakage Current V

That Guarantees Valid Outputs 1 V

VCC

FAU LT PIN

Input Threshold

1

Input Glitch Immunity 3.1 5.6 8.1 µs 1 V input overdrive Output Low Voltage, V

Leakage Current V

That Guarantees Valid Outputs 1 V

VCC

2.7 3.3 5.5 V

VCC

2.46 V V

UVLO

0.5952 0.6000 0.6048 V

1.372 1.4 1.428 V

0.4 V V

OUTL

1 µA OUTx = 5.5 V

0.4 V V

PWRGDL

1 µA PWRGD = 5.5 V

1.372 1.4 1.428 V

0.4 V V

FAULT L

1 µA

falling

VCC

= 0 V to 1 V

VINx

= 0 V to 5.5 V; V

VINx

= 0 V to 5.5 V; V

UP/

DOWN

can be greater than V

VINx

can be greater than V

UP/

DOWN

VCC

External capacitor values of 10 nF to 2.2 F; excludes

ternal capacitor tolerance

ex

= 2.7 V, I

VCC

Output is guaranteed to be either low (V or giving a valid output level from V 30 µA or V

= 2.7 V, I

VCC

Output is guaranteed to be either low (V or giving a valid output level from V 30 µA or V

= 2.7 V, I

VCC

= 5.5 V

FAU LT Output is guaranteed to be either low (V or giving a valid output level from V

30 µA or V

SINK

= 1.1 V, I

VCC

SINK

= 1.1 V, I

VCC

SINK

= 1.1 V, I

VCC

= 2 mA

SINK

= 2 mA

SINK

= 2 mA

SINK

= 100 µA

VCC

OUTL

= 1 V, I

PWRGDL

= 1 V, I

FAULT L

= 1 V, I

= 0.4 V)

=

SINK

= 0.4 V)

=

SINK

= 0.4 V)

=

SINK

Rev. 0 | Page 4 of 28

ADM1186

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Parameter Min Typ Max Unit Test Conditions/Comments

SEQ_DONE PIN

Output Low Voltage, V Leakage Current V

That Guarantees Valid Outputs 1 V

VCC

RESPONSE TIMING

VINx to PWRGD

VINx Going Low to High 21.9 28.8 35.2 µs 50 mV input overdrive VINx Going High to Low 5.8 7.3 8.9 µs 50 mV input overdrive

VINx to FAULT, OUTx Low

VINx Going High to Low (UV Fault) 6.1 7.5 9.2 µs 50 mV input overdrive

UP, DOWN, and UP/DOWN to FAULT,

OUTx Low, t

UDOUT

5.8 7.7 10.5 µs 1 V input overdrive External FAULT to OUTx Low Fault Hold Time 35 44 54 µs

1

Input comparators do not include hysteresis on their inputs. The comparator output passes through a digital glitch filter to remove short transients from the input

signal that would otherwise drive the state machine.

0.4 V V

SEQ_DONEL

1 µA SEQ_DONE = 5.5 V

5.5 8.6 12.1 µs 100 mV input overdrive

10 µs 1 V input overdrive

= 2.7 V, I

VCC

Output is guaranteed to be either low (V or giving a valid output level from V or V

= 1.1 V, I

VCC

= 2 mA

SINK

= 100 µA

VCC

SEQ_DONEL

= 1 V, I

= 0.4 V)

= 30 µA

SINK

Includes input glitch filter and all other internal

ays

del

UP, UP/DOWN

held low

Rev. 0 | Page 5 of 28

ADM1186

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

VCC Pin −0.3 V to +6 V VINx Pins −0.3 V to +6 V UP, DOWN, UP/DOWN Pins DLY_EN_OUTx, BLANK_DLY Pins −0.3 V to VCC + 0.3 V PWRGD, SEQ_DONE, OUTx Pins −0.3 V to +6 V FAU LT Pin Operating Temperature Range −40°C to +85°C Storage Temperature Range −65°C to +150°C Lead Temperature Convection Reflow

Peak Temperature 260°C Time at Peak Temperature ≤30 sec

Junction Temperature 125°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

−0.3 V to +6 V

Table 3. Thermal Resistance

Package Type θJA Unit

16-Lead QSOP 149.97 °C/W 20-Lead QSOP 125.80 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 28

ADM1186

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

VIN1

VIN2

VIN3

VIN4

DOWN

FAULT

DLY_EN_OUT1

DLY_EN_OUT2

UP

1

2

3

ADM1186-1

4

5

(Not to Scale)

6

7

8

9

10

TOP VIEW

20

VCC

19

OUT1

18

OUT2

17

OUT3

16

OUT4

15

PWRGD

14

SEQ_DONE

13

BLANK_DLY

12

DLY_EN_OUT4

11

DLY_EN_OUT3

07153-005

Figure 3. ADM1186-1 Pin Configuration Figure 4. ADM1186-2 Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

ADM1186-1 ADM1186-2

Mnemonic

Description

1 1 GND Chip Ground Pin. 2 2 VIN1

Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine.

3 3 VIN2

Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine.

4 4 VIN3

Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine.

5 5 VIN4

Noninverting Comparator Input. The voltage on this pin is compared with a 0.6 V reference. Can be used to monitor a voltage rail via a resistor divider. The output of this comparator is monitored by the state machine.

6 UP

Noninverting Comparator Input. A rising edge on this pin initiates a power-up sequence when the ADM1186-1 is in the WAIT START state.

7

Noninverting Comparator Input. A falling edge on this pin initiates a power-down

DOWN

sequence when the ADM1186-1 is in the POWER-UP DONE state.

6

UP/DOWN

Noninverting Comparator Input. A rising edge on this pin initiates a power-up sequence

when the ADM1186-2 is in the WAIT START state. A falling edge on this pin initiates a power-down sequence when the ADM1186-2 is in the POWER-UP DONE state.

8

FAU LT Active Low, Bidirectional, Open-Drain Pin. When an internal fault is detected by the

ADM1186-1 state machine, this pin is asserted low and the SET FAULT state is entered. An external device pulling this pin low also causes the ADM1186-1 to enter the SET FAU LT s tate.

9 DLY_EN_OUT1

Timing Input. The capacitor connected to this input sets the time delay between the UP input initiating a power-up sequence and OUT1 being asserted high. During a powerdown sequence, this input sets the time delay between OUT1 being asserted low and SEQ_DONE being asserted low.

10 7 DLY_EN_OUT2

Timing Input. The capacitor connected to this input sets the time delay between VIN1 coming into compliance and OUT2 being asserted high during a power-up sequence. During a power-down sequence, this input sets the time delay between OUT2 being asserted low and OUT1 being asserted low.

11 8 DLY_EN_OUT3

Timing Input. The capacitor connected to this input sets the tim coming into compliance and OUT3 being asserted high during a power-up sequence. During a power-down sequence, this input sets the time delay between OUT3 being asserted low and OUT2 being asserted low.

1

GND

2

VIN1

ADM1186-2

3

VIN2

VIN3

VIN4

UP/DOWN

DLY_EN_OUT2

DLY_EN_OUT3 DLY_EN_OUT4

TOP VIEW

4

(Not to Scale)

5

6

7

8

16

VCC

15

OUT1

14

OUT2

13

OUT3

12

OUT4

11

PWRGD

10

BLANK_DLY

9

e delay between VIN2

07153-006

Rev. 0 | Page 7 of 28

ADM1186

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Pin No.

ADM1186-1 ADM1186-2

12 9 DLY_EN_OUT4

13 10 BLANK_DLY

14 SEQ_DONE

15 11 PWRGD

16 12 OUT4

17 13 OUT3

18 14 OUT2

19 15 OUT1

20 16 VCC Positive Supply Input Pin. The operating supply voltage range is 2.7 V to 5.5 V.

Mnemonic Description

Timing Input. The capacitor connected to this input sets the tim coming into compliance and OUT4 being asserted high during a power-up sequence. During a power-down sequence, this input sets the time delay between OUT4 being asserted low and OUT3 being asserted low.

Timing Input. The capacitor connected to this input sets the bla time allowed between OUTx being asserted and VINx coming into compliance; otherwise, the SET FAULT state is entered.

Active High, Open-Drain Output. This output is pulled power-up sequence is complete, SEQ_DONE is asserted high. During a power-down sequence, the pin remains asserted until the time delay set by DLY_EN_OUT1 has elapsed. When a fault occurs, this pin is asserted low.

Active High, Open-Drain Output. This output is pulled state of this pin is a logical AND function of the UV threshold state of the VINx pins. When the voltage on all VINx inputs exceeds 0.6 V, PWRGD is asserted. This output is driven low if the voltage on any VINx pin is below 0.6 V.

Active High, Open-Drain Output. This output is pulled power-up sequence, this output is asserted high after the time delay set by the capacitor on DLY_EN_OUT4 has elapsed. The output is asserted low immediately after a powerdown sequence has been initiated.

Active High, Open-Drain Output. This output is pulled power-up sequence, this output is asserted high after the time delay set by the capacitor on DLY_EN_OUT3 has elapsed. During a power-down sequence, the output is asserted low after the time delay set by the capacitor on DLY_EN_OUT4 has elapsed.

Active High, Open-Drain Output. This output is pulled power-up sequence, this output is asserted high after the time delay set by the capacitor on DLY_EN_OUT2 has elapsed. During a power-down sequence, the output is asserted low after the time delay set by the capacitor on DLY_EN_OUT3 has elapsed.

Active High, Open-Drain Output. This output is pulled power-up sequence, this output is asserted high after the time delay set by the capacitor on DLY_EN_OUT1 has elapsed (ADM1186-1) or immediately after a rising edge on UP/DOWN (ADM1186-2). During a power-down sequence, the output is asserted low after the time delay set by the capacitor on DLY_EN_OUT2 has elapsed.

e delay between VIN3

nking time. This is the

low when V

= 1 V. When the

CC

= 1 V. The output

CC

= 1 V. During a

CC

= 1 V. During a

CC

= 1 V. During a

CC

= 1 V. During a

CC

Rev. 0 | Page 8 of 28

ADM1186

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TYPICAL PERFORMANCE CHARACTERISTICS

160

140

120

100

80

60

SUPPLY CURRENT (µA)

40

20

0

0 0.5 1.0 1. 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5. 5

SUPPLY VOLTAGE (V)

Figure 5. Supply Current vs. Supply Voltage

150

145

140

135

130

SUPPLY CURRENT (µA)

125

120

–40 –20 0 20 40 60 80

VCC = 5.5V

VCC = 3.3V

VCC = 2.7V

TEMPERATURE (°C)

Figure 6. Supply Current vs. Temperature

605

604

603

602

601

600

599

598

INPUT THRESHOLD (mV)

X

VIN

597

596

595

–40 0 6020–20 40 80

VCC = 3.3V

TEMPERATURE ( °C)

Figure 7. VINx Input Threshold vs. Temperature

07153-007

07153-008

07153-009

38

36

34

32

30

28

26

24

POSITI VE GLI TCH DURATION (µs)

22

20

0 50 100 150 200

VCC = 3.3V

OVERDRIVE (mV)

Figure 8. VINx Input Positive Glitch Immunity vs. Input Overdrive

18

16

14

12

10

8

6

4

NEGATIVE GLITCH DURATION (µs)

2

0

0 50 100 150 200

Figure 9. VINx Input Negative Glitch I

31.0

30.5

30.0

29.5

29.0

28.5

28.0

27.5

27.0

POSITI VE GLI TCH DURATION ( µs)

26.5

26.0 –40 –20 0 20 40 60 80

VCC = 3.3V

OVERDRIVE (mV)

mmunity vs. Input Overdrive

VCC = 3.3V

TEMPERATURE (° C)

Figure 10. VINx Input Positive Glitch Immunity vs. Temperature

07153-010

07153-011

07153-012

Rev. 0 | Page 9 of 28

ANALOG DEVICES ADM1186 Service Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

APPLICATION DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS