Controls supply rails from 2.7 V to 16.5 V
Allows protected board removal and insertion to a live
backplane
External sense resistor provides adjustable analog current
limit with circuit breaker
Peak fault current limited with fast response
Charge pumped gate drive for external N-FET switch
Current sense output
Soft start inrush current control
Automatic retry or latch-off during current fault
Undervoltage lockout
8-lead, TSOT package
APPLICATIONS
Hot swap board insertion: line cards, raid systems
Industrial high-side switches/circuit breakers
Electronic circuit breakers
with Current Sense Output
ADM1171
GENERAL DESCRIPTION
The ADM1171 is a hot swap controller that safely enables a
printed circuit board to be removed and inserted to a live
backplane. This is achieved using an external N-channel power
MOSFET with a current control loop that monitors the load
current through a sense resistor. An internal charge pump is
used to enhance the gate of the N-channel FET. When an
overcurrent condition is detected, the gate voltage of the FET is
reduced to limit the current flowing through the sense resistor.
During an overcurrent condition, the TIMER cap determines
the amount of time the FET remains at a current limiting mode
of operation until it is shut down. The ON (ONenable input for the device and can be used to monitor the
input supply voltage. The ADM1171 operates with a supply
voltage ranging from 2.7 V to 16.5 V.
The ADM1171 features soft start to provide the user with a
ca
pacitor programmable ramping reference to the internal
current sense comparator. This provides a linearly increasing
current limit at startup at a rate set by C
SS
and limit large inrush currents.
The ADM1171 also features a current sense output (CSOUT)
p
in. The voltage on the CSOUT pin represents the voltage drop
across the sense resistor gained up by a factor of 20.
This device is available in two options: the ADM1171-1 with
a
utomatic retry for overcurrent fault and the ADM1171-2 with
latch-off for an overcurrent fault. Toggling the ON (ONpin resets a latched fault. The ADM1171 is packaged in an
8-lead TSOT.
CLR
) pin is the
. This helps to reduce
CLR
)
FUNCTIONAL BLOCK DIAGRAM
= 5VV
IN
GNDGND
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
VCC = 2.7 V to 16.5 V, TA = −40°C to +85°C, typical values at TA = 25°C, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Conditions
VCC PIN
Operating Voltage Range VCC 2.7 16.5 V
Supply Current ICC 0.65 0.8 mA
Undervoltage Lockout V
Undervoltage Lockout Hysteresis V
ON (ON-CLR) PIN
Input Current
Threshold VON 1.22 1.3 1.38 V ON rising
Threshold Hysteresis V
SENSE PIN
Hot Swap Operating Range 2.7 16.5 V
Input Current
Circuit Breaker Limit Voltage VCB 44 50 56 mV VCB = (VCC − V
GATE PIN
Drive Voltage V
6.0 8 12 V V
8.75 10 12 V V
7.5 9 12 V V
5.56 8 12 V V
Pull-Up Current −6.5 −12 −14.5 A V
Pull-Down Current 4 mA
Pull-Down Current
TIMER PIN
Pull-Up Current I
−25 −60 −100 µA During current fault, V
Pull-Down Current I
100 µA Normal operation, V
Threshold High V
Threshold Low V
SS PIN
Soft Start Pull-up Current 10 µA
Current Setting Gain 20 V/V VSS/V
Soft Start Completion Voltage 1 V
Pull-Down Current 50 µA During fault
CSOUT PIN
Total Output Voltage Error −5 0 +5 % VCC − SENSE = 50 mV
Gain 20 V/V VCC − SENSE = 10 mV to 50 mV
Gain Accuracy 0 ±2.5 %
Offset ±1 mV
Output Impedance 14 kΩ
t
OFF
Turn-Off Time (TIMER Rise to GATE Fall) 2 µs V
Turn-Off Time (ON Fall to GATE Fall) 40 µs VON = 5 V to 0 V step, VCC = 5 V
Turn-Off Time (VCC Fall to IC Reset) 40 µs VCC = 5 V to 2 V step, VON = 5 V
2.4 2.525 2.65 V VCC rising
UVLO
40 mV
UVLOHYS
I
−1 0 +1 µA
INON
50 mV
ONHYST
I
5 10 15 µA
INSENSE
4.6 7.5 10 V V
GATE
25 mA V
− VCC, VCC = 3.0 V
GATE
− VCC, VCC = 3.3 V
GATE
− VCC, VCC = 5 V
GATE
− VCC, VCC = 12 V
GATE
− VCC, VCC = 15 V
GATE
= 0 V
GATE
= 3 V, VCC = 5 V, ON (ON-CLR) = low
V
GATE
= 3 V, VCC < UVLO
GATE
−2 −5 −8.5 µA Initial cycle, V
TIMERUP
2 3.5 µA After Cct breaker tip, V
TIMERDN
1.22 1.3 1.38 V TIMER rising
TIMERH
0.15 0.2 0.25 V TIMER falling
TIMERL
SENSE
= 0 V to 2 V step, VCC = VON = 5 V
TIMER
SENSE
TIMER
)
= 1 V
TIMER
TIMER
TIMER
= 1 V
= 1 V
= 1 V
Rev. 0 | Page 3 of 16
ADM1171
www.BDTIC.com/ADI
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
VCC Pin −0.3 V to +20 V
SENSE Pin −0.3 V to +20 V
VCC − SENSE ±5 V
TIMER Pin −0.3 V to (VCC + 0.3 V)
ON (ON-CLR) Pin
SS Pin –0.3 V to (VCC + 0.3 V)
CSOUT Pin –0.3 V to (VCC + 0.3 V)
GATE Pin −0.3 V to (VCC + 11 V)
Storage Temperature Range −65°C to +125°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (10 sec) 300°C
Junction Temperature 150°C
−0.3 V to +20 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
ma
y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA Unit
8-Lead TSOT 152.9 °C/W
Rev. 0 | Page 4 of 16
ADM1171
A
www.BDTIC.com/ADI
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
ADM1171-1AUJ
TIMER
GND
SS
ON
1
2
TOP VIEW
(Not to Scale)
3
4
8
7
6
5
V
CC
SENSE
CSOUT
GATE
Figure 2. Pin Configuration, 1AUJ Model
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 TIMER
Timer Input Pin. The initial and circuit breaker timing cycles a
delay is 272.9 ms/F, and 21.7 ms/µF for a circuit breaker delay. When the TIMER pin is pulled beyond the upper
threshold, the GATE turns off.
2 GND Chip Ground Pin.
3 SS
Soft Start Pin. An external capacitor between the SS pin and GND sets the ramp rate of the current limit
reference.
4
ON (ON-CLR
) Input Pin. The ON (ON-CLR) pin is an input to a comparator that has a low-to-high threshold of 1.3 V with 80 mV
hysteresis and a glitch filter. The ADM1171 is reset when the ON (ON-CLR
high, the ADM1171 is enabled. A rising edge on this pin has the added function of clearing a fault and restarting
the device on the latched off model, the ADM1171-2.
5 GATE
Gate Output Pin. An internal charge pump provides a 12 µA pull-up current to drive the gate of an N-channel
MOSFET. In an overcurrent condition, the ADM1171 controls the external FET to maintain a constant load
current.
6 CSOUT
Current Sense Output. The voltage on this pin represents the differential voltage across the V
gained up by a factor of 20.
7 SENSE
Current Limit Sense Input Pin. The current limit is set via a sense resistor between the V
overcurrent condition, the gate of the FET is controlled to maintain the SENSE voltage at 50 mV. When this limit is
reached, the TIMER circuit breaker mode is activated. The circuit breaker limit can be disabled by connecting the
V
pin and SENSE pin together.
CC
8 V
CC
Positive Supply Input Pin. The ADM1171 operates between 2.7
circuit with a glitch filter resets the ADM1171 when the supply voltage drops below the specified UVLO limit.
DM1171-2AUJ
TIMER
1
2
GND
05125-006
ON-CLR
SS
TOP VIEW
(Not to Scale)
3
4
8
7
6
5
V
CC
SENSE
CSOUT
GATE
05125-007
Figure 3. Pin Configuration, 2AUJ Model
re set by this external capacitor. The initial timing
) pin is low. When the ON (ON-CLR) pin is
and SENSE pins
CC
and SENSE pin. In an
CC
V to 16.5 V. An undervoltage lockout (UVLO)
Rev. 0 | Page 5 of 16
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