ANALOG DEVICES ADM1169 Service Manual

Super Sequencer with Margining Control

A

FEATURES

Complete supervisory and sequencing solution for up to

8 supplies 16-event deep black box nonvolatile fault recording 8 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C

<1.0% accuracy across all voltages and temperatures 4 selectable input attenuators allow supervision of supplies to

14.4 V on VH

6 V on VP1 to VP3 (VPx) 4 dual-function inputs, VX1 to VX4 (VXx)

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input 8 programmable driver outputs, PDO1 to PDO8 (PDOx)

Open-collector with external pull-up

Push/pull output, driven to VDDCAP or VPx

Open-collector with weak pull-up to VDDCAP or VPx

Internally charge-pumped high drive for use with external

NFET (PDO1 to PDO6 only)

Sequencing engine (SE) implements state machine control of

PDO outputs

State changes conditional on input events Enables complex control of boards Power-up and power-down sequence control Fault event handling Interrupt generation on warnings Watchdog function can be integrated in SE

Program software control of sequencing through SMBus Complete voltage margining solution for 4 voltage rails 4 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage

adjustment via dc-to-dc converter trim/feedback node 12-bit ADC for readback of all supervised voltages Reference input (REFIN) has 2 input options

Driven directly from 2.048 V (±0.25%) REFOUT pin

More accurate external reference for improved ADC

performance

Device powered by the highest of VPx, VH for improved

redundancy User EEPROM: 256 bytes Industry-standard 2-wire bus interface (SMBus) Guaranteed PDO low with VH, VPx = 1.2 V Available in 32-lead, 7 mm × 7 mm LQFP and 40-lead,

6 mm × 6 mm LFCSP packages

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

and Nonvolatile Fault Recording

ADM1169

APPLICATIONS

Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies

FUNCTIONAL BLOCK DIAGRAM

FAULT

RECORDING

VCCP

(HV CAPABLE O F

SDA SCL A1 A0

SMBus

INTERFACE

EEPROM

CONFIG URABLE

OUTPUT

DRIVERS

DRIVING GATES

OF NFET)

CONFIG URABLE

OUTPUT

DRIVERS

(LV CAPABLE

OF DRIV ING

LOGIC SIGNALS)

VDD

ARBITRATO R

GND

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PDOGND

VDDCAP

REFIN REFO UT REFGND

VX1

VX2

VX3

VX4

VP1

VP2

VP3

GND

ADM1169

12-BIT

SAR ADC

MUX

CLOSED-LOO P MARGINI NG SYSTEM

DUAL-

FUNCTION

INPUTS

(LOGIC INPUTS

OR

SFDs)

PROGRAMMABLE

RESET

GENERATO RS

V

OUT

DAC

DAC1

(SFDs)

V

OUT

DAC

DAC2

V

OUT

DAC

DAC3

VH

SEQUENCING

V

OUT

DAC

DAC4

VREF

ENGINE

Figure 1.

GENERAL DESCRIPTION

The ADM1169 Super Sequencer® is a configurable supervisory/ sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple supply systems. In addition to these functions, the ADM1169 integrates a 12-bit ADC and four 8-bit voltage output DACs. These circuits can be used to implement a closed-loop margining system that enables supply adjustment by altering either the feedback node or reference of a dc-to-dc converter using the DAC outputs.

Supply margining can be performed with a minimum of external components. The margining loop can be used for in-circuit testing of a board during production (for example, to verify board functionality at −5% of nominal supplies), or it can be used dynamically to accurately control the output voltage of a dc-to-dc converter.

For more information about the ADM1169 register map, refer to the AN-721 Application Note.

09475-001

ADM1169

REVISION HISTORY

4/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 36

ADM1169

The device also provides up to eight programmable inputs for monitoring undervoltage faults, overvoltage faults, or out-ofwindow faults on up to eight supplies. In addition, there are eight programmable outputs that can be used as logic enables. Six of these programmable outputs can also provide up to a 12 V output for driving the gate of an NFET that can be placed in the path of a supply.

The logical core of the device is a SE. This state machine-based construction provides up to 63 different states. This design enables very flexible sequencing of the outputs based on the condition of the inputs.

DETAILED BLOCK DIAGRAM

A block of nonvolatile EEPROM is available that can be used to store user-defined information and can also be used to hold a number of fault records that are written by the sequencing engine defined by the user when a particular fault or sequence occurs.

The ADM1169 is controlled via configuration data that can be programmed into an EEPROM. The entire configuration can be programmed using an intuitive GUI-based software package provided by Analog Devices, Inc.

VX1

VX2

VX3

VX4

VP1

VP2

VP3

AGND

VDDCAP

VH

ADM1169

SELECTABLE ATTENUATOR

VDD

ARBITRATO R

SAR ADC

GPI SIGNAL

CONDITI ONING

GPI SIGNAL

CONDITI ONING

REG 5.25V

CHARGE PUMP

REFOUTREFIN REFGND

VREF

12-BIT

SFD

SEQUENCING

SFD

V

OUT

DAC

SDA SCL A1 A0

SMBus

INTERFACE

DEVICE

CONTROL LER

FAULT

RECORDING

ENGINE

V

OUT

DAC

OSC

EEPROM

CONFIGURABLE

OUTPUT DRIVER

(HV)

CONFIGURABLE

OUTPUT DRIVER

(HV)

CONFIGURABLE

OUTPUT DRIVER

(LV)

CONFIGURABLE

OUTPUT DRIVER

(LV)

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PDOGND

VCCPGND

DAC1

DAC2

DAC3

DAC4

09475-002

Figure 2. Detailed Block Diagram

Rev. 0 | Page 3 of 36

ADM1169

SPECIFICATIONS

VH = 3.0 V to 14.4 V,1 VPx = 3.0 V to 6.0 V,1 TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY ARBITRATION

VH, VPx 3.0 V Minimum supply required on one of VH, VPx VPx 6.0 V Maximum VDDCAP = 5.1 V, typical VH 14.4 V VDDCAP = 4.75 V VDDCAP 2.7 4.75 5.4 V Regulated LDO output C

10 μF

VDDCAP

POWER SUPPLY

Supply Current, IVH, I

Additional Currents

All PDOx FET Drivers On 1 mA

Current Available from VDDCAP 2 mA

DAC Supply Currents 2.2 mA Four DACs on with 100 μA maximum load on each ADC Supply Current 1 mA Running round-robin loop EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V

SUPPLY FAULT DETECTORS

VH Pin

Input Impedance 52 kΩ Input Attenuator Error ±0.05 % Midrange and high range Detection Ranges

High Range 6 14.4 V

Midrange 2.5 6 V

VPx Pins

Input Impedance 52 kΩ Input Attenuator Error ±0.05 % Low range and midrange Detection Ranges

Midrange 2.5 6 V

Low Range 1.25 3 V

Ultralow Range 0.573 1.375 V No input attenuation error

VXx Pins

Input Impedance 1 MΩ Ultralow Range 0.573 1.375 V No input attenuation error

Absolute Accuracy ±1 %

Threshold Resolution 8 Bits Digital Glitch Filter 0 μs Minimum programmable filter length

100 μs Maximum programmable filter length

4.2 6 mA

VPx

Minimum recommended decoupling capacitance

VDDCAP = 4.75 V, PDO1 to PDO8 off, DACs off, ADC off

VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each, PDO7 to PDO8 off

Maximum additional load that can be drawn from all PDO pull-ups to VDDCAP

Internal reference VREF error + DAC nonlinearity + comparator offset error

Rev. 0 | Page 4 of 36

ADM1169

Parameter Min Typ Max Unit Test Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER

Signal Range 0 V

Input Reference Voltage on REFIN Pin, V

2.048 V

REFIN

Resolution 12 Bits

INL ±2.5 LSB Endpoint corrected, V

Gain Error ±0.05 % V

Conversion Time 0.44 ms One conversion on one channel

84 ms All eight channels selected, averaging enabled

Offset Error ±2 LSB V

Input Noise 0.25 LSB

BUFFERED VOLTAGE OUTPUT DACS

Resolution 8 Bits

Code 0x80 Output Voltage

Range 1 0.592 0.6 0.603 V Range 2 0.796 0.8 0.803 V Range 3 0.996 1 1.003 V

Range 4 1.246 1.25 1.253 V Output Voltage Range 601.25 mV Same range, independent of center point LSB Step Size 2.36 mV INL ±0.75 LSB Endpoint corrected DNL ±0.4 LSB Gain Error 1 % Maximum Load Current (Source) 100 μA Maximum Load Current (Sink) 100 μA Maximum Load Capacitance 50 pF Settling Time into 50 pF Load 2 μs Load Regulation 2.5 mV Per mA PSRR 60 dB DC

40 dB 100 mV step in 20 ns with 50 pF load REFERENCE OUTPUT

Reference Output Voltage 2.043 2.048 2.053 V No load Load Regulation −0.25 mV Sourcing current, I +0.25 mV Sinking current, I Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability PSRR 60 dB DC

REFIN

V

The ADC can convert signals presented to the VH, VPx, and VXx pins; VPx and VH input signals are attenuated depending on the selected range; a signal at the pin corresponding to the selected range is from 0.573 V to 1.375 V at the ADC input

= 2.048 V

REFIN

= 2.048 V

REFIN

= 2.048 V

REFIN

Direct input (no attenuator)

rms

Four DACs are individually selectable for centering on one of four output voltage ranges

= −100 μA

DACxMAX

= +100 μA

DACxMAX

Rev. 0 | Page 5 of 36

ADM1169

Parameter Min Typ Max Unit Test Conditions/Comments

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1 to PDO6) Output Impedance 500 kΩ VOH 11 12.5 14 V IOH = 0 μA

10.5 12 13.5 V IOH = 1 μA I

20 μA 2 V < V

OUTAVG

Standard (Digital Output) Mode (PDO1 to PDO8)

VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA

4.5 V VPU to VPx = 6.0 V, IOH = 0 mA V VOL 0 0.50 V IOL = 20 mA

2

I

20 mA Maximum sink current per PDOx pin

OL

2

I

60 mA Maximum total sink for all PDOx pins

SINK

R

16 20 29 kΩ Internal pull-up

PULL-UP

I

(VPx)2 2 mA

SOURCE

Three-State Output Leakage Current 10 μA V Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock

DIGITAL INPUTS (VXx, A0, A1)

Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V Input High Current, IIH −1 μA VIN = 5.5 V Input Low Current, IIL 1 μA VIN = 0 V Input Capacitance 5 pF Programmable Pull-Down Current, I

PULL-DOWN

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.8 V Output Low Voltage, V

2

0.4 V I

OL

SERIAL BUS TIMING See Figure 38

Clock Frequency, f Bus Free Time, t Start Setup Time, t Stop Setup Time, t Start Hold Time, t SCL Low Time, t SCL High Time, t

400 kHz

SCLK

1.3 μs

BUF

0.6 μs

SU;STA

0.6 μs

SU;STO

0.6 μs

HD;STA

1.3 μs

LOW

0.6 μs

HIGH

SCL, SDA Rise Time, tR 300 ns SCL, SDA Fall Time, tF 300 ns Data Setup Time, t Data Hold Time, t

100 ns

SU;DAT

250 ns

HD;DAT

Input Low Current, IIL 1 μA VIN = 0 V

SEQUENCING ENGINE TIMING

State Change Time 10 μs

1

At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.

2

Specification is not production tested but is supported by characterization data at initial product release.

− 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA

PU

20 μA

< 7 V

OH

Current load on any VPx pull-ups, that is, total source current available through any number of PDO pull-up switches configured onto any one VPx pin

= 14.4 V

PDO

VDDCAP = 4.75 V, T

= 25°C, if known logic state

A

is required

= −3.0 mA

OUT

Rev. 0 | Page 6 of 36

ADM1169

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage on VH Pin 16 V Voltage on VPx Pins 7 V Voltage on VXx Pins −0.3 V to +6.5 V Voltage on A0, A1 Pins −0.3 V to +7 V Voltage on REFIN, REFOUT Pins 5 V Voltage on VDDCAP, VCCP Pins 6.5 V Voltage on DACx Pins 6.5 V Voltage on PDOx Pins 16 V Voltage on SDA, SCL Pins 7 V Voltage on GND, AGND, PDOGND,

REFGND Pins

Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (TJ max) 150°C Storage Temperature Range −65°C to +150°C Lead Temperature

Soldering Vapor Phase, 60 sec 215°C

ESD Rating, All Pins 2000 V

−0.3 V to +0.3 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

32-Lead LQFP 54 °C/W 40-Lead LFCSP 26.5 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. 0 | Page 7 of 36

ADM1169

R

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

VDDCAP

SDA

SCLA1A0

VCCP

PDOGND

25

24

PDO1 PDO2 PDO3 PDO4 PDO5 PDO6 PDO7 PDO8

17

16

DAC1

DAC2

DAC3

DAC4

VX1 VX2 VX3 VX4 VP1 VP2 VP3

VH

32

1

8

PIN 1 INDICATO R

ADM1169

(Not to Scale)

9

AGND

REFGND

TOP VIEW

REFIN

REFOUT

Figure 3. 32-Lead LQFP Pin Configuration

VDDCAP

GND

39

40

PIN 1

1

NC VX1 VX2 VX3 VX4

NC VP1 VP2 VP3

10

VH

09475-003

NOTES

1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

2. THE LFCS P HAS AN EXPOSE D PAD ON THE BOTTOM. THIS PAD IS A NO CONNECT (NC). IF POSSIBLE, THIS PAD SHOULD BE SO LDERED TO T HE BOARD FO IMPROVED MECHANICAL STABILITY.

2 3 4 5 6 7 8 9

INDICATO R

ADM1169

TOP VIEW

(Not to Scale)

11

12

AGND

REFGND

Figure 4. 40-Lead LFCSP Pin Configuration

A0

A1

SCL

SDA

NC

37

38

13

14

REFIN

REFOUT

36

15

NC

35

16

NC

34

17

DAC1

33

18

DAC2

VCCP

32

19

DAC3

PDOGND

31

20

DAC4

PDO1

30 29

PDO2

28

PDO3

27

PDO4 PDO5

26 25

PDO6 PDO7

24

PDO8

23

NC

22

NC

21

09475-004

Table 4. Pin Function Descriptions

Pin No.

LQFP

2

N/A

LFCSP1

1, 6, 15,

Mnemonic

NC No Connect.

Description

16, 21, 22, 37, 38

1 to 4 2 to 5 VX1 to VX4 (VXx)

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.

5 to 7 7 to 9 VP1 to VP3 (VPx)

Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation on a potential divider connected to these pins, the output of which connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6 V, from 1.25 V to 3 V, and from 0.573 V to 1.375 V.

8 10 VH

High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation on a potential divider connected to this pin, the output of which connects to a supply fault detector. This pin allows thresholds from 6 V to 14.4 V and from 2.5 V to 6 V.

3

9 11 AGND 10 12 REFGND 11 13 REFIN

Ground Return for Input Attenuators.

3

Ground Return for On-Chip Reference Circuits.

Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage. The on-board reference can be used by connecting the REFOUT pin to the REFIN pin. This is the normal configuration.

12 14 REFOUT

2.048 V Reference Output. A reservoir capacitor must always be connected between this pin and GND, even if the REFIN pin is driven by an external reference. A 10 μF capacitor is recommended

for this purpose. 13 to 16 17 to 20 DAC1 to DAC4 17 to 24 23 to 30 PDO8 to PDO1 25 31 PDOGND

3

Ground Return for Output Drivers.

26 32 VCCP

Voltage Output DACs. These pins default to high impedance at power-up.

Programmable Output Drivers.

Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this

pin and GND. A 10 μF capacitor is recommended for this purpose. 27 33 A0 28 34 A1 29 35 SCL

Logic Input. This pin sets the seventh bit of the SMBus interface address.

Logic Input. This pin sets the sixth bit of the SMBus interface address.

SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up. 30 36 SDA SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.

Rev. 0 | Page 8 of 36

ADM1169

Pin No.

LQFP LFCSP1

31 39 VDDCAP

32 40 GND3 Supply Ground. N/A2 EPAD

1

The LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.

2

N/A is not applicable.

3

In a typical application, all ground pins are connected together.

Mnemonic Description

Device Supply Voltage. Linearly regulated from the highest of the VPx and VH pins to a typical of

4.75 V. Note that a capacitor must be connected between this pin and GND. A 10 μF capacitor is recommended for this purpose.

Exposed Pad. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.

Rev. 0 | Page 9 of 36

ADM1169

TYPICAL PERFORMANCE CHARACTERISTICS

(V)

VDDCAP

V

6

5

4

3

2

1

0

0654321

Figure 5. V

V

VP1

VDDCAP

(V)

vs. V

09475-050

VP1

180

160

140

120

100

(µA)

80

VP1

I

60

40

20

0

0123456

(V)

V

VP1

Figure 8. I

VP1

vs. V

(VP1 Not as Supply)

VP1

09475-053

6

5

4

(V)

3

VDDCAP

V

2

1

0

011412108642

(V)

V

VH

Figure 6. V

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

VP1

I

2.0

1.5

1.0

0.5

0

0123456

Figure 7. I

vs. V

VP1

vs. VVH

VDDCAP

(V)

V

VP1

(VP1 as Supply)

VP1

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

VH

I

2.0

1.5

1.0

0.5

350

300

250

200

(µA)

VH

150

I

100

50

0

011412108642

0

0654321

Figure 9. I

Figure 10. I

vs. VVH (VH as Supply)

VH

vs. VVH (VH Not as Supply)

VH

6

09475-051

09475-052

6

(V)

V

VH

V

(V)

VH

09475-054

09475-055

Rev. 0 | Page 10 of 36

ADM1169

14

12

(V)

10

PDO1

8

6

4

CHARGE-PUMPED V

2

0

0 15.012.510.07.55.02.5

Figure 11. Charge-Pumped V

I

(µA)

LOAD

(FET Drive Mode) vs. I

PDO1

LOAD

09475-056

1.0

0.8

0.6

0.4

0.2

0

DNL (LS B)

–0.2

–0.4

–0.6

–0.8

–1.0

CODE

40001000 2000 30000

09475-066

Figure 14. DNL for ADC

5.0

4.5

4.0

3.5

3.0

(V)

2.5

PDO1

V

2.0

1.5

1.0

0.5

4.5

4.0

3.5

3.0

2.5

(V)

2.0

PDO1

V

1.5

1.0

0.5

0

0654321

Figure 12. V

0

0605040302010

Figure 13. V

VP1 = 3V

(mA)

I

LOAD

(Strong Pull-Up to VPx) vs. I

PDO1

VP1 = 5V

VP1 = 3V

(µA)

I

LOAD

(Weak Pull-Up to VPx) vs. I

PDO1

VP1 = 5V

LOAD

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 4000300020001000

09475-057

CODE

09475-063

Figure 15. INL for ADC

12000

10000

8000

6000

HITS PER CODE

4000

2000

0

09475-058

25

Figure 16. ADC Noise, Midcode Input, 10,000 Reads

9894

CODE

81

204920482047

09475-064

Rev. 0 | Page 11 of 36

ANALOG DEVICES ADM1169 Service Manual

FEATURES

APPLICATIONS

FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

DETAILED BLOCK DIAGRAM

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS