ANALOG DEVICES ADM1168 Service Manual

Super Sequencer and Monitor with

V

FEATURES

Complete supervisory and sequencing solution for up to

8 supplies
16 event deep black box nonvolatile fault recording
8 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C

<1.0% accuracy across all voltages and temperatures
4 selectable input attenuators allow supervision of supplies to

14.4 V on VH

6 V on VP1 to VP3 (VPx)
4 dual-function inputs, VX1 to VX4 (VXx)

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input
8 programmable driver outputs, PDO1 to PDO8 (PDOx)

Open-collector with external pull-up

Push/pull output, driven to VDDCAP or VPx

Open-collector with weak pull-up to VDDCAP or VPx

Internally charge-pumped high drive for use with external

NFET (PDO1 to PDO6 only)

Sequencing engine (SE) implements state machine control of

PDO outputs

State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus

Device powered by the highest of VPx, VH for improved

redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 32-lead, 7 mm × 7 mm LQFP

APPLICATIONS

Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies

Nonvolatile Fault Recording

ADM1168

FUNCTIONAL BLOCK DIAGRAM

REFOUT REFGND

VREF

ADM1168

VX1

VX2

VX3

VX4

VP1

VP2

VP3

VH

AGND

DDCAP

DUAL-

FUNCTION

INPUTS

(LOGIC INPUTS

OR

SFDs)

PROGRAMMABLE

RESET

GENERATORS

(SFDs)

VDD

ARBITRATO R

VCCP

SEQUENCING

ENGINE

GND

Figure 1.

GENERAL DESCRIPTION

The ADM1168 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems.

The device also provides up to eight programmable inputs for
monitoring undervoltage faults, overvoltage faults, or out-of-window
faults on up to eight supplies. In addition, eight programmable
outputs can be used as logic enables. Six of these programmable
outputs can also provide up to a 12 V output for driving the gate
of an NFET that can be placed in the path of a supply.

The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs based
on the condition of the inputs.

A block of nonvolatile EEPROM is available that can be used to
store user-defined information and may also be used to hold a
number of fault records that are written by the sequencing engine
defined by the user when a particular fault or sequence occurs.

The ADM1168 is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can be
programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.

For more information about the ADM1168 register map, refer

AN-721 Application Note.

to the

SDASCLA1A0

SMBus

INTERFACE

EEPROMFAULT RECO RDING

CONFIGURABLE

OUTPUT

DRIVERS

(HV CAPABLE OF

DRIVING GATES

OF NFET)

CONFIGURABLE

OUTPUT

DRIVERS

(LV CAPABLE

OF DRIVING

LOGI C SIGNALS)

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PDOGND

09474-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2011 Analog Devices, Inc. All rights reserved.

ADM1168

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Detailed Block Diagram .................................................................. 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Powering the ADM1168................................................................ 10

Inputs................................................................................................ 11

Supply Supervision..................................................................... 11

Programming the Supply Fault Detectors............................... 11

Input Comparator Hysteresis.................................................... 12

Input Glitch Filtering ................................................................. 12

Supply Supervision with VXx Inputs....................................... 13

VXx Pins as Digital Inputs........................................................ 13

Outputs ............................................................................................ 14

Supply Sequencing Through Configurable Output Drivers. 14

Default Output Configuration.................................................. 14

Sequencing Engine......................................................................... 15

Overview ..................................................................................... 15

Warnings...................................................................................... 15

SMBus Jump (Unconditional Jump)........................................ 15

Sequencing Engine Application Example............................... 16

Fault and Status Reporting........................................................ 17

Nonvolatile Black Box Fault Recording................................... 17

Black Box Writes with No External Supply ............................ 18

Applications Diagram.................................................................... 19

Communicating with the ADM1168........................................... 20

Configuration Download at Power-Up................................... 20

Updating the Configuration ..................................................... 20

Updating the Sequencing Engine............................................. 21

Internal Registers........................................................................ 21

EEPROM ..................................................................................... 21

Serial Bus Interface..................................................................... 22

SMBus Protocols for RAM and EEPROM.............................. 24

Write Operations........................................................................ 24

Read Operations......................................................................... 25

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

4/11—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

ADM1168

DETAILED BLOCK DIAGRAM

VX1

VX2

VX3

VX4

VP1

VP2

ADM1168

SELECTABLE

ATTENUATOR

REFOUT REFGND

VREF

GPI SIGNAL

CONDITIONING

SFD

GPI SIGNAL

CONDITIONING

SFD

SFD

SDA SCL A1 A0

SMBus

INTERFACE

DEVICE

CONTROLLER

FAULT

RECORDING

SEQUENCING

ENGINE

OSC

EEPROM

CONFIGURABLE

OUTPUT DRIVER

(HV)

CONFIGURABLE

OUTPUT DRIVER

(HV)

CONFIGURABLE

OUTPUT DRIVER

(LV)

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

VP3

VH

AGND

VDDCAP

SELECTABLE

ATTENUATOR

VDD

ARBITRATOR

CHARGE PUMP

GND

SFD

REG 5.25V

VCCP

CONFIGURABLE

OUTPUT DRIVER

(LV)

PDO8

PDOGND

09474-002

Figure 2. Detailed Block Diagram

Rev. 0 | Page 3 of 28

ADM1168

SPECIFICATIONS

VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY ARBITRATION

VH, VPx 3.0 V Minimum supply required on one of the VH, VPx pins
VPx 6.0 V Maximum VDDCAP = 5.1 V typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
C

10 μF Minimum recommended decoupling capacitance

VDDCAP

POWER SUPPLY

Supply Current, IVH, I
Additional Currents

All PDOx FET Drivers On 1 mA

Current Available from VDDCAP 2 mA

EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V

SUPPLY FAULT DETECTORS

VH Pin

Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges

High Range 6 14.4 V

Midrange 2.5 6 V

VPx Pins

Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges

Midrange 2.5 6 V

Low Range 1.25 3 V

Ultralow Range 0.573 1.375 V No input attenuation error

VXx Pins

Input Impedance 1 MΩ
Detection Ranges

Ultralow Range 0.573 1.375 V No input attenuation error

Absolute Accuracy ±1 %

Threshold Resolution 8 Bits
Digital Glitch Filter 0 μs Minimum programmable filter length

100 μs Maximum programmable filter length

REFERENCE OUTPUT

Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current

0.25 mV Sinking current
Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability
PSRR 60 dB DC

4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO8 off

VPx

VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO8 off

Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP

Internal reference VREF error + DAC nonlinearity +
comparator offset error

Rev. 0 | Page 4 of 28

ADM1168

Parameter Min Typ Max Unit Test Conditions/Comments

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge Pump) Mode

(PDO1 to PDO6)
Output Impedance 500 kΩ
V

11 12.5 14 V IOH = 0 μA

OH

10.5 12 13.5 V IOH = 1 μA
I

20 μA 2 V < VOH < 7 V

OUTAVG

Standard (Digital Output) Mode

(PDO1 to PDO8)
VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA

4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
V
VOL 0 0.50 V IOL = 20 mA

2

I

20 mA Maximum sink current per PDO pin

OL

2

I

60 mA Maximum total sink for all PDO pins

SINK

R

16 20 29 kΩ Internal pull-up

PULL-UP

I

(VPx)2 2 mA

SOURCE

Three-State Output Leakage Current 10 μA V

Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock

DIGITAL INPUTS (VXx, A0, A1)

Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V

Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V

Input High Current, IIH −1 μA VIN = 5.5 V

Input Low Current, IIL 1 μA VIN = 0 V

Input Capacitance 5 pF

Programmable Pull-Down Current,

PULL-DOWN

I

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH 2.0 V

Input Low Voltage, VIL 0.8 V

Output Low Voltage, V

2

0.4 V I

OL

SERIAL BUS TIMING See Figure 27

Clock Frequency, f

Bus Free Time, t

Start Setup Time, t

Stop Setup Time, t

Start Hold Time, t

SCL Low Time, t

SCL High Time, t

400 kHz

SCLK

1.3 μs

BUF

0.6 μs

SU;STA

0.6 μs

SU;STO

0.6 μs

HD;STA

1.3 μs

LOW

0.6 μs

HIGH

SCL, SDA Rise Time, tr 300 ns

SCL, SDA Fall Time, tf 300 ns

Data Setup Time, t

Data Hold Time, t

100 ns

SU;DAT

250 ns

HD;DAT

Input Low Current, IIL 1 μA VIN = 0 V

SEQUENCING ENGINE TIMING

State Change Time 10 μs

1

At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.

2

Specification is not production tested but is supported by characterization data at initial product release.

− 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA

PU

Current load on any VPx pull-ups, that is, total source
current available through any number of PDO pull-up
switches configured onto any one VPx pin

= 14.4 V

PDO

20 μA VDDCAP = 4.75 V, T

= −3.0 mA

OUT

= 25°C, if known logic state is required

A

Rev. 0 | Page 5 of 28

ADM1168

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage on VH Pin 16 V
Voltage on VPx Pins 7 V
Voltage on VXx Pins −0.3 V to +6.5 V
Voltage on A0, A1 Pins −0.3 V to +7 V
Voltage on REFOUT Pin 5 V
Voltage on VDDCAP, VCCP Pins 6.5 V
Voltage on PDOx Pins 16 V
Voltage on SDA, SCL Pins 7 V
Voltage on GND, AGND, PDOGND,

REFGND Pins
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering Vapor Phase, 60 sec 215°C
ESD Rating, All Pins 2000 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

−0.3 V to +0.3 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

32-Lead LQFP 54 °C/W

ESD CAUTION

Rev. 0 | Page 6 of 28

ADM1168

D

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

VDDCAP

SDA

SCLA1A0

VCCP

PDOGN

NCNCNC

25

4

PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8

17

16

NC

09474-003

32

12

VX1
VX2
VX3
VX4
VP1
VP2
VP3

VH

NC = NO CONNECT.
DO NOT CONNECT TO THI S PIN.

8

PIN 1
INDICATO R

ADM1168

(Not to Scale)

9

AGND

REFGND

TOP VIEW

NC

REFOUT

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 to 4 VX1 to VX4

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.

5 to 7 VP1 to VP3

Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to these pins, the output of which connects to a supply fault detector.
These pins allow thresholds from 2.5 V to 6 V, from 1.25 V to 3 V, and from 0.573 V to 1.375 V.

8 VH

High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation
on a potential divider connected to this pin, the output of which connects to a supply fault detector.

This pin allows thresholds from 6 V to 14.4 V and from 2.5 V to 6 V.
9 AGND1 Ground Return for Input Attenuators.
10 REFGND1 Ground Return for On-Chip Reference Circuits.
11, 13 to 16 NC No Connect.
12 REFOUT

Reference Output, 2.048 V. Note that a capacitor must always be connected between this pin and REFGND.

A 10 μF capacitor is recommended for this purpose.
17 to 24 PDO8 to PDO1 Programmable Output Drivers.
25 PDOGND1 Ground Return for Output Drivers.
26 VCCP

Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin and

GND. A 10 μF capacitor is recommended for this purpose.
27 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
28 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
29 SCL SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
30 SDA SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
31 VDDCAP

Device Supply Voltage. Linearly regulated from the highest of the VPx and VH pins to a typical of 4.75 V.

A capacitor must be connected between this pin and GND. A 10 μF capacitor is recommended for

this purpose.
32 GND1 Supply Ground.

1

In a typical application, all ground pins are connected together.

Rev. 0 | Page 7 of 28

ADM1168

TYPICAL PERFORMANCE CHARACTERISTICS

(V)

VDDCAP

V

6

5

4

3

2

1

0

0654321

Figure 4. V

V

VP1

VDDCAP

(V)

vs. V

09474-050

VP1

180

160

140

120

100

(µA)

80

VP1

I

60

40

20

0

0123456

(V)

V

VP1

Figure 7. I

vs. V

VP1

(VP1 Not as Supply)

VP1

09474-053

6

5

4

(V)

3

VDDCAP

V

2

1

0

011412108642

(V)

V

VH

Figure 5. V

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

VP1

I

2.0

1.5

1.0

0.5

0

0123456

Figure 6. I

VP1

vs. V

vs. VVH

VDDCAP

(V)

V

VP1

(VP1 as Supply)

VP1

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

VH

I

2.0

1.5

1.0

0.5

350

300

250

200

(µA)

VH

150

I

100

50

0

011412108642

0

0654321

Figure 8. I

Figure 9. I

vs. VVH (VH as Supply)

VH

vs. VVH (VH Not as Supply)

VH

6

09474-051

09474-052

6

(V)

V

VH

V

(V)

VH

09474-054

09474-055

Rev. 0 | Page 8 of 28

ADM1168

14

12

(V)

10

PDO1

8

6

4

CHARGE-PUMPED V

2

0

0 15.012.510.07.55.02.5

Figure 10. Charge-Pumped V

I

(µA)

LOAD

(FET Drive Mode) vs. I

PDO1

LOAD

09474-056

4.5

4.0

3.5

3.0

2.5

(V)

2.0

PDO1

V

1.5

1.0

0.5

0

065040302010

Figure 12. V

VP1 = 5V

VP1 = 3V

(µA)

I

LOAD

(Weak Pull-Up to VPx) vs. I

PDO1

LOAD

0

09474-058

5.0

4.5

4.0

3.5

3.0

(V)

2.5

PDO1

V

2.0

1.5

1.0

0.5

0

0654321

Figure 11. V

VP1 = 3V

(mA)

I

LOAD

(Strong Pull-Up to VPx) vs. I

PDO1

VP1 = 5V

LOAD

09474-057

2.058

2.053

2.048

REFOUT (V)

2.043

2.038
–40 –20 0 20 40 60 10080

TEMPERATURE (°C)

Figure 13. REFOUT vs. Temperature

VP1 = 3.0V

VP1 = 4.75V

09474-061

Rev. 0 | Page 9 of 28