ANALOG DEVICES ADM1166 Service Manual

Super Sequencer with Margining Control

A

FEATURES

Complete supervisory and sequencing solution for up to

10 supplies 16 event deep black box nonvolatile fault recording 10 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C

<1.0% accuracy across all voltages and temperatures 5 selectable input attenuators allow supervision of supplies to

14.4 V on VH

6 V on VP1 to VP4 (VPx) 5 dual-function inputs, VX1 to VX5 (VXx)

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input 10 programmable driver outputs, PDO1 to PDO10 (PDOx)

Open-collector with external pull-up

Push/pull output, driven to VDDCAP or VPx

Open collector with weak pull-up to VDDCAP or VPx

Internally charge-pumped high drive for use with external

N-FET (PDO1 to PDO6 only)

Sequencing engine (SE) implements state machine control of

PDO outputs

State changes conditional on input events

Enables complex control of boards

Power-up and power-down sequence control

Fault event handling

Interrupt generation on warnings

Watchdog function can be integrated in SE

Program software control of sequencing through SMBus Complete voltage-margining solution for 6 voltage rails 6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage

adjustment via dc-to-dc converter trim/feedback node 12-bit ADC for readback of all supervised voltages 2 auxiliary (single-ended) ADC inputs Reference input (REFIN) has 2 input options

Driven directly from 2.048 V (±0.25%) REFOUT pin

More accurate external reference for improved ADC

performance

Device powered by the highest of VPx, VH for improved

redundancy User EEPROM: 256 bytes Industry-standard 2-wire bus interface (SMBus) Guaranteed PDO low with VH, VPx = 1.2 V Available in 40-lead, 6 mm × 6 mm LFCSP and

48-lead, 7 mm × 7 mm TQFP packages For more information about the ADM1166 register map,

refer to the

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AN-698 Application Note

and Nonvolatile Fault Recording

ADM1166

FUNCTIONAL BLOCK DIAGRAM

REFOUTREFINAUX2AUX1 REFGND

VX1 VX2 VX3 VX4 VX5

VP1 VP2 VP3 VP4

GND

ADM1166

12-BIT

MUX

SAR ADC

CLOSED-LOOP MARGINING SYSTEM

DUAL-

FUNCTION

INPUTS

(LOGIC INPUTS

OR

SFDs)

PROGRAMMABLE

RESET

GENERATORS

(SFDs)

VH

V

OUT

DAC

DAC2

V

OUT

DAC

DAC3

OUT

DAC

DAC1

SEQUENCING

V

OUT

DAC

DAC4

VREF

ENGINE

V

OUT

DAC

DAC5

Figure 1.

APPLICATIONS

Central office systems Servers/routers Multivoltage system line cards DSP/FPGA supply sequencing In-circuit testing of margined supplies

GENERAL DESCRIPTION

The ADM1166 Super Sequencer® is a configurable supervisory/ sequencing device that offers a single-chip solution for supply monitoring and sequencing in multiple-supply systems. In addition to these functions, the ADM1166 integrates a 12-bit ADC and six 8-bit voltage output DACs. These circuits can be used to implement a closed-loop margining system that enables supply adjustment by altering either the feedback node or reference of a dc-to-dc converter using the DAC outputs.

Supply margining can be performed with a minimum of external components. The margining loop can be used for in-circuit testing of a board during production (for example, to verify board functionality at −5% of nominal supplies), or it can be used dynamically to accurately control the output voltage of a dc-to-dc converter.

SDA SCL A1 A0

FAULT RECORDING

CONFIGURABLE

(HV CAPABLE OF

DRIVING GATES

OF N-FET)

CONFIGURABLE

(LV CAPABLE

OF DRIVING

LOGIC SIG NALS )

V

OUT

DAC

VCCP

DAC6

SMBus

INTERFACE

EEPROM

OUTPUT

DRIVERS

OUTPUT

DRIVERS

VDD

ARBITRATOR

GND

PDO1 PDO2 PDO3 PDO4 PDO5 PDO6

PDO7

PDO8

PDO9

PDO10 PDOGND VDDCAP

09332-001

ADM1166

REVISION HISTORY

12/10—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

ADM1166

The device also provides up to 10 programmable inputs for monitoring undervoltage faults, overvoltage faults, or out-ofwindow faults on up to 10 supplies. In addition, 10 programmable outputs can be used as logic enables. Six of these programmable outputs can also provide up to a 12 V output for driving the gate of an N-FET that can be placed in the path of a supply.

The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states. This design enables very flexible sequencing of the outputs, based on the condition of the inputs.

DETAILED BLOCK DIAGRAM

REFOUTREFIN

AUX1AUX2 REFGND

A block of nonvolatile EEPROM is available that can be used to store user-defined information and may also be used to hold a number of fault records that are written by the sequencing engine defined by the user when a particular fault or sequence occurs.

The device is controlled via configuration data that can be programmed into an EEPROM. The entire configuration can be programmed using an intuitive GUI-based software package provided by Analog Devices, Inc.

SDA SCL A1 A0

VX1

VX2 VX3 VX4

VX5

VP1

VP2 VP3 VP4

AGND

VDDCAP

VH

SELECTABLE ATTENUATOR

VDD

ARBITRATOR

ADM1166

GPI SIGNAL

CONDITIONING

GPI SIGNAL

CONDITIONING

REG 5.25V

CHARGE PUMP

12-BIT

SAR ADC

SFD

VREF

V

OUT

DAC

INTERFACE

CONTROLLER

FAULT RECORDING

SEQUENCING

ENGINE

SMBus

DEVICE

CONFIGURABLE

OUTPUT DRIVER

CONFIGURABLE

OUTPUT DRIVER

CONFIGURABLE

OUTPUT DRIVER

CONFIGURABLE

OUTPUT DRIVER

(HV)

(LV)

OSC

EEPROM

V

OUT

DAC

PDO1

PDO2 PDO3 PDO4 PDO5

PDO6

PDO7

PDO8 PDO9

PDO10

PDOGND

GND DAC2 DAC3 DAC4 DAC5

VCCP

DAC1

DAC6

09332-002

Figure 2. Detailed Block Diagram

Rev. 0 | Page 3 of 32

ADM1166

SPECIFICATIONS

VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY ARBITRATION

VH, VPx 3.0 V Minimum supply required on one of VPx, VH VPx 6.0 V Maximum VDDCAP = 5.1 V, typical VH 14.4 V VDDCAP = 4.75 V VDDCAP 2.7 4.75 5.4 V Regulated LDO output C

10 μF Minimum recommended decoupling capacitance

VDDCAP

POWER SUPPLY

Supply Current, IVH, I Additional Currents

All PDOx FET Drivers On 1 mA

Current Available from

VDDCAP DAC Supply Currents 2.2 mA Six DACs on with 100 μA maximum load on each ADC Supply Current 1 mA Running round-robin loop EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V

SUPPLY FAULT DETECTORS

VH Pin

Input Impedance 52 kΩ Input Attenuator Error ±0.05 % Midrange and high range Detection Ranges

High Range 6 14.4 V Midrange 2.5 6 V

VPx Pins

Input Impedance 52 kΩ Input Attenuator Error ±0.05 % Low range and midrange Detection Ranges

Midrange 2.5 6 V Low Range 1.25 3 V Ultralow Range 0.573 1.375 V No input attenuation error

VXx Pins

Input Impedance 1 MΩ Detection Range

Ultralow Range 0.573 1.375 V No input attenuation error

Absolute Accuracy ±1 %

Threshold Resolution 8 Bits Digital Glitch Filter 0 μs Minimum programmable filter length 100 μs Maximum programmable filter length

4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off

VPx

VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each, PDO7 to PDO10 off

2 mA

Maximum additional load that can be drawn from all PDO pull-ups to VDDCAP

VREF error + DAC nonlinearity + comparator offset error + input attenuation error

Rev. 0 | Page 4 of 32

ADM1166

Parameter Min Typ Max Unit Test Conditions/Comments

ANALOG-TO-DIGITAL CONVERTER

Signal Range 0 V

Input Reference Voltage on

REFIN Pin, V

REFIN

2.048 V

Resolution 12 Bits INL ±2.5 LSB Endpoint corrected, V Gain Error ±0.05 % V Conversion Time 0.44 ms One conversion on one channel 84 ms All 12 channels selected, 16× averaging enabled Offset Error ±2 LSB V Input Noise 0.25 LSB rms Direct input (no attenuator) AUX1, AUX2 Input Impedance 1 MΩ

BUFFERED VOLTAGE OUTPUT DACs

Resolution 8 Bits Code 0x7F Output Voltage

Range 1 0.592 0.6 0.603 V Range 2 0.796 0.8 0.803 V Range 3 0.996 1 1.003 V

Range 4 1.246 1.25 1.253 V Output Voltage Range 601.25 mV Same range, independent of center point LSB Step Size 2.36 mV INL ±0.75 LSB Endpoint corrected DNL ±0.4 LSB Gain Error 1 % Maximum Load Current (Source) 100 μA Maximum Load Current (Sink) 100 μA Maximum Load Capacitance 50 pF Settling Time to 50 pF Load 2 μs Load Regulation 2.5 mV Per mA PSRR 60 dB DC

40 dB 100 mV step in 20 ns with 50 pF load REFERENCE OUTPUT

Reference Output Voltage 2.043 2.048 2.053 V No load Load Regulation −0.25 mV Sourcing current, I

0.25 mV Sinking current, I Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability PSRR 60 dB DC

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge-Pump) Mode

(PDO1 to PDO6) Output Impedance 500 kΩ V

11 12.5 14 V IOH = 0 μA

OH

V

10.5 12 13.5 V IOH = 1 μA

OH

2

V

8 10 13.5 V IOH = 7 μA

OH

I

20 μA 2 V < VOH < 7 V

OUTAVG

REFIN

V

The ADC can convert signals presented to the VH, VPx, and VXx pins; VPx and VH input signals are attenuated depending on the selected range; a signal at the pin corresponding to the selected range is from 0.573 V to

1.375 V at the ADC input

= 2.048 V

REFIN

= 2.048 V

REFIN

= 2.048 V

REFIN

Six DACs are individually selectable for centering on one of four output voltage ranges

= −100 μA

DACxMAX

= 100 μA

DACxMAX

Rev. 0 | Page 5 of 32

ADM1166

Parameter Min Typ Max Unit Test Conditions/Comments

Standard (Digital Output) Mode

(PDO1 to PDO10) VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA

4.5 V VPU to VPx = 6.0 V, IOH = 0 mA V VOL 0 0.50 V IOL = 20 mA

2

I

20 mA Maximum sink current per PDOx pin

OL

2

I

60 mA Maximum total sink for all PDOx pins

SINK

R

16 20 29 kΩ Internal pull-up

PULL-UP

I

(VPx)2 2 mA

SOURCE

Three-State Output Leakage

Current

Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock

DIGITAL INPUTS (VXx, A0, A1)

Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V Input High Current, IIH −1 μA VIN = 5.5 V Input Low Current, IIL 1 μA VIN = 0 V Input Capacitance 5 pF Programmable Pull-Down Current,

PULL-DOWN

I

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH 2.0 V Input Low Voltage, VIL 0.8 V Output Low Voltage, V

2

0.4 V I

OL

SERIAL BUS TIMING3

Clock Frequency, f Bus Free Time, t Start Setup Time, t Stop Setup Time, t Start Hold Time, t SCL Low Time, t SCL High Time, t

400 kHz

SCLK

1.3 μs

BUF

0.6 μs

SU;STA

0.6 μs

SU;STO

0.6 μs

HD;STA

1.3 μs

LOW

0.6 μs

HIGH

SCL, SDA Rise Time, tR 300 ns SCL, SDA Fall Time, tF 300 ns Data Setup Time, t Data Hold Time, t

100 ns

SU;DAT

250 ns

HD;DAT

Input Low Current, IIL 1 μA VIN = 0 V

SEQUENCING ENGINE TIMING

State Change Time 10 μs

1

At least one of the VH and VPx pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.

2

Specification is not production tested but is supported by characterization data at initial product release.

3

Guaranteed by design.

− 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA

PU

Current load on any VPx pull-ups, that is, total source current available through any number of PDO pull-up switches configured onto any one VPx pin

10 μA V

= 14.4 V

PDO

20 μA VDDCAP = 4.75 V, T

= −3.0 mA

OUT

= 25°C, if known logic state is required

A

Rev. 0 | Page 6 of 32

ADM1166

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage on VH Pin 16 V Voltage on VPx Pins 7 V Voltage on VXx Pins −0.3 V to +6.5 V Voltage on AUX1, AUX2 Pins −0.3 V to +5 V Voltage on A0, A1 Pins −0.3 V to +7 V Voltage on REFIN, REFOUT Pins 5 V Voltage on VDDCAP, VCCP Pins 6.5 V Voltage on DACx Pins 6.5 V Voltage on PDOx Pins 16 V Voltage on SDA, SCL Pins 7 V Voltage on GND, AGND, PDOGND, REFGND Pins −0.3 V to +0.3 V Input Current at Any Pin ±5 mA Package Input Current ±20 mA Maximum Junction Temperature (TJ max) 150°C Storage Temperature Range −65°C to +150°C Lead Temperature

Soldering Vapor Phase, 60 sec 215°C

ESD Rating, All Pins 2000 V

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

40-Lead LFCSP 26.5 °C/W 48-Lead TQFP 50 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Rev. 0 | Page 7 of 32

ADM1166

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND

VDDCAP

AUX1

AUX2

SDA

SCLA1A0

VCCP

PDOGND

32

31

33

34

35

36

37

38

39

40

1

VX1 VX2

2

VX3

3

VX4

4 5

VX5

6

VP1

7

VP2 VP3

8 9

VP4

10

VH

NOTE

1. EXPOSED PAD SHOULD BE SOLDERED TO THE BO ARD FOR IMPRO V E D MECHANICAL STABILITY.

ADM1166

TOP VIEW

(Not to S cale)

11

12

13

15

14

DAC1

AGND

REFIN

REFOUT

REFGND

17

16

DAC2

DAC3

30 29 28 27 26 25 24 23 22 21

18

19

20

DAC4

DAC5

DAC6

PDO1 PDO2 PDO3 PDO4 PDO5 PDO6 PDO7 PDO8 PDO9 PDO10

09332-003

NC

X1 X2 X3 X4 X5 P1 P2 P3 P4

VH

NC

NC = NO CONNECT

Figure 3. 40-Lead LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

40-Lead LFCSP

48-Lead TQFP Mnemonic

1, 12, 13, 24,

NC No Connect.

Description

25, 36, 37, 48

1 to 5 2 to 6 VX1 to VX5 (VXx)

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to

1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.

6 to 9 7 to 10 VP1 to VP4 (VPx)

Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input attenuation on a potential divider connected to these pins, the output of which connects to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from

1.25 V to 3.00 V, and from 0.573 V to 1.375 V.

10 11 VH

High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input attenuation on a potential divider connected to this pin, the output of which connects to a supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.

1

11 14 AGND 12 15 REFGND 13 16 REFIN

Ground Return for Input Attenuators.

1

Ground Return for On-Chip Reference Circuits.

Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage. The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.

14 17 REFOUT

Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be

connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose. 15 to 20 18 to 23 DAC1 to DAC6 21 to 30 26 to 35 PDO10 to PDO1 31 38 PDOGND

1

Ground Return for Driver Outputs.

32 39 VCCP

Voltage Output DACs. These pins default to high impedance at power-up.

Programmable Driver Outputs.

Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between

this pin and GND. A 10 μF capacitor is recommended for this purpose. 33 40 A0 34 41 A1 35 42 SCL 36 43 SDA

Logic Input. This pin sets the seventh bit of the SMBus interface address.

Logic Input. This pin sets the sixth bit of the SMBus interface address.

SMBus Clock Pin. Bidirectional, open-drain pin that requires external resistive pull-up.

SMBus Data Pin. Bidirectional, open-drain pin that requires external resistive pull-up. 37, 38 44, 45 AUX2, AUX1 Auxiliary, Single-Ended ADC Inputs.

NC48GND47VDDCAP46AUX145AUX244SDA43SCL42A141A040VCCP39PDOGND38NC

1

PIN 1

2

INDICATOR 3 4 5 6 7 8 9

10 11 12

13

14

NC

AGND

15

REFGND

ADM1166

TOP VIEW

(Not to S cal e)

16

17

REFIN

REFOUT

DAC118DAC219DAC320DAC421DAC522DAC6

Figure 4. 48-Lead TQFP Pin Configuration

23NC24

37

NC

36

PDO1

35

PDO2

34

PDO3

33

PDO4

32

PDO5

31

PDO6

30

PDO7

29

PDO8

28

PDO9

27 26

PDO10

25

NC

09332-004

Rev. 0 | Page 8 of 32

ADM1166

Pin No.

40-Lead LFCSP

39 46 VDDCAP

40 47 GND1 Supply Ground. Not applicable EPAD

1

In a typical application, all ground pins are connected together.

48-Lead TQFP Mnemonic Description

Device Supply Voltage. Linearly regulated from the highest of the VPx and VH pins to a typical of 4.75 V. Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor is recommended for this purpose.

Exposed Pad. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.

Rev. 0 | Page 9 of 32

ADM1166

TYPICAL PERFORMANCE CHARACTERISTICS

(V)

VDDCAP

V

6

5

4

3

2

1

0

0654321

Figure 5. V

V

VP1

VDDCAP

(V)

vs. V

09332-050

VP1

180

160

140

120

100

(µA)

80

VP1

I

60

40

20

0

0123456

(V)

V

VP1

Figure 8. I

vs. V

VP1

(VP1 Not as Supply)

VP1

09332-053

6

5

4

(V)

3

VDDCAP

V

2

1

0

011412108642

(V)

V

VH

Figure 6. V

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

VP1

I

2.0

1.5

1.0

0.5

0

0123456

Figure 7. I

vs. V

VP1

vs. VVH

VDDCAP

(V)

V

VP1

(VP1 as Supply)

VP1

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

VH

I

2.0

1.5

1.0

0.5

0

6

09332-051

011412108642

Figure 9. IVH vs. VVH (VH as Supply)

350

300

250

200

(µA)

VH

150

I

100

50

0

0654321

09332-052

Figure 10. IVH vs. VVH (VH Not as Supply)

6

(V)

V

VH

V

(V)

VH

09332-054

09332-055

Rev. 0 | Page 10 of 32

ANALOG DEVICES ADM1166 Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

DETAILED BLOCK DIAGRAM

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS