ANALOG DEVICES ADM1075 Service Manual

−48 V Hot Swap Controller and Digital Power Monitor with PMBus Interface

Data Sheet

FEATURES

Constant power foldback for FET SOA protection Precision (<1.0%) current and voltage measurement Controls inrush and faults for negative supply voltages Suitable for wide input range due to internal shunt regulator 25 mV/50 mV full-scale sense voltage Fine tune current limit to allow use of standard sense resistor Soft start inrush current limit profiling 1% accurate UVH and OV pins, 1.5% accurate UVL pin PMBus interface for control, telemetry, and fault recording 28-lead TSSOP

−40°C to 105°C junction temperature (T

APPLICATIONS

Telecommunication and data communication equipment Central office switching

−48 V distributed power systems Negative power supply control High availability servers

) operating range

J

ADM1075

PRODUCT HIGHLIGHTS

1. Constant Power Foldback.

Maximum FET power set by a PLIM resistor divider. This eases complexity when designing to maintain FET SOA.

2. Adjustable Current Limit.

The current limit is adjustable via the ISET pin allowing for the use of a standard value sense resistor.

3. 12-Bit ADC.

Accurate voltage, current, and power measurements. Also enables calculation of energy consumption over time.

4. PMBus Interface.

PMBus fast mode compliant interface used to read back status and data registers and set warning and fault limits.

5. Fault Recording.

Latched status registers provide useful debugging information to help trace faults in high reliability systems.

6. Built-In Soft Start.

Soft start capacitor controls inrush current profile with di/dt control.

–48V RTN (0V)

VEE

R

UVH

UVL

OV

ADC_V

VCAP

ISET

DROP

VIN

VCC AND REFERENCE GENERATOR

UNDERVOLTAG E

AND

OVERVOLTAGE

DETECTOR

SPLYGD

TIMER

FUNCTIONAL BLOCK DIAGRAM

SHDN

RESTART

POWER

ACCUMULATOR

POWER

MULTIPLIER

12-BIT ADC

FET POWER

FOLDBACK

CONTROL

FAULT TIMER

GATE CO NTROL

CURRENT LIMIT

SS

VEE_G

DIGITAL

AND

PMBUS

VEE

LATCH GPO1/ALERT1/CONV

GPO2/ALERT2 SDAO

SDAI SCL

ADR

ADC_AUX

PWRGD

DRAIN

PLIM

VEE

GATE

SENSE+

SENSE–

C

LOAD

N-FET

R

SENSE

DC-TO-DC

CONVERTER

ADuM1250

12V

5V

3.3V

2.8V

...etc.

GND

SDA_ISO

SCL_ISO

–48V

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1.

09312-001

ADM1075 Data Sheet

REVISION HISTORY

10/11—Revision 0: Initial Version

Read EIN_EXT Register ............................................................49

Read VAUX Register...................................................................50

VAUX OV Warn Limit Register................................................50

VAUX UV Warn Limit Register................................................50

VAUX Status Register.................................................................50

Outline Dimensions........................................................................51

Ordering Guide...........................................................................51

Rev. 0 | Page 3 of 52

ADM1075 Data Sheet

GENERAL DESCRIPTION

The ADM1075 is a full feature, negative voltage, hot swap controller with constant power foldback and high accuracy digital current and voltage measurement that allows boards to be safely inserted and removed from a live −48 V backplane. The part provides precise and robust current limiting and protection against both transient and nontransient short circuits and overvoltage and undervoltage conditions. The ADM1075 typically operates from a negative voltage of −35 V to −80 V and, due to shunt regulation, has excellent voltage transient immunity. The operating range of the part is flexible due to the shunt regulator, and the part can be powered directly by a 10 V rail to save shunt power dissipation (see the Powering the ADM1075 section for more details).

A full-scale current limit of 25 mV or 50 mV can be selected by choosing the appropriate model. The maximum current limit is set by the combination of the sense resistor, R

, and the input

SENSE

voltage on the ISET pin, using external resistors. This allows fine tuning of the trip voltage so that standard sense resistors can be used. Inrush current is limited to this programmable value by controlling the gate drive of an external N-channel FET. A builtin soft start function allows control of the inrush current profile by an external capacitor on the soft start (SS) pin.

An external capacitor on the TIMER pin determines the maximum allowed on-time for when the system is in current limit. This is based on the safe operating area (SOA) limits of the MOSFET. A constant power foldback scheme is used to control the power dissipation in the MOSFET during power-up and fault conditions. The ADM1075 regulates the current dynamically to ensure that the power in the MOSFET is within SOA limits as V

changes. After the timer has expired, the device

DS

shuts down the MOSFET. The level of this power, along with the TIMER regulation time, can be set to ensure that the MOSFET remains within the SOA limits.

The ADM1075 employs a limited consecutive retry scheme when the

LATCH

pin is tied to the

SHDN

pin. In this mode, if the load current reaches the limit, the FET gate is pulled low after the timer expires and retries after a cooling period for seven attempts only. If the fault remains, the device latches off, and the MOSFET is disabled until a manual restart is initiated. Alternatively, the can be set to retry only once by isolating the

ADM1075

LATCH

pin from the

SHDN

pin. The part can also be configured to retry an infinite number of times with a 10 second interval between restarts by connecting the GPO2 pin to the

RESTART

pin.

The ADM1075 has separate UVx and OV pins for undervoltage and overvoltage detection. The FET is turned off if a nontransient voltage less than the undervoltage threshold (typically −35 V) is detected on the UVx pins or if greater than the overvoltage threshold (typically −80 V) is detected on the OV pin. The operating voltage range of the ADM1075 is programmable via resistor networks on the UVx and OV pins. The hysteresis levels on the overvoltage detectors can also be altered by selecting the appropriate resistors. There are two separate UVx pins to allow accurate programming of hysteresis.

In the case of a short circuit, the ADM1075 has a fast response circuit to detect and respond adequately to this event. If the sense voltage exceeds 1.5 times the normal current limit, a high current (750 mA minimum) gate pull-down switch is activated to shut down the MOSFET as quickly as possible. There is a default internal glitch filter of 900 ns. If a longer filter time or different severe overcurrent limit is required, these parameters can be adjusted via the PMBus™ interface.

The ADM1075 also includes a 12-bit ADC to provide digital measurement of the voltage and load current. The current is measured at the output of the internal current sense amplifier and the voltage from the ADC_V input. This data can be read across the PMBus interface.

The PMBus interface allows a controller to read current, voltage, and power measurements from the ADC. Measurements can be initiated by a PMBus command or can be set up to run continuously. The user can read the latest conversion data whenever it is required. A power accumulator is also provided to report total power consumed in a user specified period (total energy). Up to four unique I

2

C addresses can be created, depending on

the configuration of the ADR pin.

The GPO1/

ALERT1

/CONV and GPO2/

ALERT2

outputs can be used as a flag to warn a microcontroller or FPGA of one or more fault/warning conditions becoming active. The fault type and level is programmed across the PMBus, and the user can select which faults/warnings activate the alert.

Other functions include

PWRGD

•

output, which can be used to enable a power module (the DRAIN and GATE pins are monitored to determine when the load capacitance is fully charged) SHDN

•

input to manually disable the GATE drive

RESTART

input to remotely initiate a 10 second shutdown

Rev. 0 | Page 4 of 52

Data Sheet ADM1075

SPECIFICATIONS

VEE = −48 V, V

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SYSTEM SUPPLY

Voltage Transient Immunity −200 V Typical Operating Voltage −80 −35 V Determined by external component, R

SHUNT REGULATOR

Operating Supply Voltage Range, VIN 11.5 12.3 13 V Shunt regulation voltage, IIN = 5.5 mA to 30 mA,

Quiescent Supply Current 5.5 mA VIN = 13 V Undervoltage Lockout, V Undervoltage Lockout Hysteresis 600 mV Power Directly Without Shunt 9.2 11.5 V

UV PINS—UNDERVOLTAGE DETECTION

Undervoltage Rising Threshold, V Undervoltage Falling Threshold, V Total Undervoltage Hysteresis 100 mV When UVL and UVH are tied together Undervoltage Fault Filter 3.5 7.5 µs UV Propagation Delay 5 8 µs UV low to GATE pull-down active UVL/UVH Input Current 1 50 nA

OV PIN—OVERVOLTAGE DETECTION

Overvoltage Rising Threshold, V Overvoltage Hysteresis Current 4.3 5 5.7 µA Overvoltage Fault Filter 1.75 3.75 µs OV Propagation Delay 2 4 µs OV high to GATE pull-down active OV Input Current 1 50 nA

GATE PIN

Gate Voltage High 11 12 13 V I Gate Voltage Low 10 100 mV I Pull-Up Current −50 −30 µA V Pull-Down Current (Regulation) 100 µA V Pull-Down Current (UV/OV/OC) 5 10 mA V Pull-Down Current (Severe OC) 750 1500 2000 mA V Pull-Down On-Time (Severe OC) 8 16 µs Gate Hold-Off Resistance 20 Ω 0 V ≤ VIN ≤ (V

SENSE+, SENSE−

SENSE+, SENSE− Input Current, I

SENSE+, SENSE− Input Imbalance, I

VCAP

Internally Regulated Voltage, V

ISET

ISET Reference Select Threshold, V ISET Internal Reference, V Gain of Current Sense Amplifier, AV ISET Input Current, I

ADM1075-1 ONLY (GAIN = 50)

Hot Swap Sense Voltage

Hot Swap Sense Voltage Current Limit,

V

SENSECL

24.5 25 25.5 mV V

19.5 20 20.5 mV V

14.5 15 15.5 mV V

SENSE

= (V

SENSE+

− V

) = 0 mV, shunt regulation current = 10 mA, TJ = −40°C to +105°C, unless otherwise noted.

SENSE−

maximum I

dependent on TA, θJA (see the Powering the

IN

SHUNT

ADM1075 section)

9.2 V

UVLO_RISING

0.99 1.0 1.01 V

UVH

0.887 0.9 0.913 V

UVL

0.99 1.0 1.01 V

OVR

= −1.0 µA

GATE

= 100 µA

GATE

= 0 V to 8 V; VSS = 2 V

GATE

≥ 2 V

GATE

≥ 2 V

GATE

≥ 6 V

GATE

= 2 V)

GATE

100 A V

SENSEx

1 A I

∆SENSEx

2.66 2.7 2.74 V 0 ≤ I

VCAP

1.35 1.5 1.65 V If V

ISETRSTH

1 V Accuracies included in total sense voltage accuracies

CLREF

50/25 V/V Accuracies included in total sense voltage accuracies

CSAMP

100 nA V

ISET

19.4 20 20.6 mV V

≤ 65 mV for ADM1075-1, per individual pin;

SENSE

≤ 130 mV for ADM1075-2, per individual pin

V

SENSE

= I

− I

∆SENSEx

VCAP

> V

ISET

≤ VCAP

ISET

> 1.65 V; V

ISET

SENSE+

≤ 100 A; C

ISETRSTH

SENSE−

= 1 F

VCAP

an internal 1 V reference (V

GATE

= 3 V; I

= 0 A; VSS ≥ 2 V; V

GATE

CLREF

) is used

= 0 V

PLIM

= 1.25 V; V

ISET

= 1.0 V; V

ISET

= 0.75 V; V

ISET

GATE

= 3 V; I

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

PLIM

= 0 V

Rev. 0 | Page 5 of 52

ADM1075 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments

Constant Power Active 9.4 10 11.0 mV V

4.5 5 5.7 mV V

1.4 2 2.6 mV V Circuit Breaker Offset, V

0.6 0.75 0.95 mV Circuit breaker voltage, VCB = V

CBOS

Severe Overcurrent Activates high current gate pull-down

Voltage Threshold, V

23 25 27 mV V

SENSEOC

28 30 32 mV V 38 40 42 mV V 43 45 47 mV V

Response Time

Glitch Filter Duration 50 200 ns V

500 900 ns V

6.2 10.7 µs V

44 57 µs V

Total Response Time 180 300 ns V

610 950 ns V

7 13 µs V

45 60 µs V

ADM1075-2 ONLY (GAIN = 25)

Hot Swap Sense Voltage

Hot Swap Sense Voltage Current Limit,

V

SENSECL

39.2 40 40.8 mV V

49.2 50 50.8 mV V

39.2 40 40.8 mV V

29.2 30 30.8 mV V Constant Power Active 19 20 21.9 mV V

9.2 10 11.2 mV V 3 4 5.0 mV V

Circuit Breaker Offset, V

1.1 1.5 1.9 mV Circuit breaker voltage, VCB = V

CBOS

Severe Overcurrent Activates high current gate pull-down

Voltage Threshold, V

46 50 54 mV V

SENSEOC1

56 60 64 mV V 76 80 84 mV V

86 90 94 mV V

Response Time

Glitch Filter Duration 50 200 ns V

400 900 ns V

6.2 10.7 µs V

44 57 µs V

> 1.65 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; default at power-up

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; V

ISET

GATE

= 3 V; I = 3 V; I = 3 V; I

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

− V

SENSECL

step from 18 mV to 52 mV;

SENSE

CBOS

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

default at power-up

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

default at power-up

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 18 mV to 52 mV;

SENSE

optional select through PMBus

> 1.65 V; V

ISET

= 1.25 V; V

ISET

= 1.0 V; V

ISET

= 0.75 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; V

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; default at power-up

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; optional select through PMBus

ISET

> 1.65 V; VSS ≥ 2 V; V

ISET

GATE

= 3 V; I

= 3 V; I = 3 V; I = 3 V; I = 3 V; I

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

= 0 A; VSS ≥ 2 V; V

GATE

− V

SENSECL

step from 36 mV to 104 mV;

SENSE

CBOS

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

default at power-up

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

PLIM

= 0.2 V = 0.4 V = 1.2 V

= 0 V

= 0 V = 0.2 V = 0.4 V = 1.2 V

Rev. 0 | Page 6 of 52

Data Sheet ADM1075

Parameter Min Typ Max Unit Test Conditions/Comments

Total Response Time 180 300 ns V

610 950 ns V

7 13 µs V

45 60 µs V

SOFT START

SS Pull-Up Current, ISS −11.5 −10 −8.5 µA VSS = 0V Default V

Limit 0.6 1.25 1.9 mV When V

SENSECL

1.2 2.5 3.8 mV When V

SS Pull-Down Current 100 µA VSS = 1 V

TIMER

Timer Pull-Up Current (POR), I Timer Pull-Up Current (OC Fault), I Timer Pull-Down Current (Retry), I

−4 −3 −2 µA Initial power-on reset; V

TIMERUPPOR

−63 −60 −57 µA Overcurrent fault; 0.05 V ≤ V

TIMERUPFLT

1.7 2 2.3 µA After a fault when GATE is off; V

TIMERDNRT

Timer Retry/OC Fault Current Ratio 3.33 % Defines the limits of the autoretry duty cycle Timer Pull-Down Current (Hold), I Timer High Threshold, V Timer Low Threshold, V

0.98 1.0 1.02 V

TIMERH

0.03 0.05 0.07 V

TIMERL

TIMERDNHOLD

100 µA Holds TIMER at 0 V when inactive; V

PLIM

PLIM Active Threshold 0.08 0.09 0.1 V V Input Current, I Minimum Current Clamp, V

100 nA V

PLIM

75 100 125 mV V

ICLAMP

DRAIN

DRAIN Voltage at Which

PWRGD

Asserts

1.9 2 2.1 V I

ADC_AUX/ADC_V

Input Current 100 nA 0 V ≤ V

SHDN

PIN Input High Voltage, VIH 1.1 V Input Low Voltage, VIL 0.8 V Glitch Filter 1 µs Internal Pull-Up Current 8 µA Pull-up to VIN

RESTART

PIN Input High Voltage, VIH 1.1 V Input Low Voltage, VIL 0.8 V Glitch Filter 1 µs Internal Pull-Up Current 8 µA Pull-up to VIN

SPLYGD

Output Low Voltage, V

0.4 V I

OL_LATCH

1.5 V I Leakage Current 100 nA

1 µA

LATCH

Output Low Voltage, V

0.4 V I

OL_LATCH

1.5 V I Leakage Current 100 nA 1 µA

ALERT1

GPO1/

/CONV PIN

Output Low Voltage, V

0.4 V I

OL_GPO1

1.5 V I

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

default at power-up

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

> 1.65 V; VSS ≥ 2 V; V

ISET

step from 36 mV to 104 mV;

SENSE

optional select through PMBus

reaches this level, ISS is enabled, ramping;

SENSE

= 0 V; ADM1075-1 only (gain = 50)

V

SS

reaches this level, ISS is enabled, ramping;

SENSE

= 0 V; ADM1075-2 only (gain = 25)

V

SS

= 0.5 V

TIMER

> 1.65 V

ISET

≤ 1 V

PLIM

= 1.2 V; V

PLIM

SENSE_IMIN

= (V

÷ gain) = minimum

ICLAMP

allowed current control

≤ 50 µA

DRAIN

≤ 1.5 V

ADC

= 1 mA

SPLYGD

= 5 mA

SPLYGD

≤ 2 V; ≤ 14 V;

= 1 mA = 5 mA

≤ 2 V; ≤ 14 V;

SPLYGD

LATCH

pin disabled

V V

LATCH

V V

GPO

SPLYGD

LATCH

= 1 mA = 5 mA

≤ 1 V

TIMER

= 0.5 V

TIMER

Rev. 0 | Page 7 of 52

ADM1075 Data Sheet

Parameter Min Typ Max Unit Test Conditions/Comments

Leakage Current 100 nA V 1 µA V Input High Voltage, VIH 1.1 V Configured as CONV pin Input Low Voltage, VIL 0.8 V Configured as CONV pin Glitch Filter 1 µs Configured as CONV pin

ALERT2

GPO2/

Output Low Voltage, V

0.4 V I

OL_GPO2

1.5 V I Leakage Current 100 nA V 1 µA V

PWRGD

Output Low Voltage, V

0.4 V I

OL_PWRGD

1.5 V I VIN That Guarantees Valid Output 1 V I Leakage Current 100 nA

1 µA

CURRENT AND VOLTAGE MONITORING

Current Sense Absolute Error (ADM1075-1) 25 mV input range; 128 sample averaging (unless

−0.01 ±0.7 % V

0.05 ±0.85 % V

0.07 ±0.85 % V

0.04 ±2.8 % V ±1.0 % V ±1.4 % V ±2.7 % V ±5.9 % V Current Sense Absolute Error (ADM1075-2) 50 mV input range; 128 sample averaging (unless

−0.03 ±0.65 % V

−0.03 ±0.7 % V

−0.04 ±1.35 % V ±0.75 % V ±0.9 % V ±1.7 % V ±3.0 % V ADC_V/ADC_AUX Absolute Accuracy −0.8 +0.8 % 0.6 V ≤ V ADC Conversion Time 1 sample of voltage and current; from command

191 219 µs V 263 301 µs V

2.830 3.243 ms V

3.987 4.568 ms V 128 samples of voltage and current averaged; from

22.54 25.83 ms V

31.79 36.43 ms V Power Multiplication Time 14 µs

≤ 2 V; GPO disabled

GPO

= 14 V; GPO disabled

GPO

= 1 mA

GPO

= 5 mA

GPO

≤ 2 V; GPO disabled

GPO

= 14 V; GPO disabled

GPO

= 1 mA

PWRGD

= 5 mA

PWRGD

= 100 A; V

SINK

≤ 2 V;

V

PWRGD

= 14 V;

V

PWRGD

OL_PWRGD

PWRGD

= 0.4 V

active

otherwise noted)

= 25 mV

SENSE

= 20 mV

SENSE

= 20 mV; 16 sample averaging

SENSE

= 20 mV; 1 sample averaging

SENSE

= 15 mV

SENSE

= 10 mV

SENSE

= 5 mV

SENSE

= 2.5 mV

SENSE

otherwise noted)

= 50 mV

SENSE

= 40 mV

SENSE

= 40 mV; 16 sample averaging

SENSE

= 40 mV; 1 sample averaging

SENSE

= 30 mV

SENSE

= 20 mV

SENSE

= 10 mV

SENSE

= 5 mV

SENSE

≤ 1.5 V

ADC

received to valid data in register

disabled

AUX

enabled

AUX

16 samples of voltage and current averaged; from command received to valid data in register

disabled

AUX

enabled

AUX

command received to valid data in register

disabled (default on power-up)

AUX

enabled

AUX

Rev. 0 | Page 8 of 52

Data Sheet ADM1075

Parameter Min Typ Max Unit Test Conditions/Comments

ADR PIN See Table 6

Address Set to 00 0 0.8 V Connect to VEE Input Current for Address 00 −40 −22 A V Address Set to 01 135 150 165 kΩ Resistor to VEE Address Set to 10 −1 +1 A No connect state; maximum leakage current allowed Address Set to 11 2.1 V Connect to VCAP Input Current for Address 11 3 10 A V

SERIAL BUS DIGITAL INPUTS (SDAI/SDAO, SCL)

Input High Voltage, VIH 1.1 V Input Low Voltage, VIL 0.8 V Output Low Voltage, VOL 0.4 V IOL = 4 mA, SDAO only Input Leakage, I

−10 +10 A

LEAK-PIN

−5 +5 A Device is not powered Nominal Bus Voltage, VDD 2.7 5.5 V 3 V to 5 V ±10% Capacitive Load per Bus Segment, C Capacitance for SDAI, SDAO, or SCL Pin, C

400 pF

BUS

5 pF

Input Glitch Filter, tSP 0 50 ns

SERIAL BUS TIMING

Table 2.

Parameter Description Min Typ Max Unit Test Conditions/Comments

f

Clock frequency 400 kHz

SCLK

t

Bus free time 1.3 µs

BUF

t

Start hold time 0.6 µs

HD;STA

t

Start setup time 0.6 µs

SU;STA

t

Stop setup time 0.6 µs

SU;STO

t

SDA1 hold time 300 900 ns

HD;DAT

t

SDA1 setup time 100 ns

SU;DAT

t

SCL low time 1.3 µs

LOW

t

SCL high time 0.6 µs

HIGH

2

t

SCL, SDA1 rise time 20 300 ns

R

tF SCL, SDA1 fall time 20 300 ns tOF SCL, SDA1 output fall time 20 + 0.1 × C

1

SDAI and SDAO tied together.

2

tR = (V

– 0.15) to (V

IL(MAX)

+ 0.15) and tF = 0.9 VDD to (V

IH3V3

– 0.15); where V

IL(MAX)

t

SCL

SDA

LOW

V

IH

V

IL

t

HD;STA

V

IH

V

IL

t

BUF

HD;DAT

t

R

250 ns

BUS

= 2.1 V, and VDD = 3.3 V.

IH3V3

t

F

t

HIGH

SU;STA

t

SU;DAT

Figure 2. Serial Bus Timing Diagram

= 0 V to 0.8 V

ADR

= 2.0 V to VCAP; must not exceed the maximum

ADR

allowable current draw from VCAP

t

SU;STO

PSSP

09312-002

Rev. 0 | Page 9 of 52

ADM1075 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VIN Pin to VEE −0.3 V to +14 V UVL Pin to VEE −0.3 V to +4 V UVH Pin to VEE −0.3 V to +4 V OV Pin to VEE −0.3 V to +4 V ADC_V Pin to VEE −0.3 V to +4 V ADC_AUX Pin to VEE −0.3 V to +4 V SS Pin to VEE −0.3 V to (VCAP + 0.3 V) TIMER Pin to VEE −0.3 V to (VCAP + 0.3 V) VCAP Pin to VEE −0.3 V to +4 V ISET Pin to VEE −0.3 V to +4 V SPLYGD Pin to VEE LATCH Pin to VEE RESTART Pin to VEE SHDN Pin to VEE PWRGD Pin to VEE DRAIN Pin to VEE −0.3 V to (VCAP + 0.3 V) SCL Pin to VEE −0.3 V to +6.5 V SDAI Pin to VEE −0.3 V to +6.5 V SDAO Pin to VEE −0.3 V to +6.5 V ADR Pin to VEE −0.3 V to (VCAP + 0.3 V) GPO1/

ALERT1

GPO2/

ALERT2

PLIM Pin to VEE −0.3 V to +4 V GATE Pin to VEE −0.3 V to +18 V SENSE+ Pin to VEE −0.3 V to +4 V SENSE− Pin to VEE −0.3 V to +0.3 V VEE to VEE_G −0.3 V to +0.3 V Continuous Current into Any Pin ±10 mA Storage Temperature Range −65°C to +125°C Operating Junction Temperature

Range Lead Temperature, Soldering (10 sec) 300°C Junction Temperature 150°C

/CONV Pin to VEE

Pin to VEE

−0.3 V to +18 V

−40°C to +105°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages.

Table 4. Thermal Resistance

Package Type θ

28-Lead TSSOP 68 20 °C/W

1

Measured on JEDEC 4-layer board in still air.

1

θJC Unit

JA

ESD CAUTION

Rev. 0 | Page 10 of 52

Data Sheet ADM1075

A

PIN CONFIGURATION AND FUNCTION DESCRIPTION

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1 DRAIN

Connect to the drain pin of the FET through a resistor. The current in this resistor is used to determine the VDS of the MOSFET. This is used for

2 VIN

Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via a shunt resistor. A 1 µF capacitor to VEE is recommended on the VIN pin.

3 UVH

Undervoltage Rising Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is under the UVH limit.

4 UVL

Undervoltage Falling Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is under the UVL limit.

5 OV

Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an internal comparator to detect if the supply is above the OV limit.

6 PLIM

The voltage on this pin is proportional to the V current limit automatically adjusts to maintain constant power across the FET.

7 VCAP

A capacitor with a value of 1 µF or greater should be placed on this pin to maintain good accuracy. This is an internal regulated supply. This pin can be used as a reference to program the ISET pin voltage.

8 ADC_V

This pin is used to read back the input voltage using the internal ADC. It can be connected to the OV string or a separate divider.

9 ISET

This pin allows the current limit threshold to be programmed. The default limit is set when this pin is connected directly to VCAP. Alternatively, using a resistor divider from VCAP, the current limit can be adjusted to achieve a user defined sense voltage. An external reference can also be used.

10 SS

A capacitor is used on this pin to set the inrush current soft start ramp profile. The voltage on the soft start pin controls the current sense voltage limit, allowing control over the inrush current profile.

11 TIMER

Timer Pin. An external capacitor, C turns off when the voltage on the TIMER pin exceeds the upper threshold.

12

LATCH

This pin signals the device latching off after an overcurrent fault. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details.

13 ADR

PMBus Address Pin. This pin can be tied low, tied to VCAP, left floating, or tied low through a resistor to set four different PMBus addresses.

14

SHDN

Drive this pin low to shut down the gate. Internal weak pull-up to VIN. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for

additional details.

15

RESTART

Falling Edge Triggered 10 sec Automatic Restart. The gate remains off for 10 seconds, and then powers back up. Internal weak pull-up to VIN. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for additional details.

DRAIN

VIN

UVH

UVL

OV

PLIM

VCAP

DC_V

ISET

SS

TIMER

LATCH

ADR

SHDN

1

2

3

4

5

ADM1075

6

(Not to Scale)

7

8

9

10

11

12

13

14

TOP VIEW

28

27

26

25

24

23

22

21

20

19

18

17

16

15

Figure 3. Pin Configuration

VEE_G

GATE

SENSE+

SENSE–

VEE

SPLYGD

ADC_AUX

PWRGD

SCL

SDAI

SDAO

GPO2/ALERT2

GPO1/ALERT1/ CONV

RESTART

PWRGD

09312-004

.

voltage of the FET. As the PLIM voltage changes, the

DS

, sets an initial timing cycle delay and a fault delay. The GATE pin

TIMER

Rev. 0 | Page 11 of 52

ADM1075 Data Sheet

Pin No. Mnemonic Description

16

17

GPO1/

GPO2/

ALERT1

ALERT2

/CONV

18 SDAO PMBus Serial Data Output. This is a split version of the SDA for easy use with optocouplers. 19 SDAI PMBus Serial Data Input. This is a split version of the SDA for easy use with optocouplers. 20 SCL PMBus Clock Pin. Open-drain input requires an external resistive pull-up. 21

PWRGD

22 ADC_AUX This pin is used to read back a voltage using the internal ADC. 23

SPLYGD

24 VEE Chip Ground Pin. Must connect to –VIN rail (lowest potential). 25 SENSE−

26 SENSE+

27 GATE

28 VEE_G

General-Purpose Digital Output (GPO1). Alert (ALERT1

). This pin can be configured to generate an alert signal when one or more fault or warning conditions have been detected. Conversion (CONV). This pin can be used as an input signal to control when a power monitor ADC sampling cycle begins. This pin defaults to indicate FET health mode at power-up. There is no internal pull-up on this pin.

General-Purpose Digital Output (GPO2). Alert (ALERT2

). This pin can be configured to generate an alert signal when one or more fault or warning conditions have been detected. This pin is also used to configure the desired retry scheme. See the Hot Swap Fault Retry section for further details. This pin defaults to indicate a seven-attempt fail at power-up. There is no internal pull-up on this pin.

Power-Good Signal. This pin is used to indicate that the FET is no longer in the linear region and capacitors are fully charged. See the

PWRGD

section for details on assert and deassert.

This pin asserts low when the supply is within the UV and OV limits set by the UVx and OV pins.

Negative Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation controls the external FET gate to maintain the (V

− V

) sense voltage. This pin also connects to the VEE node, but should be routed separately.

SENSE−

SENSE+

Positive Current Sense Input Pin. A sense resistor between the SENSE+ pin and the SENSE− pin sets the analog current limit. The hot swap operation controls the external FET gate to maintain the (V

− V

) sense voltage. This pin also connects to the FET source node.

SENSE−

SENSE+

Gate Output Pin. This pin is the gate drive of an external N-channel FET. It is driven by the FET drive controller. The FET drive controller regulates to a maximum load current by regulating the GATE pin. GATE is held low while the supply is out of the voltage range.

Chip Ground Pin. Must connect to –VIN rail (lowest potential). The PCB layout should configure this pin as the gate pull-down return.

Rev. 0 | Page 12 of 52

Data Sheet ADM1075

TYPICAL PERFORMANCE CHARACTERISTIC

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

IN

I

2.0

1.5

1.0

0.5

0

–50–35–20–5 102540557085100115

TEMPERATURE (°C)

Figure 4. I

vs. Temperature

IN

09312-005

10.0

9.5

9.0

8.5

8.0

UVLO (V )

7.5

7.0

6.5

6.0

–50 –35 –20 –5 10 25 40 55 70 85 100 115

RISING

FALLING

TEMPERATURE (° C)

Figure 7. UVLO vs. Temperature

09312-008

14.0

13.5

13.0

12.5

12.0

VIN (V)

11. 5

11. 0

10.5

10.0

–50–35–20–5 102540557085100115

IIN=30mA

=5.5mA

I

IN

TEMPERATURE (° C)

Figure 5. VIN vs. Temperature

100

+105°C

+85°C +25°C

–40°C

10

(mA)

IN

I

1

10

9

8

7

LOW (mV)

GATE

V

6

5

4

–50–35–20–5 102540557085100115

09312-006

Figure 8. V

14

12

10

HIGH (V)

GATE

V

0µA 5µA

8

6

4

TEMPERATURE (°C)

Low vs. Temperature (I

GATE

= 100 μA)

GATE

09312-009

0.1

12345678910111213

Figure 6. I

VIN (V)

vs. VIN

IN

09312-007

Rev. 0 | Page 13 of 52

2

0

–40 –20 0 20 40 60 8 0 100 120

TEMPERATURE (°C)

Figure 9. V

High vs. Temperature

GATE

09312-010

ADM1075 Data Sheet

14

12

10

8

6

PULL-DOWN (mA)

GATE

4

I

2

0

–50 –35 –20 –5 10 25 40 55 70 85 100 115

Figure 10. I

TEMPERATURE (°C)

Pull-Down vs. Temperature

GATE

09312-011

50

45

40

35

30

25

PULL-UP (µA)

20

GATE

I

15

10

5

0

0 2 4 6 8 101214

V

(V)

GATE

Figure 13. I

Pull-Up vs. V

GATE

09312-014

12

10

8

6

PULL-DOWN (mA)

4

GATE

I

2

0

0 2 4 6 8 10 12 14

Figure 11. I

0

–5

–10

–15

–20

–25

PULL-UP (µA)

–30

GATE

I

–35

–40

–45

–50

–50 –35 –20 –5 10 25 40 55 70 85 100 115

Figure 12. I

V

(V)

GATE

Pull-Down vs. V

GATE

TEMPERATURE (°C)

Pull-Up vs. Temperature

GATE

0

–2

–4

–6

–8

–10

–12

–14

SS PULL-UP CURRENT (µA)

–16

–18

–20

–50 –35 –20 –5 10 25 40 55 70 85 100 115

09312-012

TEMPERATURE (°C)

09312-015

Figure 14. SS Pull-Up Current vs. Temperature

0

–10

–20

–30

–40

PULL-UP (µA)

–50

TIMER

I

–60

–70

–80

–50–35–20–5 102540557085100115

09312-013

Figure 15. I

TEMPERATURE (°C)

Pull-Up vs. Temperature

TIMER

09312-016

Rev. 0 | Page 14 of 52

Data Sheet ADM1075

A

0

–1

–2

–3

–4

–5

–6

POR PULL-UP (µA)

–7

TIMER

I

–8

–9

–10

–50–35–20–5 102540557085100115

Figure 16. I

6

5

4

3

2

RETRY PULL-DO WN (µA)

TIMER

I

1

0

–50–35–20–5 102540557085100115

Figure 17. I

TEMPERATURE (° C)

POR Pull-Up vs. Temperature

TIMER

TEMPERATURE (°C)

Retry Pull-Down vs. Temperature

TIMER

200

180

160

140

120

100

80

60

PLIM THRESHOLD (mV)

40

20

0

–50 –35 –20 –5 10 25 40 55 70 85 100 115

09312-017

TEMPERATURE (°C)

09312-020

Figure 19. PLIM Threshold vs. Temperature

200

180

160

140

120

100

80

60

PLIM CURRENT CLAMP (mV)

40

20

0

–50–35–20–5 102540557085100115

09312-018

TEMPERATURE (° C)

09312–021

Figure 20. PLIM Current Clamp vs. Temperature

1000

800

600

400

TIMER THRESHO LD (mV)

200

0

–50 –35 –20 –5 10 25 40 55 70 85 100 115

HIGH

LOW

TEMPERATURE (°C)

Figure 18. TIMER Threshold vs. Temperature

09312-019

Rev. 0 | Page 15 of 52

3.0

2.5

2.0

P (V)

1.5

VC

1.0

0.5

0

–50 –35 –20 –5 10 25 40 55 70 85 100 115

TEMPERATURE (° C)

Figure 21. VCAP vs. Temperature (I

= 100 μA)

VCAP

09312-022

ADM1075 Data Sheet

16

14

12

1000

800

UVH

UVL

600

400

UVx THRESHOL D (mV)

200

0

–50–35–20–5 102540557085100115

TEMPERATURE (°C)

Figure 22. UVx Threshold vs. Temperature

1000

800

600

400

OV THRES HOLD (mV)

200

0

–50 –35 –20 –5 10 25 40 55 70 85 100 115

TEMPERATURE (°C)

Figure 23. OV Threshold vs. Temperature

10

8

6

RESTART TIME (s)

4

2

0

09312-023

–40 –20 0 20 40 60 80 100 120

TEMPERATURE (°C)

09312-026

Figure 25. Restart Time vs. Temperature

1000

900

800

700

600

500

400

300

200

SEVERE OC RESPONSE TIME (ns)

100

09312-024

900ns GLI TCH FILTER

200ns GLI TCH FILTER

0

–50–35–20–5 102540557085100115

TEMPERATURE (°C)

09312-027

Figure 26. Severe OC Response vs. Temperature

100

80

60

40

20

(µA)

I

SENSE

–20

–40

–60

–80

–100

SENSE–

0

SENSE+

0 20 40 60 80 100 120

Figure 24. I

V

SENSE

(mV)

vs. V

SENSE

09312-025

Rev. 0 | Page 16 of 52

60000

57.5µs GLITCH FILTER

50000

40000

30000

20000

SEVERE OC RESPONSE TIME (ns)

10000

10.7µs GLITCH FILTER

0

–50 –35 –20 –5 10 25 40 55 70 85 100 115

TEMPERATURE (°C)

Figure 27. Severe OC Response vs. Temperature

09312-028

ANALOG DEVICES ADM1075 Service Manual

FEATURES

APPLICATIONS

PRODUCT HIGHLIGHTS

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

GENERAL DESCRIPTION

SPECIFICATIONS

SERIAL BUS TIMING

ABSOLUTE MAXIMUM RATINGS

THERMAL RESISTANCE

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTION

TYPICAL PERFORMANCE CHARACTERISTIC