Analog Devices ADM1073 Datasheet

T

Full-Feature −48 V Hot Swap Controller

FEATURES

Precision inrush linear current limit
Soft start inrush current limit profiling
Precision maximum on-time in current limit
Maximum on-time modulated by FET drain voltage for

additional SOA protection

Adjustable PWM retry scheme and multiple device cascading

capability for charging large capacitive loads

Limited number of PWM cycles for FET SOA protection under

short circuit condition

Ability to configure device as continuous autoretry with a

5-second cooling period

Shunt regulator topology to allow very large transient input

supplies

Separate UV and OV pins for programming allowable input

supply window

Programmable OV hysteresis using current source into pin

when supply is high

Programmable UV hysteresis using current sink from pin

when supply is low
PWRGD

SPLYGD

LATCHED

SHDN

RESTART

GENERAL DESCRIPTION

The ADM1073 is a full-feature, negative voltage, hot swap
controller that allows boards to be safely inserted and removed
from a live −48 V backplane. The part provides precise and
robust current limiting, and protection against both transient
and nontransient short circuits in overvoltage and undervoltage
conditions. The ADM1073 can operate from a negative voltage
of −18 V to −80 V and can tolerate transient voltages of up to

−200 V.

Inrush current is limited to a programmable value by control­ling the gate drive of an external N-channel FET. The maximum
current limit is set by the choice of the sense resistor, R

output indicates when capacitor charging complete

output indicates when supply is within

valid window

output indicates the end of the retry cycle before

load capacitance is charged

input for user-commanded shutdown

input for user-triggered 5-second shutdown and

autorestart— virtual card reseat

SENSE

.

ADM1073

FUNCTIONAL BLOCK DIAGRAM

IN

VCC AND
REFERENCE
GENERATOR

OV

UV

SS

IMER

OVERVOLTAGE

DETECTOR

UNDERVOLTAGE

DETECTOR

SOFT START

CONTROL

t

CONTROL

ON

5 SECOND

SHUTDOWN

SHDN

100mV(MAX)

AND CONTROL

Figure 1.

APPLICATIONS

Central office switching
Telecommunication and data communication equipment

−48 V distributed power systems
Negative power supply control
High availability servers

−48 V power supply modules
Disk arrays

A built-in soft start function allows control of the inrush
current profile by an external capacitor on the soft start (SS)
pin.

An external capacitor on the TIMER pin determines the time
for which the FET gate is controlled to be high when maximum
inrush current flows. The ADM1073 employs a limited consec­utive retry scheme, whereby, if the load capacitance is not fully
charged within one attempt, the FET gate is pulled low and
retries after a cooling period.

(continued on Page 3)

SPLYGDV

FAULT TIMER

OSCILLATOR

FOLDBACK

AND PWRGD

PWM

TIMEOUT

LATCHEDRESTART

V

50µA

IN

PWRGD

DRAIN

GATE

SENSE

V

EE

04488-PrG-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

ADM1073

TABLE OF CONTENTS

General Description ......................................................................... 3

Timing Control—TIMER ......................................................... 15

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 6

Thermal Characteristics .............................................................. 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 8

Functional Description.................................................................. 13

Hot Circuit Insertion ................................................................. 13

Initial Startup .............................................................................. 13

Board Removal ........................................................................... 14

Controlling the Current............................................................. 14

Sense............................................................................................. 15

Sense Resistor.............................................................................. 15

Soft Start (SS Pin) ....................................................................... 15

GATE............................................................................................ 15

V

................................................................................................. 15

IN

V

................................................................................................. 15

EE

Drain ............................................................................................ 16

PWRGD

LATCHED

SPLYGD

RESTART

SHDN

Undervoltage/Overvoltage Detection ..................................... 16

Functionality and Timing.............................................................. 18

Live Insertion.............................................................................. 18

Overvoltage and Undervoltage Faults..................................... 18

Soft Start ...................................................................................... 19

Current Faults ............................................................................. 20

Logic Inputs................................................................................. 21

Kelvin Sense Resistor Connection ........................................... 21

Outline Dimensions....................................................................... 22

Ordering Guide .......................................................................... 22

....................................................................................... 16

................................................................................... 16

....................................................................................... 16

..................................................................................... 16

........................................................................................... 16

REVISION HISTORY

Revision 0: Initial Version

Rev. 0| Page 2 of 24

ADM1073

GENERAL DESCRIPTION

(continued from Page 1)

Further control of the inrush current is provided by modulating
the width of the pulses, depending on the drain-source voltage
across the FET. This allows maximum charge transfer to the
load capacitance while maintaining the FET in its safe operating
area (SOA).

The default duty cycle of the pulse train is 6%, decreasing to

2.5% with maximum FET drain-source voltage, with a
maximum of seven successive autorestarts. After seven
successive autorestarts, the fault is latched and the part goes into
shutdown, with the result that the external FET is disabled until
the power is reset. The
the seven retries are complete.

Further programmability is offered by allowing alteration of the
default 6% ratio. An extra resistor between the TIMER pin and

allows the ratio of on-time to off-time to be decreased,

V

EE

while a resistor between TIMER and V
increased.

The ADM1073 has separate UV and OV pins for undervoltage
and overvoltage detection. The FET is turned off, if a
nontransient voltage less than the undervoltage threshold

LATCHED

output signal indicates when

allows the ratio to be

IN

(typically −36 V) is detected on the UV pin, or if greater than
the overvoltage threshold (typically −80 V) is detected on the
OV pin. The operating voltage window of the ADM1073 is
programmable via resistor networks on the UV and OV pins.
The hysteresis levels on the undervoltage and overvoltage
detectors can also be altered (see the Undervoltage/Overvoltage
Detection section). The
the backplane supply is within the externally programmable
operating voltage range.

Other functions include

PWRGD

•

module (the DRAIN pin is monitored to determine when
the load capacitance is fully charged)
SHDN

•

RESTART

•

The ADM1073 is fabricated using BiCMOS technology for
minimal power consumption and is available in a 14-lead
TSSOP package.

output, which can be used to enable a power

input to manually disable the GATE drive

input to remotely initiate a 5 second shutdown

SPLYGD

output signal indicates when

Rev. 0 | Page 3 of 24

ADM1073

SPECIFICATIONS

VDD = 0 V, VEE = −48 V; TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions

BOARD SUPPLY (Not Connected Directly to Device)

Maximum Voltage Range −200 −48 −18 V

Typical Operating Voltage Range −80 −48 −35 V
VIN PIN—SHUNT REGULATOR

Operating Supply Voltage Range 11.7 12.3 12.9 V IIN = 0.6 mA to 2 mA

Quiescent Supply Current 300 500 µA VIN = 11.7 V

Maximum Shunt Supply Voltage 14 V IIN = 10 mA

Undervoltage Lockout, V

8 V

LKO

Power-On Reset Delay 150 ms
UV, OV PINS—UNDERVOLTAGE AND OVERVOLTAGE DETECTION

Undervoltage Falling Threshold, V

825 868 910 mV

UVF

Undervoltage Hysteresis Current 5 µA

Undervoltage Fault Filter 0.6 ms

Overvoltage Rising Threshold, V

1.86 1.93 2.00 V

OVR

Overvoltage Hysteresis Current 5 µA

Overvoltage Fault Filter 5 µs

Input Current 0.2 µA
GATE PIN—FET DRIVER

Maximum Gate Voltage 11.5 V

V I

IN(MAX)

Minimum Gate Voltage 10 100 mV I

Pull-Up Current −50 µA V

−36 µA V

Pull-Down Current 20 mA V

50 mA V
SENSE PIN—CURRENT SENSE—SOFT START

Current Limit Control Loop Threshold, V

97 100 103 mV I

ACL

Circuit Breaker Limit Voltage, VCB 86 90 mV

Fast Current Limit Voltage, V

110 mV

FCL

Control Loop Transconductance 4.5 µA/mV

Soft Start Pin Current 5 µA
TIMER PIN—PWM CONTROL

Minimum TIMER Pull-Up Current 18 19 20 µA I

16 19 20 µA I

Maximum TIMER Pull-Up Current 37 39 41 µA I

34 39 41 µA I

TIMER Pull-Down Current 1 µA

TIMER Low Voltage Trip Point 0.45 0.50 0.55 V

TIMER High Voltage Trip Point 2.34 2.42 2.50 V

Current Limit On-Time, tON 6 ms I

Current Limit On-Time, tON, with Foldback 3 ms I

Number of Consecutive PWM Retry Cycles 7

Continuous Short-Circuit Time before Latched Shutdown 0.6 s C

Limited by external components

= −1.0 µA

GATE

= 1.0 µA

GATE

= 0 V to 8 V; VSS = 2 V

GATE

= 0 V to 8 V; VSS = 0 V

GATE

> 2 V

GATE

> 5 V

GATE

= 0 mA

GATE

< 4 µA; TA = 25°C to 85°C

PWRGD

< 4 µA

PWRGD

= 24 µA; TA = 25°C to 85°C

PWRGD

= 24 µA

PWRGD

= 4 µA; C

DRAIN

= 20 µA; C

DRAIN

TIMER

= 47 nF

TIMER

TIMER

= 47 nF

= 47 nF

Rev. 0| Page 4 of 24

ADM1073

Parameter Min Typ Max Unit Test Conditions

DRAIN (FOLDBACK) AND PWRGD

DRAIN Voltage at Which PWRGD Asserts
Maximum DRAIN Pin Current Allowable, I

36 µA VDS = 80 V; R

DRAIN(MAX)

PWRGD Output Voltage Low

0.2 0.4 V I

PWRGD Internal Pull-Up Current
PWRGD Output Voltage High

RESTART

Time before Restart 5 s
Input Threshold 1.35 1.45 1.55 V
Glitch Filter 5 µs
Internal Pull-Up Current 6 µA

SHDN

Glitch Filter 5 µs
Input Threshold 1.35 1.45 1.55 V
Internal Pull-Up Current 6 µA

LATCHED AND SPLYGD

Output Voltage Low 1 2 V I

0.2 0.4 V I

Internal Pull-Up Current 6 µA
Output Voltage High VIN V

1.9 2 2.1 V R

1 2 V I

= 3.75 M to 20 M

DRAIN

= 2.5 mA

PWRGD

= 0.5 mA

PWRGD

6 µA
V

V

IN

LATCHED

LATCHED

, I

, I

SPLYGD

SPLYGD

= 3.25 M

DRAIN

= 2.5 mA

= 0.5 mA

Rev. 0 | Page 5 of 24

ADM1073

ABSOLUTE MAXIMUM RATINGS

All voltages referred to VEE, TA = 25°C, unless otherwise noted.

Table 2.

Parameter Rating

Supply Voltage (V
Maximum Shunt Supply Voltage, VSS 16 V
SENSE Pin −2 V to +2 V
GATE Pin −0.3 V to +16 V
UV Pin −0.3 V to +6 V
OV Pin −0.3 V to +6 V
SS Pin −0.3 V to +6 V
TIMER Pin −0.3 V to +6 V
DRAIN Pin −0.3 V to +6 V
SHDN Pin
SPLYGD Pin
LATCHED Pin
PWRGD Pin
RESTART Pin
Maximum Junction Temperature 125°C
Operating Temperature Range −40°C to +85°C
Continuous Power Dissipation 180 mW
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 s) 300°C

− VEE) −0.3 V to −200.0 V

DD

−0.3 V to +16 V

−0.3 V to +16 V

−0.3 V to +16 V

−0.3 V to +16 V

−0.3 V to +16 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

14-lead TSSOP Package:

θ

JA

θ

JC

= 240°C/W
= 43°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0| Page 6 of 24

ADM1073

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

RESTART

V

PWRGD

SS

SENSE

V

LATCHED

IN

EE

1
2
3

ADM1073

4

TOP VIEW

(Not to Scale)

5
6
7

14
13
12
11
10

9
8

SHDN
TIMER
UV
OV
DRAIN
GATE
SPLYGD

04488-PrG-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin Number Mnemonic Function

1

RESTART

2 VIN

3

PWRGD

4 SS

Input Pin. Edge-triggered 5-second shutdown and automatic restart.
Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via shunt resistor. A 1 µF

capacitor to V

is recommended on the VIN pin.

EE

Open Drain Output. Signals that the hot swap is complete.
Analog Pin for Soft Start. An external capacitor on this pin sets the ramp rate of the inrush current

profile. This pin can be overdriven to alter the current limit control loop threshold.
5 SENSE Voltage Input from External Sense Resistor.
6 VEE Ground Supply to Chip (usually a −48 V system supply). Also low-side sense resistor connection.
7

8

LATCHED
SPLYGD

Open Drain Output. Signals that the device is not in reset and that the supply is in operating voltage

Open Drain Output. Signals the end of the PWM retry period after a current fault.

window.
9 GATE Output to External FET Gate Drive.
10 DRAIN Analog Input for Monitoring of FET Drain Voltage.
11 OV Input Pin for Overvoltage Detection Circuitry.
12 UV Input Pin for Undervoltage Detection Circuitry.
13 TIMER

Analog Pin. An external capacitor on this pin sets the maximum allowable time in current limit, the

PWM on-time, and the PWM duty cycle.
14

SHDN

Input Pin. Level-triggered device shutdown and reset.

Rev. 0 | Page 7 of 24

ADM1073

TYPICAL PERFORMANCE CHARACTERISTICS

500

450

400

350

300

250

(µA)

IN

I

200

150

100

50

100.0

0

TEMPERATURE (°C)

Figure 3. I

vs. Temperature

IN

85–50–35–20–51025405570

04488-PrG-003

14.5

14.0

13.5

13.0

(V)

IN

12.5

V

12.0

11.5

11.0

TEMPERATURE (°C)

Figure 6. V

vs. Temperature

IN

85–50–35–20–51025405570

04488-PrG-006

12

10

10.0

(mA)

IN

I

(Ω)

Z

R

1.0

0.1

10

9

8

7

6

5

4

3

2

1

0

1.5

0.5

Figure 5. R

TA = –40°C

TA = +25°C

TA = +85°C

3.5

5.5

7.5

2.5

4.5

6.5

Figure 4. I

VIN (V)

IN

8.5

vs. V

9.5

IN

TEMPERATURE (°C)

(VIN Forward Voltage) vs. Temperature

Z

10.5

11.5

12.5

13.5

14.5

8

(V)

6

LKO

V

4

2

04488-PrG-004

0

TEMPERATURE (°C)

Figure 7. Undervoltage Lockout, V

, vs. Temperature

LKO

85–50 –35 –20 –5 –10 25 40 55 70

04488-PrG-007

400

350

300

250

200

150

DELAY (ms)

100

50

85–50–35–20–51025405570

04488-PrG-005

0

TEMPERATURE (°C)

85–50 –35 –20 –50 10 25 40 55 70

04488-PrG-008

Figure 8. POR Delay vs. Temperature

Rev. 0| Page 8 of 24