Analog Devices ADM1067 a Datasheet
Super Sequencer™ with
FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
better than 1% accuracy
5 selectable input attenuators allow supervision:
Supplies up to 14.4 V on VH
Supplies up to 6 V on VP1–4
5 dual-function inputs, VX1–5:
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable output drivers (PDO1–10):
Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external
N-FET (PDO1–6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs:
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Open-loop margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow
voltage adjustment via dc/dc converter trim/feedback
node
Device powered by the highest of VP1–4, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
40-lead 6 mm × 6 mm LFCSP and
48-lead 7 mm × 7 mm TQFP packages
Open-Loop Margining DACs
ADM1067
FUNCTIONAL BLOCK DIAGRAM
REFOUT REFGND
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
SFDGND
VDDCAP
MUP
VH
ADM1067
(LOGIC INPUTS
PROGRAMMABLE
GENERATORS
ARBITRATOR
V
OUT
DAC
DAC1
DUAL-
FUNCTION
INPUTS
OR
SFDs)
RESET
(SFDs)
VDD
DAC2
V
DAC
VREF
OUT
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1067 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems. In addition to these
functions, the ADM1067 integrates six 8-bit voltage output
DACs. These circuits can be used to implement a open-loop
margining system, which enables supply adjustment by altering
either the feedback node or reference of a dc/dc converter using
the DAC outputs.
SDA SCL A1 A0
INTERFACE
SEQUENCING
ENGINE
V
V
OUT
DAC
DAC
DAC3
DAC4
Figure 1.
SMBus
OUT
EEPROM
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE
OF DRIVING
GATES OF
N-CHANNEL FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
V
V
OUT
DAC
DAC5
OUT
DAC
DAC6
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
GND
VCCP
MDN
04635-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
(continued on Page 3)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
ADM1067
TABLE OF CONTENTS
General Description......................................................................... 3
Monitoring Fault Detector ........................................................ 19
Specifications..................................................................................... 4
Pin Configurations and Function Descriptions ........................... 7
Absolute Maximum Ratings............................................................ 8
Thermal Characteristics .............................................................. 8
ESD Caution.................................................................................. 8
Typical Performance Characteristics............................................. 9
Powering the ADM1067................................................................ 12
Inputs................................................................................................ 13
Supply Supervision .....................................................................13
Programming the Supply Fault Detectors............................... 13
Input Comparator Hysteresis.................................................... 14
Input Glitch Filtering ................................................................. 14
Supply Supervision with VXn Inputs....................................... 14
VXn Pins as Digital Inputs........................................................ 15
Outputs ............................................................................................ 16
Timeout Detector ....................................................................... 19
Fault Reporting ........................................................................... 19
Supply Margining ........................................................................... 20
Overview ..................................................................................... 20
Open-Loop Margining .............................................................. 20
Writ i ng to t he DACs .................................................................. 20
Choosing the Size of the Attenuation Resistor...................... 21
DAC Limiting/Other Safety Features ...................................... 21
Applications Diagram .................................................................... 22
Communicating with the ADM1067........................................... 23
Configuration Download at Power-Up................................... 23
Updating the Configuration ..................................................... 23
Updating the Sequencing Engine............................................. 24
Internal Registers........................................................................ 24
EEPROM ..................................................................................... 24
Supply Sequencing through Configurable Output Drivers .. 16
Sequencing Engine......................................................................... 17
Overview...................................................................................... 17
Wa r ni n g s ...................................................................................... 17
SMBus Jump/Unconditional Jump .......................................... 17
Sequencing Engine Application Example ...............................18
Sequence Detector...................................................................... 19
REVISION HISTORY
1/05—Rev. 0 to Rev. A
Changes to Figure 1.......................................................................... 1
Changes to Absolute Maximum Ratings Section ......................... 8
Change to Supply Sequencing through Configurable
Output Drivers Section............................................................... 16
Changes to Figure 28...................................................................... 22
Change to Table 9 ........................................................................... 25
10/04—Revision 0: Initial Version
Serial Bus Interface..................................................................... 24
SMBus Protocols for RAM and EEPROM.............................. 26
Write Operations........................................................................ 26
Read Operations......................................................................... 28
Outline Dimensions....................................................................... 30
Ordering Guide .......................................................................... 30
Rev. A | Page 2 of 32
ADM1067
GENERAL DESCRIPTION
(continued from Page 1)
Supply margining can be performed with a minimum of
external components. The margining capability can be used for
in-circuit testing of a board during production (for example, to
verify the board’s functionality at −5% of nominal supplies), or
can be used dynamically to accurately control the output
voltage of a dc/dc converter.
The device also provides up to ten programmable inputs for
monitoring under, over, or out-of-window faults on up to ten
supplies. In addition, ten programmable outputs can be use d as
logic enables. Six of them can also provide up to a 12 V output
REFOUT REFGND
SDASCLA1A0
for driving the gate of an N-channel FET, which can be placed
in the path of a supply.
The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can
be programmed using an intuitive GUI-based software package
provided by ADI.
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VDDCAP
VDDCAP
VREF
ADM1067
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
VDD
ARBITRATOR
REG 5.25V
CHARGE PUMP
SMBus
INTERFACE
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
V
OUT
DAC
V
OUT
DAC
DEVICE
CONTROLLER
SEQUENCING
ENGINE
V
V
OUT
DAC
OUT
DAC
OSC
EEPROM
CONFIGURABLE
O/P DRIVER
(HV)
CONFIGURABLE
O/P DRIVER
(HV)
CONFIGURABLE
O/P DRIVER
(LV)
CONFIGURABLE
O/P DRIVER
(LV)
V
V
OUT
DAC
OUT
DAC
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
GND
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
04635-002
Figure 2. Detailed Block Diagram
Rev. A | Page 3 of 32
ADM1067
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPn 3.0 V Minimum supply required on one of VPn, VH
VP 6.0 V Maximum VDDCAP = 5.1 V, typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
C
VDDCAP
POWER SUPPLY
Supply Current, IVH, I
Additional Currents
All PDO FET Drivers On 1 mA
Current Available from VDDCAP 2 mA
DACs Supply Current 2.2 mA 6 DACs on with 100 µA maximum load on each
ADC Supply Current 1 mA Running round-robin loop
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V
SUPPLY FAULT DETECTORS
VH Pin
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges
High Range 6 14.4 V
Midrange 2.5 6 V
VPn Pins
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges
Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error
VX Pins
Input Impedance 1 MΩ
Detection Ranges
Ultralow Range 0.573 1.375 V No input attenuation error
Absolute Accuracy ±1 %
Threshold Resolution 8 Bits
Digital Glitch Filter 0 µs Minimum programmable filter length
100 µs Maximum programmable filter length
BUFFERED VOLTAGE OUTPUT DACs
Resolution 8 Bits
Code 0x80 Output Voltage
Range 1 0.592 0.6 0.603 V
Range 2 0.796 0.8 0.803 V
Range 3 0.997 1 1.003 V
Range 4 1.247 1.25 1.253 V
Output Voltage Range 601.25 mV Same range, independent of center point
LSB Step Size 2.36 mV
INL ±0.75 LSB Endpoint corrected
VPn
10 µF Minimum recommended decoupling capacitance
4.2 6 mA VDDCAP = 4.75 V, PDO1–10 off, DACs off, ADC off
VDDCAP = 4.75 V, PDO1-6 loaded with 1 µA each,
PDO7–10 off
Maximum additional load that can be drawn from
all PDO pull-ups to VDDCAP
VREF error + DAC nonlinearity + comparator offset
error + input attenuation error
6 DACs are individually selectable for centering on
one of four output voltage ranges
Rev. A | Page 4 of 32
ADM1067
Parameter Min Typ Max Unit Test Conditions/Comments
DNL ±0.4 LSB
Gain Error 1 %
Load Regulation
−4
2 mV Sinking Current, I
Maximum Load Capacitance 50 pF
Settling Time into 50 pF Load 2 µs
Load Regulation 2.5 mV Per mA
PSRR 60 dB DC
40 dB 100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation
−0.25
0.25 mV Sinking current, I
Minimum Load Capacitance 1 µF Capacitor required for decoupling, stability
Load Regulation 2 mV Per 100 µA
PSRR 60 dB DC
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDO1–6)
Output Impedance 500 kΩ
V
OH
11 12.5 14 V IOH = 0
10.5 12 13.5 V IOH = 1 µA
I
OUTAVG
20 µA 2 V < V
Standard (Digital Output) Mode (PDO1–10)
V
OH
2.4 V VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA
4.5 V VPU to Vpn = 6.0 V, IOH = 0 mA
V
V
OL
2
I
OL
2
I
SINK
R
PULL-UP
I
(VPn)2 2 mA
SOURCE
− 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA
PU
0 0.50 V IOL = 20 mA
20 mA Maximum sink current per PDO pin
60 mA Maximum total sink for all PDOs
20 kΩ Internal pull-up
Three-State Output Leakage Current 10 µA V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXn, A0, A1, MUP, MDN)
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
IH
IL
IH
IL
2.0 V Maximum VIN = 5.5 V
0.8 V Maximum VIN = 5.5 V
−1 µA VIN = 5.5 V
1 µA VIN = 0
Input Capacitance 5 pF
Programmable Pull-Down Current,
I
PULL-DOWN
20 µA
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, V
Input Low Voltage, V
Output Low Voltage, V
IH
IL
2
OL
2.0 V
0.8 V
0.4 V I
SERIAL BUS TIMING
Clock Frequency, f
Bus Free Time, t
BUF
Start Setup Time, t
Start Hold Time, t
SCLK
SU;STA
HD;STA
400 kHz
4.7 µs
4.7 µs
4 µs
mV
mV
Sourcing Current, I
Sourcing current, I
Current load on any VPn pull-ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
PDO
VDDCAP = 4.75, T
required
OUT
< 7 V
OH
= 14.4 V
= −3.0 mA
= −200 µA
REFOUTMAX
= 100 µA
REFOUTMAX
= −100 µA
DACnMAX
= 100 µA
DACnMAX
= 25°C, if known logic state is
A
Rev. A | Page 5 of 32
ADM1067
Parameter Min Typ Max Unit Test Conditions/Comments
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Input Low Current, I
LOW
HIGH
r
f
SU;DAT
HD;DAT
IL
SEQUENCING ENGINE TIMING
State Change Time 10 µs
1
At least one of the VH, VP1–4 pins must be ≥ 3.0 V to maintain the device supply on VDDCAP.
2
Specification is not production tested, but is supported by characterization data at initial product release.
4.7 µs
4 µs
1000 µs
300 µs
250 ns
5 ns
1 µA VIN = 0
Rev. A | Page 6 of 32
ADM1067
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND40VDDCAP39MDN38MUP37SDA36SCL35A134A033VCCP32PDOGND
X1
1
PIN 1
INDICATOR
2
X2
X3
3
X4
4
X5
5
6
P1
7
P2
P3
8
P4
9
VH
10
11
12NC13
AGND
NC = NO CONNECT
REFGND
Figure 3. LFCSP Pin Configuration
ADM1067
TOP VIEW
(Not to Scale)
14
DAC115DAC216DAC317DAC418DAC519DAC6
REFOUT
NC48GND47VDDCAP46MDN45MUP44SDA43SCL42A141A040VCCP39PDOGND38NC
31
PDO1
30
29
PDO2
PDO3
28
PDO4
27
PDO5
26
25
PDO6
24
PDO7
PDO8
23
PDO9
22
PDO10
21
20
04635-003
NC
1
X1
X2
X3
X4
X5
P1
P2
P3
P4
VH
NC
NC = NO CONNECT
PIN 1
2
INDICATOR
3
4
5
6
7
8
9
10
11
12
13
14
NC
AGND
15NC16
REFGND
ADM1067
TOP VIEW
(Not to Scale)
17
DAC118DAC219DAC320DAC421DAC522DAC6
REFOUT
Figure 4. TQFP Pin Configuration
23NC24
37
NC
36
PDO1
35
PDO2
34
PDO3
33
32
PDO4
31
PDO5
30
PDO6
29
PDO7
28
PDO8
27
PDO9
26
PDO10
NC
25
04635-004
Table 2. Pin Function Descriptions
Pin No.
LFCSP TQFP
13
1, 12–13,
Mnemonic Description
NC No connection.
16, 24–25,
36–37, 48
1–5 2–6 VX1–5
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
6–9 7–10 VP1–4
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply
fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.
10 11 VH
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
11 14 AGND Ground Return for Input Attenuators.
12 15 REFGND Ground Return for On-Chip Reference Circuits.
14 17 REFOUT 2.048 V Reference Output.
15–20 18–23 DAC1–6 Voltage Output DACs. These pins default to high impedance at power-up.
21–30 26–35 PDO10–1 Programmable Output Drivers.
31 38 PDOGND Ground Return for Output Drivers.
32 39 VCCP
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
and GND.
33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 SCL SMBus Clock Pin. Open-drain output requires external resistive pull-up.
36 43 SDA SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
37 44 MUP
Digital Input. Forces DACs to their lowest value, causing the voltage at the feedback node to drop,
which is compensated for by the output voltage of the supply increasing, thus margining up.
38 45 MDN
Digital Input. Forces DACs to their highest value, causing the voltage at the feedback node to rise,
which is compensated for by the output voltage of the supply decreasing, thus margining down.
39 46 VDDCAP Device Supply Voltage. Linearly regulated from the highest of the VP1–4, VH pins to a typical of 4.75 V.
40 47 GND Supply Ground.
Rev. A | Page 7 of 32
ADM1067
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Voltage on VH Pin 16 V
Voltage on VP Pins 7 V
Voltage on VX Pins −0.3 V to +6.5 V
Voltage on MUP, MDN Pins −0.3 V to +5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
Vapor Phase, 60 sec 215°C
ESD Rating, All Pins 2000 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
40-lead LFCSP package: θJA = 25°C/W.
48-lead TQFP package: θ
= 14.8°C/W.
JA
Rev. A | Page 8 of 32
ADM1067
TYPICAL PERFORMANCE CHARACTERISTICS
6
5
4
(V)
3
VDDCAP
V
2
1
0
0654321
Figure 5. V
V
VP1
VDDCAP
(V)
vs. V
VP1
6
5
4
(V)
3
VDDCAP
V
2
1
0
0161412108642
Figure 6. V
VVH (V)
VDDCAP
vs. V
VH
5.0
4.5
4.0
3.5
3.0
2.5
(mA)
VP1
I
2.0
1.5
1.0
0.5
0
0123456
Figure 7. I
VP1
vs. V
V
VP1
VP1
(V)
(VP1 as Supply)
04635-050
04635-051
04635-052
180
160
140
120
100
(µA)
80
VP1
I
60
40
20
0
0123456
Figure 8. I
V
(V)
VP1
vs. V
VP1
(VP1 Not as Supply)
VP1
5.0
4.5
4.0
3.5
3.0
2.5
(mA)
VH
I
2.0
1.5
1.0
0.5
0
0161412108642
Figure 9. I
VVH (V)
vs. VVH (VH as Supply)
VH
350
300
250
200
(µA)
VH
150
I
100
50
0
0654321
Figure 10. I
VH
vs. V
VH
VVH (V)
(VH Not as Supply)
04635-053
04635-054
04635-055
Rev. A | Page 9 of 32
ADM1067
14
12
10
8
CHARGE PUMPED
PDO1
V
5.0
4.5
4.0
3.5
3.0
(V)
2.5
PDO1
V
2.0
1.5
1.0
0.5
4.5
4.0
3.5
3.0
2.5
(V)
2.0
PDO1
V
1.5
1.0
0.5
6
4
2
0
0 15.012.510.07.55.02.5
0
0654321
Figure 12. V
0
0605040302010
Figure 13. V
Figure 11. V
VP1 = 3V
VP1 = 3V
I
CURRENT (µA)
LOAD
(FET Drive Mode) vs. I
PDO1
I
(mA)
LOAD
(Strong Pull-Up VP) vs. I
PDO1
VP1 = 5V
I
(µA)
LOAD
(Weak Pull-Up to VP) vs. I
PDO1
LOAD
VP1 = 5V
LOAD
LOAD
04635-056
04635-057
04635-058
DAC
20kΩ
BUFFER
OUTPUT
47pF
1
CH1 200mV M1.00µs CH1 756mV
Figure 14. Transient Response of DAC Code Change into Typical Load
DAC
BUFFER
OUTPUT
PROBE
POINT
1
CH1 200mV M1.00µs CH1 944mV
Figure 15. Transient Response of DAC to Turn-On from HI-Z State
1.005
1.004
1.003
1.002
1.001
1.000
0.999
DAC OUTPUT
0.998
0.997
0.996
0.995
–40 –20 0 20 40 60 10080
VP1 = 4.75V
TEMPERATURE (°C)
VP1 = 3.0V
Figure 16. DAC Output vs. Temperature
100kΩ
PROBE
POINT
04635-065
04635-059
1V
04635-060
Rev. A | Page 10 of 32
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