ANALOG DEVICES ADM1067 Service Manual

Super Sequencer with

www.BDTIC.com/ADI

FEATURES

Complete supervisory and sequencing solution for up to

10 supplies

10 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures

5 selectable input attenuators allow supervision of supplies to

14.4 V on VH
6 V on VP1 to VP4 (VPx)

5 dual-function inputs, VX1 to VX5 (VXx)

High impedance input to supply fault detector with

thresholds bet

General-purpose logic input

10 programmable driver outputs, PDO1 to PDO10 (PDOx)

Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external

N-FE

T (PDO1 to PDO6 only)

Sequencing engine (SE) implements state machine control of

PDO ou

tputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus

Open-loop margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage

adju

stment via dc-to-dc converter trim/feedback node

Device powered by the highest of VPx, VH for improved

dundancy

re
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and

48-lead, 7 mm × 7 mm TQFP packages

For more information about the ADM1067 register map,

ref

er to the AN-698 Application Note at

ween 0.573 V and 1.375 V

www.analog.com.

Open-Loop Margining DACs

ADM1067

FUNCTIONAL BLOCK DIAGRAM

REFOUT REFGND

AGND

V

DDCAP

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

VH

MUP

ADM1067

FUNCTION

(LOGIC INPUTS

PROGRAM MABLE

GENERATORS

ARBITR ATOR

V

OUT

DAC

DAC1

DUAL-

INPUTS

SFDs)

RESET

(SFDs)

VDD

VREF

OR

V

OUT

DAC

DAC2

APPLICATIONS

Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies

GENERAL DESCRIPTION

The ADM1067 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple supply systems. In addition
to these functions, the ADM1067 integrates six 8-bit voltage
output DACs. These circuits can be used to implement an open­loop margining system that enables supply adjustment by altering
either the feedback node or reference of a dc-to-dc converter
using the DAC outputs.

SDA SCL A1 A0

SEQUENCING

ENGINE

V

OUT

DAC

DAC3

Figure 1.

SMBus

INTERFACE

V

OUT

DAC

DAC4

EEPROM

CONFIG URABLE

OUTPUT

DRIVERS

(HV CAPABLE O F

DRIVING GATES

OF N-FET)

CONFIG URABLE

OUTPUT

DRIVERS

(LV CAPABLE

OF DRIVING

LOGIC SIGNALS)

V

V

OUT

DAC

DAC5

OUT

DAC

DAC6

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PDO9

PDO10

PDOGND

GND

VCCP

MDN

04635-001

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2004–2008 Analog Devices, Inc. All rights reserved.

ADM1067

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features.............................................................................................. 1

Functional Block Diagram .............................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Detailed Block Diagram .................................................................. 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 7

Thermal Resistance ...................................................................... 7

ESD Caution.................................................................................. 7

Pin Configurations and Function Descriptions ........................... 8

Typical Performance Characteristics ........................................... 10

Powering the ADM1067................................................................ 13

Inputs................................................................................................ 14

Supply Supervision..................................................................... 14

Programming the Supply Fault Detectors............................... 14

Input Comparator Hysteresis.................................................... 14

Input Glitch Filtering ................................................................. 15

Supply Supervision with VXx Inputs....................................... 15

VXx Pins as Digital Inputs........................................................ 15

Outputs ............................................................................................ 16

Supply Sequencing Through Configurable Output Drivers. 16

Default Output Configuration.................................................. 16

Sequencing Engine .........................................................................17

Overview...................................................................................... 17

Warnings...................................................................................... 17

SMBus Jump (Unconditional Jump)........................................ 17

Sequencing Engine Application Example............................... 18

Fault and Status Reporting........................................................ 19

Supply Margining........................................................................... 20

Overview ..................................................................................... 20

Open-Loop Supply Margining ................................................. 20

Writing to the DACs .................................................................. 20

Choosing the Size of the Attenuation Resistor....................... 21

DAC Limiting and Other Safety Features............................... 21

Applications Diagram.................................................................... 22

Communicating with the ADM1067........................................... 23

Configuration Download at Power-Up................................... 23

Updating the Configuration ..................................................... 23

Updating the Sequencing Engine............................................. 24

Internal Registers........................................................................ 24

EEPROM ..................................................................................... 24

Serial Bus Interface..................................................................... 24

SMBus Protocols for RAM and EEPROM.............................. 27

Write Operations........................................................................ 27

Read Operations......................................................................... 28

Outline Dimensions....................................................................... 30

Ordering Guide .......................................................................... 30

REVISION HISTORY

5/08—Rev. B to Rev. C

Changes to Figure 1.......................................................................... 1

Changes to Table 1............................................................................ 4

Changes to Powering the ADM1067 Section ............................. 13

Changes to Sequence Detector Section ....................................... 18

Changes to Figure 27...................................................................... 20

Changes to Configuration Download at Power-Up Section..... 23

Changes to Table 10........................................................................ 24

Changes to Figure 40 and Error Correction Section ................. 29

Changes to Ordering Guide.......................................................... 30

11/06—Rev. A to Rev. B

U

pdated Format..................................................................Universal

Changes to Features.......................................................................... 1

Changes to Figure 2.......................................................................... 3

Changes to Table 1............................................................................ 4

Changes to Table 2............................................................................ 7

Changes to Absolute Maximum Ratings Section......................... 9

Rev. C | Page 2 of 32

Changes to Programming the Supply Fault Detectors Section... 14

hanges to Table 6.......................................................................... 14

C

Added the Default Output Configuration Section .................... 18

Changes to Fault Reporting Section ............................................ 21

Changes to Figure 28...................................................................... 24

Changes to the Identifying the ADM1067

on the SMBus Section .................................................................... 26

Changes to Figure 30 and Figure 31............................................. 28

Changes to Ordering Guide.......................................................... 32

1/05—Rev. 0 to Rev. A

C

hanges to Figure 1...........................................................................1

Changes to Absolute Maximum Ratings Section..........................8

Change to Supply Sequencing through Configurable

Output Drivers Section.................................................................. 16

Changes to Figure 28...................................................................... 22

Change to Table 9........................................................................... 25

10/04—Revision 0: Initial Version

ADM1067

www.BDTIC.com/ADI

Supply margining can be performed with a minimum of external
components. The margining capability can be used for in-circuit
testing of a board during production (for example, to verify
board functionality at −5% of nominal supplies), or it can be
used dynamically to accurately control the output voltage of
a dc-to-dc converter.

The device also provides up to 10 programmable inputs for
m

onitoring undervoltage faults, overvoltage faults, or out-of­window faults on up to 10 supplies. In addition, 10 program­mable outputs can be used as logic enables.

DETAILED BLOCK DIAGRAM

Six of these programmable outputs can also provide up to a 12 V
o

utput for driving the gate of an N-FET that can be placed in

the path of a supply.

The logical core of the device is a sequencing engine. This state­machi

ne-based construction provides up to 63 different states.
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.

The device is controlled via configuration data that can be

rogrammed into an EEPROM. The entire configuration can

p
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

AGND

VDDCAP

MUP

VCCP

VH

REFOUT REFGND

VREF

ADM1067

SELECTABLE
ATTENUATOR

SELECTABLE
ATTENUATOR

VDD

ARBITRATOR

REG 5.25V

CHARGE PUMP

SDA SCL A1 A0

GPI SIGNAL

CONDITIO NING

SFD

GPI SIGNAL

CONDITIO NING

SFD

SFD

SFD

V

DAC

OUT

V

DAC

SMBus

INTERFACE

OUT

SEQUENCING

ENGINE

V

OUT

DAC

DEVICE

CONTROLL ER

V

OUT

DAC

OSC

EEPROM

CONFIGURABLE
OUTPUT DRIVER

(HV)

CONFIGURABLE
OUTPUT DRIVER

(HV)

CONFIGURABLE
OUTPUT DRIVER

(LV)

CONFIGURABLE
OUTPUT DRIVER

(LV)

V

DAC

OUT

V

OUT

DAC

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PDO9

PDO10

MDN

PDOGND

GND

DAC1

DAC2

Figure 2. Detailed Block Diagram

Rev. C | Page 3 of 32

DAC3

DAC4

DAC5

DAC6

04635-002

ADM1067

www.BDTIC.com/ADI

SPECIFICATIONS

VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY ARBITRATION

VH, VPx 3.0 V Minimum supply required on one of VH, VPx
VPx 6.0 V Maximum VDDCAP = 5.1 V, typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
C

10 μF Minimum recommended decoupling capacitance

VDDCAP

POWER SUPPLY

Supply Current, IVH, I
Additional Currents

All PDO FET Drivers On 1 mA

Current Available from VDDCAP 2 mA

DACs Supply Current 2.2 mA Six DACs on with 100 μA maximum load on each
ADC Supply Current 1 mA Running round-robin loop
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V

SUPPLY FAULT DETECTORS

VH Pin

Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges

High Range 6 14.4 V
Midrange 2.5 6 V

VPx Pins

Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges

Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error

VXx Pins

Input Impedance 1 MΩ
Detection Ranges

Ultralow Range 0.573 1.375 V No input attenuation error

Absolute Accuracy ±1 %

Threshold Resolution 8 Bits
Digital Glitch Filter 0 μs Minimum programmable filter length
100 μs Maximum programmable filter length

BUFFERED VOLTAGE OUTPUT DACs

Resolution 8 Bits
Code 0x80 Output Voltage

Range 1 0.592 0.6 0.603 V
Range 2 0.796 0.8 0.803 V
Range 3 0.997 1 1.003 V

Range 4 1.247 1.25 1.253 V
Output Voltage Range 601.25 mV Same range, independent of center point
LSB Step Size 2.36 mV

4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off

VPx

VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,

O7 to PDO10 off

PD
Maximum additional load that can be drawn from all PDO

pull-ups to

VREF error + DAC nonlinearity + comparator offset error +

nput attenuation error

i

Six DACs are individually selectable for centering on one of

our output voltage ranges

f

VDDCAP

Rev. C | Page 4 of 32

ADM1067

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

INL ±0.75 LSB Endpoint corrected
DNL ±0.4 LSB
Gain Error 1 %
Maximum Load Current (Source) 100 μA
Maximum Load Current (Sink) 100 μA
Maximum Load Capacitance 50 pF
Settling Time into 50 pF Load 2 μs
Load Regulation 2.5 mV Per mA

PSRR 60 dB DC
40 dB 100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT

Reference Output Voltage 2.043 2.048 2.053 V No load

Load Regulation

−0.25

0.25 mV Sinking current, I

Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability

PSRR 60 dB DC
PROGRAMMABLE DRIVER OUTPUTS

High Voltage Charge Pump Mode

(PDO1 to PDO6)
Output Impedance 500 kΩ
VOH 11 12.5 14 V IOH = 0 μA

10.5 12 13.5 V IOH = 1 μA
I

20 μA 2 V < V

OUTAVG

Standard (Digital Output) Mode

(PDO1 to PDO10)
VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA

4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
V

V V

−

PU

0.3

VOL 0 0.50 V IOL = 20 mA

2

I

OL

2

I

SINK

R

16 20 29 kΩ Internal pull-up

PULL-UP

I

SOURCE

(VPx)

2

20 mA Maximum sink current per PDOx pin
60 mA Maximum total sink for all PDOx pins

2 mA

Three-State Output Leakage Current 10 μA V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock

DIGITAL INPUTS (VXx, A0, A1, MUP, MDN)

Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 μA VIN = 5.5 V
Input Low Current, IIL 1 μA VIN = 0 V
Input Capacitance 5 pF
Programmable Pull-Down Current,

I

PULL-DOWN

20 μA VDDCAP = 4.75 V, T

SERIAL BUS DIGITAL INPUTS (SDA, SCL)

Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, V

2

OL

0.4 V I

mV

Sourcing current, I

PU

Current load on any VPx pull-ups, that is, total source current

vailable through any number of PDO pull-up switches

a
configured onto any one VPx pin

PDO

OUT

DACxMAX

DACxMAX

< 7 V

OH

≤ 2.7 V, IOH = 0.5 mA

= 14.4 V

= 25°C, if known logic state is required

A

= −3.0 mA

= −100 μA

= 100 μA

Rev. C | Page 5 of 32

ADM1067

www.BDTIC.com/ADI

Parameter Min Typ Max Unit Test Conditions/Comments

SERIAL BUS TIMING

Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Stop Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, tR 1000 μs
SCL, SDA Fall Time, tF 300 μs
Data Setup Time, t
Data Hold Time, t
Input Low Current, IIL 1 μA VIN = 0

SEQUENCING ENGINE TIMING

State Change Time 10 μs

1

At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.

2

Specification is not production tested but is supported by characterization data at initial product release.

400 kHz

SCLK

4.7 μs

BUF

4.7 μs

SU;STA

4 μs

SU;STO

4 μs

HD;STA

4.7 μs

LOW

4 μs

HIGH

250 ns

SU;DAT

5 ns

HD;DAT

Rev. C | Page 6 of 32

ADM1067

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage on VH Pin 16 V
Voltage on VPx Pins 7 V
Voltage on VXx Pins −0.3 V to +6.5 V
Voltage on A0, A1 Pins −0.3 V to +7 V
Voltage on REFOUT Pin 5 V
Voltage on VDDCAP, VCCP Pins 6.5 V
Voltage on DACx Pins 6.5 V
Voltage on PDOx Pins 16 V
Voltage on SDA, SCL Pins 7 V
Voltage on GND, AGND, PDOGND, REFGND Pins −0.3 V to +0.3 V
Voltage on MUP and MDN Pins VDDCAP + 0.6 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature,

Soldering Vapor Phase, 60 sec

ESD Rating, All Pins 2000 V

Stresses above those listed under Absolute Maximum Ratings
ma

y cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

215°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

40-Lead LFCSP 25 °C/W
48-Lead TQFP 50 °C/W

ESD CAUTION

Rev. C | Page 7 of 32

ADM1067

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

V

www.BDTIC.com/ADI

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND40VDDCAP39MDN38MUP37SDA36SCL35A134A033VCCP32PDOGND

X1

1

PIN 1
INDICATOR

2

X2

X3

3

X4

4

X5

5

6

P1

7

P2

P3

8

P4

9

VH

10

11

AGND

NC = NO CONNECT

12NC13

REFGND

ADM1067

TOP VIEW

(Not to Scale)

14

DAC115DAC216DAC317DAC418DAC519DAC6

REFOUT

Figure 3. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

LFCSP1TQFP

13

1, 12, 13, 16,

Mnemonic

NC No Connection.
24, 25, 36,
37, 48

1 to 5 2 to 6

6 to 9 7 to 10

VX1 to VX5

Xx)

(V

VP1 to VP4

(VPx)

10 11 VH

11 14 AGND
12 15 REFGND

2

2

14 17 REFOUT

15 to 20 18 to 23

21 to 30 26 to 35

31 38 PDOGND

DAC1 to

AC6

D

PDO10 to

O1

PD

2

32 39 VCCP

33 40 A0
34 41 A1
35 42 SCL
36 43 SDA
37 44 MUP

NC48GND47VDDCAP46MDN45MUP44SDA43SCL42A141A040VCCP39PDOGND38NC

NC

31

PDO1

30

29

PDO2

PDO3

28

PDO4

27

PDO5

26

25

PDO6

24

PDO7

PDO8

23

PDO9

22

PDO10

21

20

04635-003

1

X1

X2

X3

X4

X5

P1

P2

P3

P4

VH

NC

NC = NO CONNECT

PIN 1

2

INDICATOR

3

4

5

6

7

8

9

10

11

12

13

14

NC

AGND

15NC16

REFGND

ADM1067

TOP VIEW

(Not to Scale)

17

DAC118DAC219DAC320DAC421DAC522DAC6

REFOUT

23NC24

37

NC

36

PDO1

35

PDO2

34

PDO3

33

32

PDO4

31

PDO5

30

PDO6

29

PDO7

28

PDO8

27

PDO9

26

PDO10

NC

25

04635-004

Figure 4. TQFP Pin Configuration

Description

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to

1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input

attenuation on a potential divider connected to these pins, the output of which connects to a
supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from 1.25 V to 3.00 V, and
from 0.573 V to 1.375 V.

High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.

Ground Return for Input Attenuators.
Ground Return for On-Chip Reference Circuits.
Reference Output, 2.048 V. Note that the capacitor must be connected between this pin and

REFGND. A 10 μF capacitor is recommended for this purpose.
Voltage Output DACs. These pins default to high impedance at power-up.

Programmable Output Drivers.

Ground Return for Output Drivers.
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin

and GND. A 10 μF capacitor is recommended for this purpose.
Logic Input. This pin sets the seventh bit of the SMBus interface address.
Logic Input. This pin sets the sixth bit of the SMBus interface address.
SMBus Clock Pin. Bidirectional open drain requires external resistive pull-up.
SMBus Data Pin. Bidirectional open drain requires external resistive pull-up.
Digital Input. Forces DACs to their lowest value, c

ausing the voltage at the feedback node to drop.

This is compensated for by an increase in the supply output voltage, thus margining up.

Rev. C | Page 8 of 32

ADM1067

www.BDTIC.com/ADI

Pin No.

LFCSP1TQFP

38 45 MDN

39 46 VDDCAP

40 47 GND

1

Note that the LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.

2

In a typical application, all ground pins are connected together.

Mnemonic Description

Digital Input. Forces DACs to their highest value, causing the v
This is compensated for by a decrease in the supply output voltage, thus margining down.

Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of 4.75 V.
Note tha

2

recommended for this purpose.
Supply Ground.

t the capacitor must be connected between this pin and GND. A 10 μF capacitor is

oltage at the feedback node to rise.

Rev. C | Page 9 of 32

ADM1067

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

180

160

140

120

100

(µA)

80

VP1

I

60

40

20

0

0123456

V

(V)

VP1

Figure 8. I

vs. V

VP1

(VP1 Not as Supply)

VP1

04635-053

(V)

VDDCAP

V

6

5

4

3

2

1

0

0654321

Figure 5. V

V

VP1

VDDCAP

(V)

vs. V

04635-050

VP1

6

5

4

(V)

3

VDDCAP

V

2

1

0

01

Figure 6. V

5.0

4.5

4.0

3.5

3.0

2.5

(mA)

VP1

I

2.0

1.5

1.0

0.5

0

0123456

Figure 7. I

VP1

vs. V

VVH (V)

VDDCAP

V

VP1

VP1

vs. VVH

(V)

(VP1 as Supply)

61412108642

04635-051

04635-052

(mA)

VH

I

350

300

250

200

(µA)

VH

150

I

100

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

0161412108642

50

0

0654321

Figure 9. I

Figure 10. I

VVH (V)

vs. VVH (VH as Supply)

VH

VVH (V)

vs. V

(VH Not as Supply)

VH

VH

04635-054

04635-055

Rev. C | Page 10 of 32