ANALOG DEVICES ADM1066 Service Manual

Super Sequencer with Margining Control

A

www.BDTIC.com/ADI

FEATURES

Complete supervisory and sequencing solution for up to

10 supplies

10 supply fault detectors enable supervision of supplies to

<0.5% accuracy at all voltages at 25°C
<1.0% accuracy across all voltages and temperatures

5 selectable input attenuators allow supervision of supplies to

14.4 V on VH
6 V on VP1 to VP4 (VPx)

5 dual-function inputs, VX1 to VX5 (VXx)

High impedance input to supply fault detector with

thresholds between 0.573 V and 1.375 V

General-purpose logic input

10 programmable driver outputs, PDO1 to PDO10 (PDOx)

Open-collector with external pull-up
Push/pull output, driven to VDDCAP or VPx
Open collector with weak pull-up to VDDCAP or VPx
Internally charge-pumped high drive for use with external

N-FET (PDO1 to PDO6 only)

Sequencing engine (SE) implements state machine control of

PDO outputs
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE

Program software control of sequencing through SMBus
Complete voltage-margining solution for 6 voltage rails
6 voltage output 8-bit DACs (0.300 V to 1.551 V) allow voltage

adjustment via dc-to-dc converter trim/feedback node
12-bit ADC for readback of all supervised voltages
2 auxiliary (single-ended) ADC inputs
Reference input (REFIN) has 2 input options

Driven directly from 2.048 V (±0.25%) REFOUT pin

More accurate external reference for improved ADC

performance

Device powered by the highest of VPx, VH for improved

redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPx = 1.2 V
Available in 40-lead, 6 mm × 6 mm LFCSP and

48-lead, 7 mm × 7 mm TQFP packages

For more information about the ADM1066 register map,

refer to the AN-698 Application Note at

www.analog.com.

and Auxiliary ADC Inputs

ADM1066

FUNCTIONAL BLOCK DIAGRAM

V

OUT

DAC

DAC6

SDA SCL A1 A0

SMBus

INTERFACE

EEPROM

CONFIGURABLE

OUTPUT

DRIVERS

(HV CAPABLE O F

DRIVING GATES

OF N-FET)

CONFIGURABLE

OUTPUT

DRIVERS

(LV CAPABLE

OF DRIVING

LOGIC SIGNALS)

VDD

ARBITRATOR

GND

VCCP

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PDO9

PDO10

PDOGND

VDDCAP

REFOUTREFINAUX2AUX1 REFGND

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

GND

ADM1066

12-BIT

MUX

SAR ADC

CLOSED-LOOP
MARGINI NG SYSTEM

DUAL-

FUNCTION

INPUTS

(LOGIC INPUTS

OR

SFDs)

PROGRAMMABLE

RESET

GENERATORS

(SFDs)

VH

V

V

OUT

DAC

DAC2

V

OUT

DAC

DAC3

OUT

DAC

DAC1

SEQUENCING

V

OUT

DAC

DAC4

ENGINE

V

OUT

DAC

DAC5

VREF

Figure 1.

APPLICATIONS

Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies

GENERAL DESCRIPTION

The ADM1066 Super Sequencer® is a configurable supervisory/
sequencing device that offers a single-chip solution for supply
monitoring and sequencing in multiple-supply systems. In addition
to these functions, the ADM1066 integrates a 12-bit ADC and
six 8-bit voltage output DACs. These circuits can be used to
implement a closed-loop margining system that enables supply
adjustment by altering either the feedback node or reference of
a dc-to-dc converter using the DAC outputs.

Supply margining can be performed with a minimum of external
components. The margining loop can be used for in-circuit testing
of a board during production (for example, to verify board func­tionality at −5% of nominal supplies), or it can be used dynamically
to accurately control the output voltage of a dc-to-dc converter.

04609-001

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2004–2008 Analog Devices, Inc. All rights reserved.

ADM1066

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TABLE OF CONTENTS

Features .............................................................................................. 1

Functional Block Diagram .............................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 3

Detailed Block Diagram .................................................................. 4

Specifications ..................................................................................... 5

Absolute Maximum Ratings ............................................................ 8

Thermal Resistance ...................................................................... 8

ESD Caution .................................................................................. 8

Pin Configurations and Function Descriptions ........................... 9

Typical Performance Characteristics ........................................... 11

Powering the ADM1066 ................................................................ 14

Inputs ................................................................................................ 15

Supply Supervision ..................................................................... 15

Programming the Supply Fault Detectors ............................... 15

Input Comparator Hysteresis .................................................... 15

Input Glitch Filtering ................................................................. 16

Supply Supervision with VXx Inputs ....................................... 16

VXx Pins as Digital Inputs ........................................................ 16

Outputs ............................................................................................ 17

Supply Sequencing Through Configurable Output Drivers . 17

Default Output Configuration .................................................. 17

Sequencing Engine ......................................................................... 18

Overview ...................................................................................... 18

Warnings ...................................................................................... 18

SMBus Jump (Unconditional Jump) ........................................ 18

Sequencing Engine Application Example ............................... 19

Fault and Status Reporting ........................................................ 20

Voltage Readback............................................................................ 21

Supply Supervision with the ADC ........................................... 21

Supply Margining ........................................................................... 22

Overview ..................................................................................... 22

Open-Loop Supply Margining ................................................. 22

Closed-Loop Supply Margining ............................................... 22

Writing to the DACs .................................................................. 23

Choosing the Size of the Attenuation Resistor ....................... 23

DAC Limiting and Other Safety Features ............................... 23

Applications Diagram .................................................................... 24

Communicating with the ADM1066 ........................................... 25

Configuration Download at Power-Up ................................... 25

Updating the Configuration ..................................................... 25

Updating the Sequencing Engine ............................................. 26

Internal Registers ........................................................................ 26

EEPROM ..................................................................................... 26

Serial Bus Interface ..................................................................... 26

SMBus Protocols for RAM and EEPROM .............................. 28

Write Operations ........................................................................ 28

Read Operations ......................................................................... 30

Outline Dimensions ....................................................................... 31

Ordering Guide .......................................................................... 31

Rev. D | Page 2 of 32

ADM1066

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REVISION HISTORY

5/08—Rev. C to Rev. D

Changes to Powering the ADM1066 Section .............................. 14

Changes to Table 5 .......................................................................... 15

Changes to Default Output Configuration Section .................... 17

Changes to Sequence Detector Section ........................................ 19

Changes to Configuration Download at Power-Up Section ..... 25

Changes to Table 11 ........................................................................ 26

Changes to Figure 36 ...................................................................... 27

Changes to Figure 37 ...................................................................... 28

Changes to Figure 46 and Error Correction Section .................. 30

Changes to Ordering Guide ........................................................... 31

11/06—Rev. B to Rev. C

Updated Format .................................................................. Universal

Changes to Features .......................................................................... 1

Changes to Figure 2 ........................................................................... 3

Changes to Buffered Voltage Output DACs .................................. 5

Changes to Table 2 ............................................................................ 7

Changes to Table 6 .......................................................................... 14

Changes to Programming the Supply Fault Detectors Section . 14

Changes to Table 9 .......................................................................... 22

Changes to Figure 36 and Figure 37 ............................................. 29

5/06—Rev. A to Rev. B

Changes to Features Section ............................................................ 1

Changes to Table 1 ............................................................................ 5

Changes to Table 2 ............................................................................ 8

Changes to Table 3 .......................................................................... 10

Added Table 4 .................................................................................. 10

Added Default Output Configuration Section ............................ 19

Changes to Fault Reporting Section ............................................. 19

Added Table 11 ................................................................................ 30

Changes to Ordering Guide ........................................................... 36

1/05—Rev. 0 to Rev. A

Changes to Figure 1 .......................................................................... 1

Changes to Absolute Maximum Ratings Section ......................... 8

Change to Supply Sequencing Through Configurable

Output Drivers Section .................................................................. 16

Changes to Figure 33 ...................................................................... 23

Change to Table 10 .......................................................................... 32

10/04—Revision 0: Initial Version

Rev. D | Page 3 of 32

ADM1066

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The device also provides up to 10 programmable inputs for moni­toring undervoltage faults, overvoltage faults, or out-of-window
faults on up to 10 supplies. In addition, 10 programmable outputs
can be used as logic enables. Six of these programmable outputs
can also provide up to a 12 V output for driving the gate of an N­FET that can be placed in the path of a supply.

The logical core of the device is a sequencing engine. This state
machine-based construction provides up to 63 different states.

DETAILED BLOCK DIAGRAM

REFOUTREFIN

AUX1AUX2 REFGND

This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.

The device is controlled via configuration data that can be
programmed into an EEPROM. The entire configuration can
be programmed using an intuitive GUI-based software package
provided by Analog Devices, Inc.

SDA SCL A1 A0

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

AGND

VDDCAP

VH

SELECTABLE
ATTENUATOR

SELECTABLE
ATTENUATOR

VDD

ARBITRATOR

ADM1066

SAR ADC

GPI SIG NAL

CONDITIONING

GPI SIG NAL

CONDITIONING

REG 5.25V

CHARGE PUMP

12-BIT

SFD

SFD

SFD

SFD

VREF

V

OUT

DAC

INTERFACE

CONTROLL ER

SEQUEN CING

ENGINE

SMBus

DEVICE

CONFIGURABL E

OUTPUT DRIVER

CONFIGURABL E

OUTPUT DRIVER

CONFIGURABL E

OUTPUT DRIVER

CONFIGURABL E

OUTPUT DRIVER

(HV)

(HV)

(LV)

(LV)

OSC

EEPROM

V

OUT

DAC

PDO1

PDO2

PDO3

PDO4

PDO5

PDO6

PDO7

PDO8

PDO9

PDO10

PDOGND

GND DAC2 DAC3 DAC4 DAC5

VCCP

Figure 2. Detailed Block Diagram

Rev. D | Page 4 of 32

DAC1

DAC6

04609-002

ADM1066

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SPECIFICATIONS

VH = 3.0 V to 14.4 V1, VPx = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY ARBITRATION

VH, VPx 3.0 V Minimum supply required on one of VPx, VH
VPx 6.0 V Maximum VDDCAP = 5.1 V, typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
C

10 μF Minimum recommended decoupling capacitance

VDDCAP

POWER SUPPLY

Supply Current, IVH, I
Additional Currents

All PDO FET Drivers On 1 mA

Current Available from

VDDCAP
DAC Supply Currents 2.2 mA Six DACs on with 100 μA maximum load on each
ADC Supply Current 1 mA Running round-robin loop
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V

SUPPLY FAULT DETECTORS

VH Pin

Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges

High Range 6 14.4 V
Midrange 2.5 6 V

VPx Pins

Input Impedance 52 kΩ
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges

Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error

VXx Pins

Input Impedance 1 MΩ
Detection Range

Ultralow Range 0.573 1.375 V No input attenuation error

Absolute Accuracy ±1 %

Threshold Resolution 8 Bits
Digital Glitch Filter 0 μs Minimum programmable filter length
100 μs Maximum programmable filter length

ANALOG-TO-DIGITAL CONVERTER

Signal Range 0 V

Input Reference Voltage on

REFIN Pin, V
Resolution 12 Bits
INL ±2.5 LSB Endpoint corrected, V
Gain Error ±0.05 % V

REFIN

4.2 6 mA VDDCAP = 4.75 V, PDO1 to PDO10 off, DACs off, ADC off

VPx

VDDCAP = 4.75 V, PDO1 to PDO6 loaded with 1 μA each,
PDO7 to PDO10 off

2 mA

V

REFIN

2.048 V

Maximum additional load that can be drawn from all PDO
pull-ups to VDDCAP

VREF error + DAC nonlinearity + comparator offset error + input
attenuation error

The ADC can convert signals presented to the VH, VPx, and VXx
pins; VPx and VH input signals are attenuated depending on the
selected range; a signal at the pin corresponding to the selected
range is from 0.573 V to 1.375 V at the ADC input

= 2.048 V

REFIN

= 2.048 V

REFIN

Rev. D | Page 5 of 32

ADM1066

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Parameter Min Typ Max Unit Test Conditions/Comments

Conversion Time 0.44 ms One conversion on one channel
84 ms All 12 channels selected, 16× averaging enabled
Offset Error ±2 LSB V
Input Noise 0.25 LSB

Direct input (no attenuator)

rms

AUX1, AUX2 Input Impedance 1 MΩ

BUFFERED VOLTAGE OUTPUT DACs

Resolution 8 Bits
Code 0x7F Output Voltage

Range 1 0.592 0.6 0.603 V
Range 2 0.796 0.8 0.803 V
Range 3 0.996 1 1.003 V

Range 4 1.246 1.25 1.253 V
Output Voltage Range 601.25 mV Same range, independent of center point
LSB Step Size 2.36 mV
INL ±0.75 LSB Endpoint corrected
DNL ±0.4 LSB
Gain Error 1 %
Maximum Load Current (Source) 100 μA
Maximum Load Current (Sink) 100 μA
Maximum Load Capacitance 50 pF
Settling Time to 50 pF Load 2 μs
Load Regulation 2.5 mV Per mA
PSRR 60 dB DC

40 dB 100 mV step in 20 ns with 50 pF load
REFERENCE OUTPUT

Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current, I

0.25 mV Sinking current, I
Minimum Load Capacitance 1 μF Capacitor required for decoupling, stability
PSRR 60 dB DC

PROGRAMMABLE DRIVER OUTPUTS

High Voltage (Charge-Pump)

Mode (PDO1 to PDO6)
Output Impedance 500 kΩ
V

11 12.5 14 V IOH = 0 μA

OH

V

10.5 12 13.5 V IOH = 1 μA

OH

2

V

8 10 13.5 V IOH = 7 μA

OH

I

20 μA 2 V < V

OUTAVG

Standard (Digital Output) Mode

(PDO1 to PDO10)
VOH 2.4 V VPU (pull-up to VDDCAP or VPx) = 2.7 V, IOH = 0.5 mA

4.5 V VPU to VPx = 6.0 V, IOH = 0 mA
V

− 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA

PU

VOL 0 0.50 V IOL = 20 mA

2

I

20 mA Maximum sink current per PDOx pin

OL

2

I

60 mA Maximum total sink for all PDOx pins

SINK

R

16 20 29 kΩ Internal pull-up

PULL-UP

I

SOURCE

Three-State Output Leakage

2

(VPx)

2 mA

10 μA V

Current

Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock

= 2.048 V

REFIN

Six DACs are individually selectable for centering on one of four
output voltage ranges

= −100 μA

DACxMAX

= 100 μA

DACxMAX

< 7 V

OH

Current load on any VPx pull-ups, that is, total source current
available through any number of PDO pull-up switches
configured onto any one VPx pin

= 14.4 V

PDO

Rev. D | Page 6 of 32

ADM1066

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Parameter Min Typ Max Unit Test Conditions/Comments

DIGITAL INPUTS (VXx, A0, A1)

Input High Voltage, VIH 2.0 V Maximum VIN = 5.5 V
Input Low Voltage, VIL 0.8 V Maximum VIN = 5.5 V
Input High Current, IIH −1 μA VIN = 5.5 V
Input Low Current, IIL 1 μA VIN = 0 V
Input Capacitance 5 pF
Programmable Pull-Down

Current, I

PULL-DOWN

SERIAL BUS DIGITAL INPUTS

20 μA VDDCAP = 4.75 V, T

(SDA, SCL)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, V

2

0.4 V I

OL

= −3.0 mA

OUT

SERIAL BUS TIMING

Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Stop Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t

400 kHz

SCLK

4.7 μs

BUF

4.7 μs

SU;STA

4 μs

SU;STO

4 μs

HD;STA

4.7 μs

LOW

4 μs

HIGH

SCL, SDA Rise Time, tR 1000 μs
SCL, SDA Fall Time, tF 300 μs
Data Setup Time, t
Data Hold Time, t

250 ns

SU;DAT

5 ns

HD;DAT

Input Low Current, IIL 1 μA VIN = 0

SEQUENCING ENGINE TIMING

State Change Time 10 μs

1

At least one of the VH, VPx pins must be ≥3.0 V to maintain the device supply on VDDCAP.

2

Specification is not production tested but is supported by characterization data at initial product release.

= 25°C, if known logic state is required

A

Rev. D | Page 7 of 32

ADM1066

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ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Voltage on VH Pin 16 V
Voltage on VPx Pins 7 V
Voltage on VXx Pins −0.3 V to +6.5 V
Voltage on AUX1, AUX2 Pins −0.3 V to +5 V
Voltage on A0, A1 Pins −0.3 V to +7 V
Voltage on REFIN, REFOUT Pins 5 V
Voltage on VDDCAP, VCCP Pins 6.5 V
Voltage on DACx Pins 6.5 V
Voltage on PDOx Pins 16 V
Voltage on SDA, SCL Pins 7 V
Voltage on GND, AGND, PDOGND, REFGND Pins −0.3 V to +0.3 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature,

Soldering Vapor Phase, 60 sec

ESD Rating, All Pins 2000 V

215°C

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA Unit

40-Lead LFCSP 25 °C/W
48-Lead TQFP 50 °C/W

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. D | Page 8 of 32

ADM1066

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

GND40VDDCAP39AUX138AUX237SDA36SCL35A134A033VCCP32PDOGND

1

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

VH

NC = NO CONNECT

PIN 1
INDICATOR

2

3

4

5

6

7

8

9

10

11

12

AGND

REFGND

13

REFIN

ADM1066

TOP VIEW

(Not to Scale)

14

DAC115DAC216DAC317DAC418DAC519DAC6

REFOUT

31

30

PDO1

PDO2

29

PDO3

28

PDO4

27

26

PDO5

25

PDO6

PDO7

24

PDO8

23

PDO9

22

21

PDO10

20

04609-003

Figure 3. LFCSP Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

1

TQFP

1, 12, 13,

Mnemonic

NC No Connection.

Description LFCSP

24, 25, 36,
37, 48

1 to 5 2 to 6 VX1 to VX5 (VXx)

High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to

1.375 V. Alternatively, these pins can be used as general-purpose digital inputs.

6 to 9 7 to 10 VP1 to VP4 (VPx)

Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the
input attenuation on a potential divider connected to these pins, the output of which connects
to a supply fault detector. These pins allow thresholds from 2.5 V to 6.0 V, from 1.25 V to 3.00 V,
and from 0.573 V to 1.375 V.

10 11 VH

High Voltage Input to Supply Fault Detectors. Two input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a

supply fault detector. This pin allows thresholds from 6.0 V to 14.4 V and from 2.5 V to 6.0 V.
11 14 AGND
12 15 REFGND
13 16 REFIN

2

2

Ground Return for On-Chip Reference Circuits.

Ground Return for Input Attenuators.

Reference Input for ADC. Nominally, 2.048 V. This pin must be driven by a reference voltage.

The on-board reference can be used by connecting the REFOUT pin to the REFIN pin.
14 17 REFOUT

Reference Output, 2.048 V. Typically connected to REFIN. Note that the capacitor must be

connected between this pin and REFGND. A 10 μF capacitor is recommended for this purpose.
15 to 20 18 to 23 DAC1 to DAC6
21 to 30 26 to 35 PDO10 to PDO1
31 38 PDOGND

2

Ground Return for Driver Outputs.

32 39 VCCP

Voltage Output DACs. These pins default to high impedance at power-up.

Programmable Driver Outputs.

Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this

pin and GND. A 10 μF capacitor is recommended for this purpose.
33 40 A0
34 41 A1
35 42 SCL
36 43 SDA

Logic Input. This pin sets the seventh bit of the SMBus interface address.

Logic Input. This pin sets the sixth bit of the SMBus interface address.

SMBus Clock Pin. Bidirectional, open-drain pin that requires external resistive pull-up.

SMBus Data Pin. Bidirectional, open-drain pin that requires external resistive pull-up.
37, 38 44, 45 AUX2, AUX 1 Auxiliary, Single-Ended ADC Inputs.

NC48GND47VDDCAP46AUX145AUX244SDA43SCL42A141A040VCCP39PDOGND38NC

NC

1

VX1

VX2

VX3

VX4

VX5

VP1

VP2

VP3

VP4

VH

NC

NC = NO CONNECT

PIN 1

2

INDICATOR

3

4

5

6

7

8

9

10

11

12

13

14

NC

AGND

Figure 4. TQFP Pin Configuration

15

REFGND

ADM1066

TOP VIEW

(Not to Scale)

16

17

DAC118DAC219DAC320DAC421DAC522DAC6

REFIN

REFOUT

23NC24

37

NC

36

PDO1

35

PDO2

34

PDO3

33

32

PDO4

31

PDO5

30

PDO6

29

PDO7

28

PDO8

27

PDO9

26

PDO10

NC

25

04609-004

Rev. D | Page 9 of 32

ADM1066

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Pin No.

LFCSP1TQFP

39 46 VDDCAP

40 47 GND

1

The LFCSP has an exposed pad on the bottom. This pad is a no connect (NC). If possible, this pad should be soldered to the board for improved mechanical stability.

2

In a typical application, all ground pins are connected together.

Mnemonic Description

Device Supply Voltage. Linearly regulated from the highest of the VPx, VH pins to a typical of

4.75 V. Note that the capacitor must be connected between this pin and GND. A 10 μF capacitor

2

Supply Ground.

is recommended for this purpose.

Rev. D | Page 10 of 32