ANALOG DEVICES ADM1065 Service Manual
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FEATURES
Complete supervisory and sequencing solution for up to
10 supplies
10 supply fault detectors enable supervision of supplies to
better than 1% accuracy
5 selectable input attenuators allow supervision:
Supplies up to 14.4 V on VH
Supplies up to 6 V on VP1–4
5 dual-function inputs, VX1–5:
High impedance input to supply fault detector with
thresholds between 0.573 V and 1.375 V
General-purpose logic input
10 programmable output drivers (PDO1–10):
Open collector with external pull-up
Push/pull output, driven to VDDCAP or VPn
Open collector with weak pull-up to VDDCAP or VPn
Internally charge-pumped high drive for use with external
N-FET (PDO1–6 only)
Sequencing engine (SE) implements state machine control of
PDO outputs:
State changes conditional on input events
Enables complex control of boards
Power-up and power-down sequence control
Fault event handling
Interrupt generation on warnings
Watchdog function can be integrated in SE
Program software control of sequencing through SMBus
Device powered by the highest of VP1–4, VH for improved
redundancy
User EEPROM: 256 bytes
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VH, VPn = 1.2 V
40-lead 6 mm × 6 mm LFCSP and
48-lead 7 mm × 7 mm TQFP packages
Super Sequencer™ and Monitor
ADM1065
FUNCTIONAL BLOCK DIAGRAM
REFOUTREFIN REFGND
VREF
ADM1065
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
DDCA
DUAL-
FUNCTION
INPUTS
(LOGIC INPUTS
OR
SFDs)
PROGRAMMABLE
RESET
GENERATORS
(SFDs)
VDD
ARBITRATOR
VCCP
SEQUENCING
ENGINE
GND
Figure 1.
APPLICATIONS
Central office systems
Servers/routers
Multivoltage system line cards
DSP/FPGA supply sequencing
In-circuit testing of margined supplies
GENERAL DESCRIPTION
The ADM1065 is a configurable supervisory/sequencing device
that offers a single-chip solution for supply monitoring and
sequencing in multiple supply systems.
SDA SCL A1 A0
SMBus
INTERFACE
EEPROM
CONFIGURABLE
OUTPUT
DRIVERS
(HV CAPABLE
OF DRIVING
GATES OF
N-CHANNEL FET)
CONFIGURABLE
OUTPUT
DRIVERS
(LV CAPABLE
OF DRIVING
LOGIC SIGNALS)
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
04634-001
(continued on Page 3)
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2005 Analog Devices, Inc. All rights reserved.
www.analog.com
ADM1065
TABLE OF CONTENTS
General Description......................................................................... 3
SMBus Jump/Unconditional Jump .......................................... 15
Specifications..................................................................................... 4
Pin Configurations and Function Descriptions ........................... 6
Absolute Maximum Ratings............................................................ 7
Thermal Characteristics .............................................................. 7
ESD Caution.................................................................................. 7
Typical Performance Characteristics............................................. 8
Powering the ADM1065................................................................ 10
Inputs................................................................................................ 11
Supply Supervision .....................................................................11
Programming the Supply Fault Detectors............................... 11
Input Comparator Hysteresis.................................................... 12
Input Glitch Filtering ................................................................. 12
Supply Supervision with VXn Inputs....................................... 12
VXn Pins as Digital Inputs........................................................ 13
Outputs ............................................................................................ 14
Sequencing Engine Application Example ............................... 16
Sequence Detector...................................................................... 17
Monitoring Fault Detector ........................................................ 17
Timeout Detector ....................................................................... 17
Fault Reporting ........................................................................... 17
Applications Diagram .................................................................... 18
Communicating with the ADM1065........................................... 19
Configuration Download at Power-Up................................... 19
Updating the Configuration ..................................................... 19
Updating the Sequencing Engine............................................. 20
Internal Registers........................................................................ 20
EEPROM ..................................................................................... 20
Serial Bus Interface..................................................................... 20
SMBus Protocols for RAM and EEPROM.............................. 22
Write Operations........................................................................ 22
Supply Sequencing through Configurable Output Drivers .. 14
Sequencing Engine......................................................................... 15
Overview...................................................................................... 15
Wa r ni n g s ...................................................................................... 15
REVISION HISTORY
1/05—Rev. 0 to Rev. A
Changes to Specifications Section.................................................. 3
Change to Absolute Maximum Ratings Section........................... 7
Change to Supply Sequencing through Configurable
Output Drivers Section............................................................... 14
Changes to Figure 24...................................................................... 18
Change to Table 8 ........................................................................... 28
10/04—Revision 0: Initial Version
Read Operations......................................................................... 24
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 26
Rev. A | Page 2 of 28
ADM1065
GENERAL DESCRIPTION
(continued from Page 1)
The device provides up to ten programmable inputs for
monitoring under, over, or out-of-window faults on up to ten
supplies. In addition, ten programmable outputs can be use d as
logic enables. Six of them can also provide up to a 12 V output
for driving the gate of an N-channel FET, which can be placed
in the path of a supply.
The logical core of the device is a sequencing engine. This statemachine-based construction provides up to 63 different states.
REFOUTREFIN REFGND
This design enables very flexible sequencing of the outputs,
based on the condition of the inputs.
The device is controlled via configuration data that can be
programmed into an EEPROM. The whole configuration can be
programmed using an intuitive GUI-based software package
provided by ADI.
SDA SCL A1 A0
VX1
VX2
VX3
VX4
VX5
VP1
VP2
VP3
VP4
VH
AGND
VDDCAP
ADM1065
SELECTABLE
ATTENUATOR
SELECTABLE
ATTENUATOR
VDD
ARBITRATOR
GPI SIGNAL
CONDITIONING
SFD
GPI SIGNAL
CONDITIONING
SFD
SFD
SFD
VREF
INTERFACE
CONTROLLER
SEQUENCING
ENGINE
REG 5.25V
CHARGE PUMP
SMBus
DEVICE
CONFIGURABLE
CONFIGURABLE
CONFIGURABLE
CONFIGURABLE
EEPROM
O/P DRIVER
(HV)
O/P DRIVER
(HV)
O/P DRIVER
(LV)
O/P DRIVER
(LV)
OSC
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
PDOGND
GND
VCCP
04634-002
Figure 2. Detailed Block Diagram
Rev. A | Page 3 of 28
ADM1065
SPECIFICATIONS
VH = 3.0 V to 14.4 V1, VPn = 3.0 V to 6.0 V1, TA = −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VH, VPn 3.0 V Minimum supply required on one of VPn, VH
VP 6.0 V Maximum VDDCAP = 5.1 V, typical
VH 14.4 V VDDCAP = 4.75 V
VDDCAP 2.7 4.75 5.4 V Regulated LDO output
C
VDDCAP
POWER SUPPLY
Supply Current, IVH, I
Additional Currents
All PDO FET Drivers On 1 mA
Current Available from VDDCAP 2 mA
EEPROM Erase Current 10 mA 1 ms duration only, VDDCAP = 3 V
SUPPLY FAULT DETECTORS
VH Pin
Input Attenuator Error ±0.05 % Midrange and high range
Detection Ranges
High Range 6 14.4 V
Midrange 2.5 6 V
VPn Pins
Input Attenuator Error ±0.05 % Low range and midrange
Detection Ranges
Midrange 2.5 6 V
Low Range 1.25 3 V
Ultralow Range 0.573 1.375 V No input attenuation error
VX Pins
Input Impedance 1 MΩ
Detection Ranges
Ultralow Range 0.573 1.375 V No input attenuation error
Absolute Accuracy ±1 %
Threshold Resolution 8 Bits
Digital Glitch Filter 0 µs Minimum programmable filter length
100 µs Maximum programmable filter length
REFERENCE OUTPUT
Reference Output Voltage 2.043 2.048 2.053 V No load
Load Regulation −0.25 mV Sourcing current, I
0.25 mV Sinking current, I
Minimum Load Capacitance 1 µF Capacitor required for decoupling, stability
Load Regulation 2 mV Per 100 µA
PSRR 60 dB DC
VPn
10 µF Minimum recommended decoupling capacitance
4.2 6 mA VDDCAP = 4.75 V, PDO1–10 off
VDDCAP = 4.75 V, PDO1–6 loaded with 1 µA each,
PDO7–10 off
Maximum additional load that can be drawn from
all PDO pull-ups to VDDCAP
VREF error + DAC nonlinearity + comparator offset
error + input attenuation error
= −100 µA
DACnMAX
= 100 µA
DACnMAX
Rev. A | Page 4 of 28
ADM1065
Parameter Min Typ Max Unit Test Conditions/Comments
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode (PDO1–6)
Output Impedance 500 kΩ
V
OH
10.5 12 13.5 V IOH = 1 µA
I
OUTAVG
Standard (Digital Output) Mode (PDO1–10)
V
OH
4.5 V VPU to Vpn = 6.0 V, IOH = 0 mA
V
V
OL
2
I
OL
2
I
60 mA Maximum total sink for all PDOs
SINK
R
PULL-UP
I
(VPn)2 2 mA
SOURCE
Three-State Output Leakage Current 10 µA V
Oscillator Frequency 90 100 110 kHz All on-chip time delays derived from this clock
DIGITAL INPUTS (VXn, A0, A1)
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
IH
IL
IH
IL
Input Capacitance 5 pF
Programmable Pull-Down Current,
I
PULL-DOWN
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, V
Input Low Voltage, V
Output Low Voltage, V
IH
IL
2
0.4 V I
OL
SERIAL BUS TIMING
Clock Frequency, f
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
Input Low Current, I
SCLK
BUF
SU;STA
HD;STA
LOW
HIGH
r
f
SU;DAT
HD;DAT
IL
SEQUENCING ENGINE TIMING
State Change Time 10 µs
1
At least one of the VH, VP1-4 pins must be ≥3.0 V to maintain the device supply on VDDCAP.
2
Specification is not production tested, but is supported by characterization data at initial product release.
11 12.5 14 V IOH = 0
20 µA 2 V < V
OH
< 7 V
2.4 V VPU (pull-up to VDDCAP or VPN) = 2.7 V, IOH = 0.5 mA
− 0.3 V VPU ≤ 2.7 V, IOH = 0.5 mA
PU
0 0.50 V IOL = 20 mA
20 mA Maximum sink current per PDO pin
20 kΩ Internal pull-up
Current load on any VPn pull- ups, that is, total
source current available through any number of
PDO pull-up switches configured onto any one
= 14.4 V
PDO
2.0 V Maximum VIN = 5.5 V
0.8 V Maximum VIN = 5.5 V
−1 µA VIN = 5.5 V
1 µA VIN = 0
20 µA
VDDCAP = 4.75, T
= 25°C, if known logic state is
A
required
2.0 V
0.8 V
= −3.0 mA
OUT
400 kHz
4.7 µs
4.7 µs
4 µs
4.7 µs
4 µs
1000 µs
300 µs
250 ns
5 ns
1 µA VIN = 0
Rev. A | Page 5 of 28
ADM1065
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
GND40VDDCAP39NC38NC37SDA36SCL35A134A033VCCP32PDOGND
X1
1
PIN 1
X2
X3
X4
X5
P1
P2
P3
P4
VH
NC = NO CONNECT
INDICATOR
2
3
4
5
6
7
8
9
10
11
12NC13
AGND
REFGND
Figure 3. LFCSP Pin Configuration
ADM1065
TOP VIEW
(Not to Scale)
14NC15NC16NC17NC18NC19NC20
REFOUT
31
30
29
28
27
26
25
24
23
22
21
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO10
04634-003
NC
X1
X2
X3
X4
X5
P1
P2
P3
P4
VH
NC
NC = NO CONNECT
NC48GND47VDDCAP46NC45NC44SDA43SCL42A141A040VCCP39PDOGND38NC
1
PIN 1
2
INDICATOR
3
4
5
6
7
8
9
10
11
12
13
14
NC
ADM1065
TOP VIEW
(Not to Scale)
15NC16
17NC18NC19NC20NC21NC22NC23NC24
AGND
REFGND
REFOUT
Figure 4. TQFP Pin Configuration
37
NC
36
PDO1
35
PDO2
34
PDO3
33
32
PDO4
31
PDO5
30
PDO6
29
PDO7
28
PDO8
27
PDO9
26
PDO10
NC
25
04634-004
Table 2. Pin Function Descriptions
Pin No.
LFCSP TQFP
13, 15–
20, 37–38
1, 12–13, 16,
18–25, 36–37,
Mnemonic Description
NC No Connection.
44–45, 48
1–5 2–6 VX1–5
High Impedance Inputs to Supply Fault Detectors. Fault thresholds can be set from 0.573 V to 1.375 V.
Alternatively, these pins can be used as general-purpose digital inputs.
6–9 7–10 VP1–4
Low Voltage Inputs to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to these pins, the output of which connects to a supply
fault detector. These pins allow thresholds from 2.5 V to 6.0 V, 1.25 V to 3.00 V, and 0.573 V to 1.375 V.
10 11 VH
High Voltage Input to Supply Fault Detectors. Three input ranges can be set by altering the input
attenuation on a potential divider connected to this pin, the output of which connects to a supply
fault detector. This pin allows thresholds from 6.0 V to 14.4 V and 2.5 V to 6.0 V.
11 14 AGND Ground Return for Input Attenuators.
12 15 REFGND Ground Return for On-Chip Reference Circuits.
14 17 REFOUT 2.048 V Reference Output.
21–30 26–35 PDO10–1 Programmable Output Drivers.
31 38 PDOGND Ground Return for Output Drivers.
32 39 VCCP
Central Charge-Pump Voltage of 5.25 V. A reservoir capacitor must be connected between this pin
and GND.
33 40 A0 Logic Input. This pin sets the seventh bit of the SMBus interface address.
34 41 A1 Logic Input. This pin sets the sixth bit of the SMBus interface address.
35 42 SCL SMBus Clock Pin. Open-drain output requires external resistive pull-up.
36 43 SDA SMBus Data I/O Pin. Open-drain output requires external resistive pull-up.
39 46 VDDCAP Device Supply Voltage. Linearly regulated from the highest of the VP1–4, VH pins to a typical of 4.75 V.
40 47 GND Supply Ground.
Rev. A | Page 6 of 28
ADM1065
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Voltage on VH Pin 16 V
Voltage on VP Pins 7 V
Voltage on VX Pins −0.3 V to +6.5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering
Vapor Phase, 60 sec 215°C
ESD Rating, All Pins 2000 V
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
40-lead LFCSP package: θJA = 25°C/W.
48-lead TQFP package: θ
= 14.8°C/W.
JA
Rev. A | Page 7 of 28
ADM1065
TYPICAL PERFORMANCE CHARACTERISTICS
6
5
4
(V)
3
VDDCAP
V
2
1
0
0654321
Figure 5. V
V
VP1
VDDCAP
(V)
vs. V
VP1
6
5
4
(V)
3
VDDCAP
V
2
1
0
0161412108642
Figure 6. V
VVH (V)
VDDCAP
vs. V
VH
5.0
4.5
4.0
3.5
3.0
2.5
(mA)
VP1
I
2.0
1.5
1.0
0.5
0
0123456
Figure 7. I
V
(V)
VP1
vs. V
VP1
(VP1 as Supply)
VP1
04634-050
04634-051
04634-052
180
160
140
120
100
A)
µ
(
80
VP1
I
60
40
20
0
0123456
Figure 8. I
V
(V)
VP1
vs. V
VP1
(VP1 Not as Supply)
VP1
5.0
4.5
4.0
3.5
3.0
2.5
(mA)
VH
I
2.0
1.5
1.0
0.5
0
0161412108642
Figure 9. I
VVH (V)
vs. VVH (VH as Supply)
VH
350
300
250
200
(µA)
VH
150
I
100
50
0
0654321
Figure 10. I
VH
vs. V
VVH (V)
VH
(VH Not as Supply)
04634-053
04634-054
04634-055
Rev. A | Page 8 of 28
ADM1065
14
12
10
CHARGE PUMPED
PDO1
V
5.0
4.5
4.0
3.5
3.0
(V)
2.5
PDO1
V
2.0
1.5
1.0
0.5
8
6
4
2
0
0 15.012.510.07.55.02.5
0
0654321
Figure 12. V
Figure 11. V
VP1 = 3V
I
CURRENT (µA)
LOAD
(FET Drive Mode) vs. I
PDO1
I
(mA)
LOAD
(Strong Pull-Up VP) vs. I
PDO1
04634-056
LOAD
VP1 = 5V
04634-057
LOAD
4.5
4.0
3.5
3.0
2.5
(V)
2.0
PDO1
V
1.5
1.0
0.5
0
065040302010
Figure 13. V
VP1 = 3V
VP1 = 5V
I
(µA)
LOAD
(Weak Pull-Up to VP) vs. I
PDO1
2.058
2.053
2.048
REFOUT (V)
2.043
2.038
–40 –20 0 20 40 60 10080
TEMPERATURE (°C)
Figure 14. REFOUT vs. Temperature
LOAD
VP1 = 3.0V
VP1 = 4.75V
04634-058
0
04634-061
Rev. A | Page 9 of 28
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