Analog Devices ADM1060 b Datasheet
Communications System
FEATURES
Faults detected on 7 independent supplies
1 high voltage supply (2 V to 14.4 V)
4 positive voltage only supplies (2 V to 6 V)
2 positive/negative voltage supplies
(+2 V to +6 V and –2 V to –6 V)
Watchdog detector input—timeout delay programmable
from 200 ms to 12.8 sec
4 general-purpose logic inputs
Programmable logic block—combinatorial and sequencing
logic control of all inputs and outputs
9 programmable output drivers:
Open collector (external resistor required)
Open collector with internal pull-up to V
Fast internal pull-up to V
Open collector with internal pull-up to VPn
Fast internal pull-up to VPn
Internally charge-pumped high drive (for use with
external N-channel FETs—PDOs 1 to 4 only)
EEPROM—256 bytes of user EEPROM
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VPn, VH = 1 V
DD
APPLICATIONS
Central office systems
Servers
Infrastructure network boards
High density, multivoltage system cards
GENERAL DESCRIPTION
The ADM1060 is a programmable supervisory/sequencing
device that offers a single chip solution for multiple power
supply fault detection and sequencing in communications
systems.
In central offices, servers, and other infrastructure systems, a
common backplane dc supply is reduced to multiple board supplies using dc-to-dc converters. These multiple supplies are used
to power different sections of the board, such as 3.3 V logic
circuits, 5 V logic circuits, DSP core, and DSP I/O circuits. There
is usually a requirement that certain sections power up before
others; for example, a DSP core may need to power up before
the DSP I/O, or vice versa, to avoid damage, miscommunication,
or latch-up. The ADM1060 facilitates this, providing supply
DD
Supervisory/Sequencing Circuit
ADM1060
fault detection and sequencing/combinatorial logic for up to
seven independent supplies. The seven supply fault detectors
consist of one high voltage detector (up to +14.4 V), two bipolar
voltage detectors (up to +6 V or down to −6 V), and four positive low voltage detectors (up to +6 V). All of the detectors can
be programmed to detect undervoltage, overvoltage, or out-ofwindow (undervoltage or overvoltage) conditions. The inputs to
these supply fault detectors are via the VH (high voltage) pin,
VBn (positive or negative) pins, and VPn (positive only) pins.
Either the VH supply or one of the VPn supplies is used to
power the ADM1060 (whichever is highest). This ensures that
in the event of a supply failure, the ADM1060 is kept alive for as
long as possible, thus enabling a reliable fault flag to be asserted
and the system to be powered down in an ordered fashion.
Other inputs to the ADM1060 include a watchdog detector
(WDI) and four general-purpose inputs (GPIn). The watchdog
detector can be used to monitor a processor clock. If the clock
does not toggle (transition from low to high or from high to
low) within a programmable timeout period (up to 18 sec.), a
fail flag will assert. The four general-purpose inputs can be configured as logic buffers or to detect positive/negative edges and
to generate a logic pulse or level from those edges. Thus, the
user can input control signals from other parts of the system
(e.g., RESET or POWER_GOOD) to gate the sequencing of the
supplies supervised by the ADM1060.
The ADM1060 features nine programmable driver outputs
(PDOs). All nine outputs can be configured to be logic outputs,
which can provide multiple functions for the end user such as
RESET generation, POWER_GOOD status, enabling of LD Os,
and watchdog timeout assertion. PDOs 1 to 4 have the added
feature of being able to provide an internally charge-pumped
high voltage for use as the gate drive of an external N-channel
FET that could be placed in the path of one of the supplies
being supervised.
(continued on Page 3)
.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
ADM1060
TABLE OF CONTENTS
General Description ......................................................................... 3
PROGRAMMABLE DRIVER OUTPUTS ............................. 33
Specifications..................................................................................... 5
Absolute Maximum Ratings............................................................ 7
Typical Performance Characteristics ............................................. 8
Inputs................................................................................................ 11
SFD REGISTER NAMES........................................................... 14
SFD Register Bit Maps............................................................... 15
Programming .................................................................................. 21
Logic ................................................................................................. 22
PLBA REGISTER BIT MAPS ................................................... 28
Outputs ............................................................................................ 33
REVISION HISTORY
12/03—Data sheet changed from Rev. A to Rev. B
Changes to Specifications
Changes to Outputs section............................................................33
.............................................................................5
Status/Faults .................................................................................... 35
FAULT REGISTERS................................................................... 38
MASK REGISTERS.................................................................... 39
Programming.................................................................................. 40
WRITE OPERATIONS ............................................................. 44
READ OPERATIONS................................................................ 45
Pin Configuration and Functional Descriptions........................ 49
Outline Dimensions....................................................................... 50
Ordering Guide .......................................................................... 50
Updated Outline Dimensions.........................................................50
5/03—Data sheet changed from Rev. 0 to Rev. A.
Changes to Features.......................................................................... 1
Changes to Specifications................................................................ 5
Changes to Figure 1.......................................................................... 4
Changes to Absolute Maximum Ratings ....................................... 7
Changes to Figures 2, 8, 15–16..................................................8–10
Changes to Figure 17...................................................................... 11
Changes to Programmable Supply Fault Detectors section...... 11
Changes to Figure 18...................................................................... 12
Changes to Figure 19...................................................................... 13
Change to Table 9 ........................................................................... 15
Change to Table 14 ......................................................................... 16
Change to Table 19 ......................................................................... 17
Changes to Programmable Driver Outputs section................... 33
Change to Table 40 ......................................................................... 34
Changes to Figure 25–26 ............................................................... 43
Changes to Figure 37...................................................................... 47
Changes to Table 58........................................................................ 49
Changes to Ordering Guide section............................................. 50
Revision 0: Initial Version
Rev. B | Page 2 of 52
ADM1060
GENERAL DESCRIPTION
(continued from Page 1)
All of the inputs and outputs described previously are
controlled by the programmable logic block array (PLBA). This
is the logic core of the ADM1060. It is comprised of nine
macrocells, one for each PDO. These macrocells are essentially
just wide AND gates. Any/all of the inputs can be used as an
input to these macrocells. The output of a macrocell can also be
used as an input to any macrocell other than itself (an input to
itself would result in a nonterminating loop). The PLBA outputs
control the PDOs of the ADM1060 via delay blocks, where a
delay of 0 ms to 500 ms can be programmed on the rising
and/or the falling edge of the data. This results in a very flexible
sequencing ability. Thus, for instance, PDO1 can be
programmed so that it will not assert until the VP2, VP3, and
VP4 supplies are in tolerance; VB1 and VH have been in
tolerance for 200 ms; and PDO7 has already been asserted. A
simple sequencing operation would be to daisy-chain each PLB
output into the input of the next PLB such that PDO9 does not
assert until PDO8 asserts, which in turn does not assert until
PDO7 asserts, and so on.
All of the functional capability described here is programmable
through the industry-standard 2-wire bus (SMBus) provided.
Device settings can be written to EEPROM memory for automatic programming of the device on power-up. The EEPROM
is organized in 512 bytes, half of which are used to program all
of the functions on the ADM1060. The other 256 bytes of
EEPROM are for general-purpose system use such as date codes
and system ID. Read/write access to this is also via the 2-wire
interface. In addition, each output state can be directly overdriven from the serial interface, allowing a further level of
control, as in a system controlled soft power-down.
Rev. B | Page 3 of 52
ADM1060
V
VH
VP1
VP2
VP3
VP4
VB1
VB2
GPI1
GPI2
GPI3
GPI4
WDI
GND
CCP
8
9
10
11
12
13
14
28
27
26
25
24
6
7
ADM1060
HIGH SUPPLY
(14.4V)
FAULT DETECTOR
POSITIVE
SUPPLY FAULT
DETECTOR 1
POSITIVE
SUPPLY FAULT
DETECTOR 4
BIPOLAR
SUPPLY FAULT
DETECTOR 1
BIPOLAR
SUPPLY FAULT
DETECTOR 2
INPUT LOGIC
SIGNAL
CONDITION
WATCHDOG
FAULT
DETECTOR
VREF
INTERNAL
5.25V SUPPLY
PROGRAMMABLE
LOGIC BLOCK
ARRAY
(PLBA)
PLB
MACROCELL 1
PLB
MACROCELL 2
PLB
MACROCELL 3
PLB
MACROCELL 4
PLB
MACROCELL 5
PLB
MACROCELL 6
PLB
MACROCELL 7
PLB
MACROCELL 8
PLB
MACROCELL 9
PROGRAMMABLE
DELAY BLOCKS
PDB1
t
t
RISE
FALL
PDB2
t
t
RISE
FALL
PDB3
t
t
RISE
FALL
PDB4
t
RISEtFALL
PDB5
t
t
RISE
FALL
PDB6
t
t
RISE
FALL
PDB7
t
t
RISE
FALL
PDB8
t
t
RISE
FALL
PDB9
t
t
RISE
FALL
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
PDO1
15
PDO2
16
PDO3
17
PDO4
18
PDO5
19
20
PDO6
PDO7
21
PDO8
22
23
PDO9
REGULATED
5.25V SUPPLY
CHARGE PUMP
V
DD
ARBITRATOR
5
VDDCAP
SMBus INTERFACE
43
21
SCL
SDAA1SDA
WRITE ENABLE BUSES
A0
DATA, ADDRESS, AND
TO STORE CONTROL
INFORMATION LOCAL
TO FUNCTIONS
DEVICE
CONTROLLER
SMBus DATA
100kHz CLOCK
EEPROM
Figure 1. Functional Block Diagram
Rev. B | Page 4 of 52
ADM1060
SPECIFICATIONS
(VH = 4.75 V to 14.4 V, VPn = 3.0 V to 6.0 V,1 TA = −40°C to +85°C, unless otherwise noted.)
Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY ARBITRATION
VDDCAP 2.7 V Any VPn ≥ 3.0 V
2.7 V VH ≥ 4.75 V
4.75 5.1 V Any VPn = 6.0 V
4.75 5.1 V VH = 14.4 V
POWER SUPPLY
Supply Current, IDD 3 mA
5 mA
Additional Current Available
from VDDCAP
2
1 mA
SUPPLY FAULT DETECTORS
Input Impedance
VH Input 52 kΩ From VH to GND
VPn Inputs 52 kΩ From VPn to GND
VBn Inputs 190 kΩ From VBn to 2.25 V (internal reference)
52 kΩ From VBn to GND (positive mode)
30 kΩ From VBn to GND (negative mode)
Absolute Accuracy (VH, VPn, VBn Inputs) –2.5 +2.5 %
Calibrated Absolute Accuracy
3
VH, VPn Inputs –1.0 +1.0 %
VBn Inputs –1.5 +1.5 % Factory preprogrammed to specific thresholds
Glitch Filters (Digital) 0 100 µs
PROGRAMMABLE DRIVER OUTPUTS
High Voltage (Charge Pump) Mode
(PDOs 1 to 4)
Output Impedance, R
440 kΩ
OUT
VOH 11 12.5 14 V IOH = 0 µA
10.5 12 V IOH = 1 µA
I
Standard (Digital Output) Mode
20 µA 2 V < VOH < 7 V
OUTAVG
(PDOs 1 to 9)
VOH 2.4 V VPU (pull-up to VDDCAP or VPn) > 2.7 V, IOH = 1 mA
4.5 V VPU to VPn = 6.0 V, IOH = 0 mA
VPU – 0.3 V VPU ≤ 2.7 V, IOH = 1 mA
VOL 0.4 V IOL = 2 mA
1.2 V IOL = 10 mA
2.0 V IOL = 15 mA
I
R
I
2
20 mA Total sink current (PDO1–PDO9)
SINK
Weak Pull-Up 20 kΩ Internal pull-up
PULLUP-
2
SOURCE (VPn)
2 mA
Three-State Output Leakage Current 10 µA V
VDDCAP = 4.75 V, no PDO FET drivers on, no
loaded PDO pull-ups to VDDCAP
VDDCAP = 4.75 V, all PDO FET drivers on (loaded
with 1 µA), no PDO pull-ups to VDDCAP
Max additional load that can be drawn from PDO
pull-ups to VDDCAP
Factory preprogrammed to specific thresholds
See Figure 19. Eight timeout options between 0 µs
and 100 µs
Current load on any VPn pull-up (i.e., total source
current available through any number of PDO
pull-up switches configured on to any one)
= 14.4 V
PDO
Rev. B | Page 5 of 52
ADM1060
Parameter Min Typ Max Unit Test Conditions/Comments
DIGITAL INPUTS (GPI 1–4, WDI, A0, A1)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Input High Current, IIH –1 µA VIN = 5.5 V
Input Low Current, IIL 1 µA VIN = 0 V
Input Capacitance 10 pF
Programmable Pull-Down Current, I
SERIAL BUS DIGITAL INPUTS (SDA, SCL)
Input High Voltage, VIH 2.0 V
Input Low Voltage, VIL 0.8 V
Output Low Voltage, VOL 0.4 V I
PROGRAMMABLE DELAY BLOCK
Timeout 0 500 ms
WATCHDOG TIMER INPUT
Timeout 0 12.8 s Eight programmable timeout options
EEPROM RELIABILITY
Endurance
Data Retention
SERIAL BUS TIMING
Clock Frequency, f
5, 6
7
8
400 kHz See Figure 27
SCLK
Glitch Immunity, tSW 50 ns See Figure 27
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
4.7 µs See Figure 27
BUF
4.7 µs See Figure 27
SU;STA
4 µs See Figure 27
HD;STA
4.7 µs See Figure 27
LOW
4 µs See Figure 27
HIGH
SCL, SDA Rise Time, tr 1000 ns See Figure 27
SCL, SDA Fall Time, tf 300 µs See Figure 27
Data Setup Time, t
Data Hold Time, t
NOTES
1
At least one VPn must be ≥3.0 V if used as supply. VH must be ≥4.5 V if used as supply.
2
Specification is not production tested, but is supported by characterization data at initial product release.
3
1% threshold accuracy is only achievable on parts preprogrammed by Analog Devices. Contact ADM1060.program@analog.com for further details.
4
Logic inputs will accept input high voltages up to 5.5 V even when the device is operating at supply voltages below 5 V.
5
Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C.
6
For programming and erasing of EEPROM, a minimum VDD = 3.0 V is required 0°C to +85°C and a minimum VDD = 4.5 V is required −40°C to 0°C.
7
Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22 method A117.
8
Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge.
250 ns See Figure 27
SU;DAT
300 ns See Figure 27
HD;DAT
4
PULLDOWN
10 µA If known logic state required
= −3.0 mA
OUT
16 programmable options on both rising and
falling edge
100
10
Kcycles
Years
Rev. B | Page 6 of 52
ADM1060
ABSOLUTE MAXIMUM RATINGS
Table 2. Absolute Maximum Ratings
Parameter Rating
Voltage on VH Pin, PDO Pins 17 V
Voltage on VP Pins 7 V
Voltage on VB Pins –7 V to +7 V
Voltage on Any Other Input –0.3 V to +6.5 V
Input Current at Any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature
max)
(T
J
Storage Temperature Range –65°C to +150°C
Lead Temperature, Soldering
Vapor Phase (60 sec)
ESD Rating, All Pins 2000 V
150°C
215°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any
other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
28-Lead TSSOP Package:
= 98°C/W
θ
JA
Rev. B | Page 7 of 52
ADM1060
5
6
TYPICAL PERFORMANCE CHARACTERISTICS
6
VP1
VH
(V)
VDDCAP
V
5
4
3
2
1
(mA)
DD
I
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
024681012 1614
Figure 2. V
3.0
2.5
2.0
1.5
(mA)
DD
I
1.0
0.5
0
0123
Figure 3. I
300
250
VDDCAP
DD
V
vs. V
(V)
VH,VVP1
vs. VVH and V
V
(V)
VP1
(Supply)
VP1
0
0246 108
VP1
250
200
150
(µA)
VH
I
100
50
4
0
01234
Figure 5. I
Figure 6. I
300
200
VVH (V)
vs. VVH
DD
VVH (V)
vs. VVH (Not Supply)
VH
12 14 16
5
200
(µA)
150
VP1
I
100
50
0
01 3245
Figure 4. I
VP1
vs. V
V
(V)
VP1
(Not Supply)
VP1
100
–6 –4 –2 0 4 62
0
(µA)
VB1
–100
I
–200
–300
–400
Figure 7. I
V
(V)
VB1
vs. V
VB1
VB1
Rev. B | Page 8 of 52
ADM1060
1.5%
1.0%
V
= 4.75V
0.5%
0.0%
–0.5%
PERCENT DEVIATION
–1.0%
–1.5%
–40 –25 –10 5 20 35 50 65 80
Figure 8. Percent Deviation in V
VDDCAP
V
= 2.7V
VDDCAP
TEMPERATURE (°C)
vs. Temperature
THRESH
4.5
4.0
3.5
3.0
2.5
(V)
PDO
2.0
V
1.5
1.0
0.5
0
0 5 10 15 20 25 30 4035
Figure 11. V
(Weak Pull-Up to VP1) vs. Load Current
PDO
I
LOAD
(µA)
V
= 5V
VP1
V
= 3.3V
VP1
14.0
13.5
13.0
12.5
(V)
12.0
PDO
V
11.5
11.0
10.5
10.0
–40 –25 –10 5 20 35 6550 80
Figure 9. V
4.5
4.0
3.5
3.0
2.5
(V)
PDO
2.0
V
1.5
1.0
0.5
0
0 0.5 1.0 1.5 2
Figure 10. V
(FET Drive Mode) vs. Temperature
PDO
(Strong Pull-Up to VP1) vs. Load Current
PDO
0µA LOAD
1µA LOAD
TEMPERATURE (°C)
V
= 3.3V
VP1
I
(mA)
LOAD
1.00
0.75
(V)
0.50
PDO
V
0.25
0
0246 108
Figure 12. V
2.0
= 5V
V
VP1
1.8
1.6
1.4
1.2
(V)
1.0
PDO
V
0.8
0.6
0.4
0.2
0
0102030405060 8070
(Strong Pull-Down) vs. Load Current
PDO
Figure 13. V
(Weak Pull-Down) vs. Load Current
PDO
I
LOAD
I
LOAD
(mA)
(µA)
Rev. B | Page 9 of 52
ADM1060
110
108
106
104
102
100
98
96
94
OSCILLATOR FREQUENCY (kHz)
92
90
–40 –25 –10 5 20 35 50 65 80
Figure 14. Oscillator Frequency vs. Temperature
TEMPERATURE (°C)
6.00
5.75
5.50
5.25
VCCP (V)
5.00
4.75
4.50
0 100 200 300 500400
I
LOAD
Figure 15. VCCP vs. Load Current
3.0
2.5
2.0
1.5
(µA)
V
VDDCAP
V
VDDCAP
= 4.75V
V
VDDCAP
= 2.7V
= 2.7V
1.0
GPI THRESHOLD (V)
0.5
0
–40 –25 –10 5 20 35 50 65 80
TEMPERATURE (°C)
V
VDDCAP
= 4.75V
Figure 16. GPI Threshold vs. Temperature
Rev. B | Page 10 of 52
ADM1060
N
INPUTS
VH
POWERING THE ADM1060
The ADM1060 is powered from the highest voltage input on
either the Positive Only supply inputs (VPn) or the High Voltage supply input (VH). The same pins are used for supply fault
detection (discussed below). A V
chooses which supply to use. The arbitrator can be considered
as diode OR’ing the positive supplies together (as shown in
Figure 17).The diodes are supplemented with switches in a synchronous rectifier manner to minimize voltage loss. This loss
can be reduced to ~0.2 V, resulting in the ability to power the
ADM1060 from a supply as low as 3.0 V. Note that the supply on
the VBn pins cannot be used to power the device, even if the
input on these pins is positive. Also, the minimum supply of
3.0 V must appear on one of the VPn pins in order to correctly
power up the ADM1060. A supply of no less than 4.5 V can be
used on VH. This is because there is no synchronous rectifier
circuit on the VH pin, resulting in a voltage drop of ~1.5 V
across the diode of the V
DD
An external capacitor to GND is required to decouple the
on-chip supply from noise. This capacitor should be connected
to the VDDCAP pin, as shown in Figure 17. The capacitor has
another use during “brown outs” (momentary loss of power).
Under these conditions, where the input supply, VPn, dips
transiently below V
, the synchronous rectifier switch
DD
immediately turns off so that it does not pull V
V
capacitor can then act as a reservoir to keep the chip active
DD
until the next highest supply takes over the powering of the
device. A 1 µF capacitor is recommended for this function. A
minimum capacitor value of 0.1 µF is required.
arbitrator on the device
DD
arbitrator.
down. The
DD
VDDCAP PIN
VP1
VP2
VP3
VP4
Figure 17. V
Arbitrator Operation
DD
OFF-CHIP
DECOUPLING
CAPACITOR
ON-CHIP SUPPLY
PROGRAMMABLE SUPPLY FAULT DETECTORS (SFDs)
The ADM1060 has seven programmable supply fault detectors
(SFDs): one high voltage detector (+2 V to +14.4 V), two bipolar
detectors (+1 V to +6 V, −2 V to –6 V) and four positive only
voltage detectors (+0.6 V to +6 V). Inputs are applied to these
detectors via the VH (high voltage supply input), VBn (bipolar
supply input), and VPn (positive only input) pins, respectively.
The SFDs detect a fault condition on any of these input supplies.
A fault is defined as undervoltage (where the supply drops
below a preprogrammed level), overvoltage (where the supply
rises above a preprogrammed level), or out-of-window (where
the supply deviates outside either the programmed overvoltage
or undervoltage threshold). Only one fault type can be selected
at a time.
Note that in the case where there are two or more supplies
within 100 mV of each other, the supply that takes control of
first will keep control. For example, if VP1 is connected to a
V
DD
3.3 V supply, V
will power up to approximately 3.1 V through
DD
VP1. If VP2 is then connected to another 3.3 V supply, VP1 will
still power the device, unless VP2 goes 100 mV higher than
VP1.
A second capacitor is required on the VCCP pin of the
ADM1060. This capacitor is the reservoir capacitor for the
central charge pump. Again, a 1 µF capacitor is recommended
for this function. A minimum capacitor value of 0.1 µF is
required.
Rev. B | Page 11 of 52
An undervoltage (UV) fault is detected by comparing the input
supply to a programmed reference (the undervoltage threshold).
If the input voltage drops below the undervoltage threshold, the
output of the comparator goes high, asserting a fault. The
undervoltage threshold is programmed using an 8-bit DAC. On
a given range, the UV threshold can be set with a resolution of
Step Size = Threshold Range/255
An overvoltage (OV) fault is detected in exactly the same way,
using a second comparator and DAC to program the reference.
All thresholds are programmed using 8-bit registers, one register each for the seven UV thresholds and one each for the seven
OV thresholds. The UV or OV threshold programmed by the
user is given by
V
×
R
V +
=
T
255
V
B
ADM1060
V
where
Voltage Range VB (V) VR (V)
0.6 V to 1.8 V 0.604 1.204
1 V to 3 V 1.003 1.999
2 V to 6 V 2.005 3.997
4.8 V to 14.4 V 4.849 9.666
–2 V to –6 V –1.994 –3.995
VT is the desired threshold voltage (UV or OV)
is the threshold voltage range
V
R
N is the decimal value of the 8 bit code
is the bottom of threshold range
V
B
The code for a given threshold is therefore given by
N = 255 × (V
– VB)/VR
T
For example, if the user wishes to set a 5 V OV threshold on
VP1, the code to be programmed in the PS1OVTH register
(discussed later) would be
N = 255 × (5 – 2.005)/3.997
Thus, N = 191 (1011 1111 binary, or 0xBF)
The available threshold ranges and their resolutions are shown
in Table 3. Note that the low end of the detection range is fixed
at 33.33% of the top of the range. Note also that for a given SFD,
the ranges overlap; for example, VH goes from 2 V to 6 V and
then from 4.8 V to 14.4 V. This is to provide better threshold
setting resolution as supplies decrease in value.
Table 3. Input Threshold Ranges and Resolution
Input Name Voltage Ranges Resolution
VH
4.8 V to 14.4 V 37.6 mV
2 V to 6 V 15.6 mV
2 V to 6 V 15.6 mV (Pos. Mode)
VBn
1 V to 3 V 7.8 mV (Pos. Mode)
−6 V to −2 V 15.6 mV (Neg. Mode)
2 V to 6 V 15.6 mV
VPn
1 V to 3 V 7.8 mV
0.6 V to 1.8 V 4.7 mV
Figure 18 illustrates the function of the programmable SFD (for
the case of a positive supply).
Pn
RANGE SELECT
DAC (1 OR 2 BITS)
VREF
DUAL 8-BIT
DAC FOR
SETTING UV
AND OV
THRESHOLDS
Figure 18. Positive Programmable Supply Fault Detector
OV
COMPARATOR
UV
COMPARATOR
GLITCH
FILTER
FAULT TYPE
SELECT
FAULT
OUTPUT
SFD COMPARATOR HYSTERESIS
The OV and UV comparators shown in Figure 18 are always
looking at VPn via a potential divider. In order to avoid
chattering (multiple transitions when the input is very close to
the set threshold level), these comparators have digitally
programmable hysteresis. The UV and OV hysteresis can be
programmed in two registers that are similar but separate to the
UV or OV threshold registers. Only the five LSBs of these
registers can be set. The hysteresis is added after the supply
voltage goes out of tolerance. Thus, the user can determine how
much above the UV threshold the input must rise again before a
UV fault is deasserted. Similarly, the user can determine how
much below the OV threshold the input must fall again before
an OV fault is deasserted. The hysteresis figure is given by
= VR × N
V
H
where
V
is the desired hysteresis voltage
H
is the decimal value of the 5-bit hysteresis code
N
THRESH
Therefore, if the low range threshold detector was selected, the
max hysteresis is defined as
(3 V – 1 V) × 31/255 = 242 mV, where (2
The hysteresis programming resolution is the same as the
threshold detect ranges—that is, 37.5 mV on the high range,
15.6 mV on the midrange, 7.8 mV on the low range, and 4.7 mV
on the ultralow range.
THRESH
/255
5
– 1 = 31)
BIPOLAR SFDs
The two bipolar SFDs also allow the detection of faults on negative supplies. A polarity bit in the setup register for this SFD
(Bit 7 in Register BSnSEL—see register map overleaf) determines if a positive or negative input should be applied to VBn.
Only one range (−6 V to −2 V) is available when the SFDs are in
negative mode. Note that the bipolar SFDs cannot be used to
power the ADM1060, even if the voltage on VBn is positive.
Rev. B | Page 12 of 52
ADM1060
SFD FAULT TYPES
Three types of faults can be asserted by the SFD: an OV fault, a
UV fault, and an out-of-window fault (where the UV and OV
faults are OR’ed together). The type of fault required is
programmed using the fault type select bits (Bits 0, 1 in Register
_SnSEL). If an application requires separate fault conditions to
be detected on one supply (e.g., assert PDO1 if a UV fault
occurs on a 3.3 V supply, assert PDO9 if an OV fault occurs on
the same 3.3 V supply), that supply will need to be applied to
more than one input pin.
GLITCH FILTERING ON THE SFDs
The final stage of the SFD is a glitch filter. This block provides
time domain filtering on the output of the SFD. This allows the
user to remove any spurious transitions (such as supply bounce
at turn-on). This deglitching function is in addition to the
programmable hysteresis of the SFDs. The glitch filter timeout
is programmable up to 100 µs. If a pulse shorter than the
programmed timeout appears on the input, this pulse is masked
and the signal change will appear on the output. If an input
pulse longer than the programmed timeout appears on the
input, this pulse will appear on the output. The output will be
delayed (with respect to the input) by the length of the
programmed timeout.
GLITCH FILTER INPUT
PROGRAMMED TIMEOUT
t
0
t
0
t
GF
t
GF
GLITCH FILTER OUTPUT
Figure 19. Glitch Filtering on the SFDs
PROGRAMMED TIMEOUT
t
t
t
0
0
GF
t
GF
PROGRAMMING THE SFDs ON THE SMBus
The details of using the SMBus are described later, but the register names associated with the supply fault detector blocks, the
bit map of those registers, and the function of each of the bits is
described in the following tables. The tables show how to set up
UV threshold, UV hysteresis, OV threshold, OV hysteresis,
glitch filtering, and fault type for each of the SFDs on the
ADM1060.
Figure 19 shows the implementation of glitch filtering.
Rev. B | Page 13 of 52
ADM1060
SFD REGISTER NAMES
Table 4. List of Registers for the Supply Fault Detectors
Hex
Address Table Name
A0 Table 5 BS1OVTH 0xFF Overvoltage Threshold for Bipolar Voltage SFD1 (BS1SFD)
A1 Table 6 BS1OVHYST 0x00 Digital Hysteresis on OV Threshold for BS1SFD
A2 Table 7 BS1UVTH 0x00 Undervoltage Threshold for BS1SFD
A3 Table 8 BS1UVHYST 0x00 Digital Hysteresis on UV Threshold for BS1SFD
A4 Table 9 BS1SEL 0x00 Glitch Filter, Range, and Fault Type Select for BS1SFD
A8 Table 5 BS2OVTH 0xFF Overvoltage Threshold for Bipolar Voltage SFD2 (BS2SFD)
A9 Table 6 BS2OVHYST 0x00 Digital Hysteresis on OV Threshold for BS2SFD
AA Table 7 BS2UVTH 0x00 Undervoltage Threshold for BS2SFD
AB Table 8 BS2UVHYST 0x00 Digital Hysteresis on UV Threshold for BS2SFD
AC Table 9 BS2SEL 0x00 Glitch Filter, Range, and Fault Type Select for BS2SFD
B0 Table 10 HSOVTH 0xFF Overvoltage Threshold for High Voltage SFD (HVSFD)
B1 Table 11 HSOVHYST 0x00 Digital Hysteresis on OV Threshold for HVSFD
B2 Table 12 HSUVTH 0x00 Undervoltage Threshold for HVSFD
B3 Table 13 HSUVHYST 0x00 Digital Hysteresis on UV Threshold for HVSFD
B4 Table 14 HSSEL 0x00 Glitch Filter, Range, and Fault Type Select for HVSFD
B8 Table 15 PS1OVTH 0xFF Overvoltage Threshold for Positive Voltage SFD1 (PS1SFD)
B9 Table 16 PS1OVHYST 0x00 Digital Hysteresis on OV Threshold for PS1SFD
BA
BB
BC Table 19 PS1SEL 0x00 Glitch Filter, Range, and Fault Type Select for PS1SFD
C0 Table 15 PS2OVTH 0xFF Overvoltage Threshold for Positive Voltage SFD2 (PS2SFD)
C1 Table 16 PS2OVHYST 0x00 Digital Hysteresis on OV Threshold for PS2SFD
C2
C3
C4 Table 19 PS2SEL 0x00 Glitch Filter, Range, and Fault Type Select for PS2SFD
C8 Table 15 PS3OVTH 0xFF Overvoltage Threshold for Positive Voltage SFD3 (PS3SFD)
C9 Table 16 PS3OVHYST 0x00 Digital Hysteresis on OV Threshold for PS3SFD
CA
CB
CC Table 19 PS3SEL 0x00 Glitch Filter, Range, and Fault Type Select for PS3SFD
D0 Table 15 PS4OVTH 0xFF Overvoltage Threshold for Positive Voltage SFD4 (PS4SFD)
D1 Table 16 PS4OVHYST 0x00 Digital Hysteresis on OV Threshold for PS4SFD
D2
D3
D4 Table 19 PS4SEL 0x00 Glitch Filter, Range, and Fault Type Select for PS4SFD
Table 17
PS1UVTH 0x00 Undervoltage Threshold for PS1SFD
Table 18
PS1UVHYST 0x00 Digital Hysteresis on UV Threshold for PS1SFD
Table 17
PS2UVTH 0x00 Undervoltage Threshold for PS2SFD
Table 18
PS2UVHYST 0x00 Digital Hysteresis on UV Threshold for PS2SFD
Table 17
PS3UVTH 0x00 Undervoltage Threshold for PS3SFD
Table 18
PS3UVHYST 0x00 Digital Hysteresis on UV Threshold for PS3SFD
Table 17
PS4UVTH 0x00 Undervoltage Threshold for PS4SFD
Table 18
PS4UVHYST 0x00 Digital Hysteresis on UV Threshold for PS4SFD
Default
Power-On Value Description
Rev. B | Page 14 of 52
ADM1060
SFD Register Bit Maps
BIPOLAR SUPPLY FAIL DETECT (BSn SFD) REGISTERS
Table 5. Register 0xA0, 0xA8 BSnOVTH
(Power-On Default 0xFF)
Bit Name R/W Description
7–0 OV7–OV0 R/W
8-Bit Digital Value for OV
Threshold on BSn SFD
Table 6. Register 0xA1, 0xA9 BSnOVHYST
(Power-On Default 0x00)
Bit Name R/W Description
7–5 Reserved N/A Cannot Be Used
4–0 HY4–HY0 R/W
5-Bit Digital Value for Hysteresis
on OV Threshold of BSn SFD
Table 9. Register 0xA4, 0xAC BSnSEL (Power-On Default 0x00)
Bit Name R/W Description
7 POL R/W
6−4 GF2−GF0 R/W
3 Reserved N/A Cannot Be Used
2 RSEL R/W
1−0 FS1−FS0 R/W
Polarity of Bipolar
SFDn
GF2 GF1 GF0 Glitch Filter Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100
Note: When POL is set to 1 (SFD is in negative mode), RSEL is unused since there is only one range in
this mode.
RSEL1 Bottom of Range Top of Range Step Size (mV)
0 1 V 3 V 7.8
1 2 V 6 V 15.6
FS1 FS0 Fault Select Type
0 0 Overvoltage
0 1 Undervoltage
1 0 Out-of-Window
1 1 Not Allowed
POL Sign of Detection Range
0 Positive
1 Negative
Table 7. Register 0xA2, 0xAA BSnUVTH
(Power-On Default 0x00)
Bit Name R/W Description
7–0
UV7–UV0
R/W
8-Bit Digital Value for UV Threshold on BSn SFD
Table 8. Register 0xA3, 0xAB BSnUVHYST
(Power-On Default 0x00)
Bit Name R/W Description
7–5 Reserved N/A Cannot Be Used
4–0
HY4–HY0
R/W
5-Bit Digital Value for Hysteresis
on UV Threshold of BSn SFD
Rev. B | Page 15 of 52
ADM1060
HIGH VOLTAGE SUPPLY FAULT DETECT (HV SFD) REGISTERS
Table 10. Register 0xB0 HSOVTH (Power-On Default 0xFF)
Bit Name R/W Description
7–0 OV7–OV0 R/W
8-Bit Digital Value for OV
Threshold on HV SFD
Table 11. Register 0xB1 HSOVHYST (Power-On Default 0x00)
Bit Name R/W Description
7–5 Reserved N/A Cannot Be Used
4–0 HY4–HY0 R/W
5-Bit Digital Value for Hysteresis
on OV Threshold of HV SFD
Table 12. Register 0xB2 HSUVTH (Power-On Default 0x00)
Bit Name R/W Description
7–0
Table 13. Register 0xB3 HSUVHYST (Power-On Default 0x00)
Bit Name R/W Description
7–5 Reserved N/A Cannot Be Used
4–0
Table 14. Register 0xB4 HSSEL (Power-On Default 0x00)
Bit Name R/W Description
7 Reserved N/A Cannot Be Used
6−4 GF2−GF0 R/W
3 Reserved N/A Cannot Be Used
2 RSEL W
1−0 FS1−FS0 W
GF2 GF1 GF0 Glitch Filter Delay (µs)
0 0 0 0
0 0 1 5
0 1 0 10
0 1 1 20
1 0 0 30
1 0 1 50
1 1 0 75
1 1 1 100
RSEL Bottom of Range Top of Range Step Size (mV)
0 2 V 6 V 15.6
1 4.8 V 14.4 V 37.6
FS1 FS0 Fault Select Type
0 0 Overvoltage
0 1 Undervoltage
1 0 Out-of-Window
1 1 Not Allowed
UV7–UV0
HY4–HY0
R/W
8-Bit Digital Value for UV
Threshold on HV SFD
R/W
5-Bit Digital Value for Hysteresis
on UV Threshold of HV SFD
Rev. B | Page 16 of 52
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