ANALOG DEVICES ADM1060 Service Manual
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PRELIMINARY TECHNICAL DA T A
Communications System
a
Preliminary Technical Data
ADM1060 TABLE OF CONTENTS
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
ADM1060 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
ADM1060 Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Powering the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Programmable Supply Fault Detectors (SFD’s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SFD Comparator Hysteresis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bipolar SFD’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
SFD Fault Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Glitch Filtering on the SFD’s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Programming the SFD’s on the SMBus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SFD Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SFD Register Bitmaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bipolar Supply Fail Detect (BSnSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
High Voltage Supply Fault Detect (HVSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Positive Voltage Supply Fault Detect (PSnSFD) Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Watchdog Fault Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
General Purpose Inputs (GPI’s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Logic State of the GPI’s (and other Logic Inputs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Programmable Logic Block Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
PLBA Register Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
PLBA Register Bitmaps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Programmable Delay Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Programmable Driver Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Fault/Status Reporting on the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Fault Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Mask Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Configuuration Download at Power- Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Updating the Configuration of the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Internal Registers of the ADM1060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
General SMBus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
SMBus Protocols for RAM and EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ADM1060 Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
ADM1060 Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Applications Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Outline Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Supervisory/Sequencing Circuit
ADM1060
REV. PrJ 11/02
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
ADM1060
PRELIMINARY TECHNICAL D A T A
FEATURES
Faults detected on 7 independent supplies
•
1 High Voltage supply (up to 14.4V)
•
4 Positive Voltage Only Supplies (up to 6V)
•
2 Positive/Negative Voltage supplies (up to +6V OR
down to -6V)
Watchdog Detector Input- Timeout delay programmable
from 200ms to 12.8sec
4 General Purpose Logic Inputs
Programmable Logic Block- combinatorial and sequencing logic control of all inputs and outputs
9 Programmable Output Drivers
•
Open Collector (external resistor required)
•
Open Collector with internal pull-up to V
•
Fast Internal pull-up to V
•
Open Collector with internal pull-up to VPn
•
Fast Internal pull-up to VPn
•
Internally charge pumped high drive (for use with
external N- channel FETS- PDO’s 1 to 4 only)
EEPROM- 512 Bytes
Industry Standard 2- Wire Bus Interface (SMBus)
Guaranteed PDO Low with VPn, VH=1V
APPLICATIONS
Central Office Systems
Servers
Infrastructure Network Boards
High density, multi- voltage system cards
GENERAL DESCRIPTION
The ADM1060 is a programmable supervisory/sequencing
device which offers a single chip solution for multiple
power supply fault detection and sequencing in communications systems.
In central office, servers and other infrastructure systems,
a common backplane dc supply is reduced to multiple
board supplies using dc/dc converters. These multiple
supplies are used to power different sections of the board
(eg) 3.3V Logic circuits, 5V logic circuits, DSP core and
I/O circuits etc. There is usually a requirement that certain sections power up before others (eg) a DSP core to
power up before the DSP I/O or vice versa. This is in
order to avoid damage, miscommunication or latch- up.
The ADM1060 facilitates this, providing supply fault
detection and sequencing/combinatorial logic for up to 7
independent supplies. The 7 Supply Fault Detectors consist of one high voltage detector (up to +14.4V), two bipolar voltage detectors (up to +6V OR down to -6V) and
4 positive low voltage detectors (up to +6V). All of the
detectors can be programmed to detect undervoltage, overvoltage or out- of window (undervoltage OR overvoltage) conditions. The inputs to these Supply Fault
Detectors are via the VH pin (High Voltage), VBn pins
(positive OR negative) and VPn pins (Positive only) pins
respectively. Either the VH supply or one of the VPn
supplies is used to power the ADM1060 (whichever is
highest). This ensures that, in the event of a supply failure, the ADM1060 is kept alive for as long as possible,
thus enabling a reliable fault flag to be asserted and the
system to be powered down in an ordered fashion.
DD
DD
Other inputs to the ADM1060 include a Watchdog Detector (WDI) and 4 General Purpose Inputs (GPIn). The
Watchdog Detector can be used to monitor a processor
clock. If the clock does not toggle (transition from low to
high or from high to low) within a programmable timeout
period (up to 18 sec.), a fail flag will assert. The 4 General Purpose inputs can be configured as logic buffers or
to detect positive/negative edges and to generate a logic
pulse or level from those edges. Thus, the user can input
control signals from other parts of their system (eg RESET or POWER_GOOD) to gate the sequencing of the
supplies supervised by the ADM1060.
The ADM1060 features 9 Programmable Driver Outputs
(PDO’s). All 9 outputs can be configured to be logic
outputs, which can provide multiple functions for the end
user such as RESET generation, POWER_GOOD status,
enabling of LDO’s, Watchdog Timeout assertion etc.
PDO’s 1- 4 have the added feature of being able to provide an internally charge pumped high voltage for use as
the gate drive of an external N- Channel FET which
could be placed in the path of one of the supplies being
supervised.
All of the inputs and outputs described above are controlled by the Programmable Logic Block Array. This is
the logic core of the ADM1060. It is comprised of 9
macrocells, one for each PDO. These macrocells are
essentially just wide AND gates. Any/all of the inputs can
be used as an input to these macrocells. The output of a
macrocell can also be used as an input to any macrocell
other than itself (an input to itself would result in a noterminating loop). The PLBA outputs control the PDO’s
of the ADM1060 via delay blocks, where a delay of between 0 and 500ms can be programmed on the rising and/
or the falling edge of the data. This results in a very flexible sequencing ability. Thus, for instance, PDO1 can be
programmed so that it will not assert until, say, VP2,
VP3and VP4 supplies are in tolerance, VB1 and VH have
been in tolerance for 200mS, and PDO7 has already been
asserted. A simple sequencing operation would be to
daisy chain each PLB output into the input of the next
PLB such that PDO9 doesn’t assert until PDO8 asserts,
which in turn doesn’t assert until PDO7 asserts etc.
All of the functional capability described here is programmable through the industry standard 2 wire bus (SMBus)
provided. Device settings can be written to EEPROM
memory for automatic programming of the device on
power-up. The EEPROM is organised in 512 bytes, half
of which are used to program all of the functions on the
ADM1060. The other 256 bytes of EEPROM are for
general purpose system use (eg) date codes, system ID etc.
Read/write access to this is also via the 2 wire interface.
In addition, each output state can be directly overdriven
from the serial interface, allowing a further level of control (eg) a system controlled soft powerdown.
–2–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DA T A
ADM1060
VH
VP1
VP2
VP3
VP4
VB1
VB2
GPI1
GPI2
GPI3
GPI4
WDI
GND
VCCP
PROGRAMMABLE
DELAY BLOCKS
PROGRAMMABLE
PDB1
LOGIC BLOCK
ARRAY
8
9
10
11
12
13
14
28
27
26
25
24
6
HIGH SUPPLY(14.4v)
FAULT DETECTOR
POSITIVE SUPPLY
FAULT DETECTOR 1
POSITIVE SUPPLY
FAULT DETECTOR 4
BIPOLAR SUPPLY
FAULT DETECTOR 1
BIPOLAR SUPPLY
FAULT DETECTOR 2
INPUT LOGIC
SIGNAL CONDITION
WATCHDOG FAULT
DETECTOR
VREF
(PLBA)
PLB
MACROCELL 1
PLB
MACROCELL 2
PLB
MACROCELL 3
PLB
MACROCELL4
PLB
MACROCELL 5
PLB
MACROCELL 6
PLB
MACROCELL 7
PLB
MACROCELL 8
PLB
MACROCELL 9
Internal
7
5.5V supply
T
RISETFALL
T
RISETFALL
T
RISETFALL
T
RISETFALL
T
RISETFALL
T
RISETFALL
T
RISETFALL
T
RISETFALL
T
RISETFALL
PDB2
PDB3
PDB4
PDB5
PDB6
PDB7
PDB8
PDB9
S
M
B
REGULATED
5.5V SUPPLY
CHARGE PUMP
Data, Address and
Write Enable Buses
to store control information
local to functions
U
S
D
A
T
V
DD
ARBITRATOR
SMBus INTERFACE
A
DEVICE
CONTROLLER
PROGRAMMABLE
DRIVER OUPUTS
PDO2
PDO3
PDO4
PDO5
PDO6
PDO8
1
0
0
K
H
z
C
L
O
C
K
PDO1
PDO7
PDO9
EEPROM
15
16
17
18
19
20
21
22
23
PDO1
PDO2
PDO3
PDO4
PDO5
PDO6
PDO7
PDO8
PDO9
REV. PrJ 11/02
5
4
SCL
SDA
A1
123
A0
VDDCAP
ADM1060 FUNCTIONAL BLOCK DIAGRAM
–3–
PRELIMINARY TECHNICAL D A T A
ADM1060–SPECIFICA TIONS
(VH=4.5V to 14.4V, VPn = 3.0V to 6.0V 2, TA = -40oC to 85oC, unless otherwise noted.)
Parameter Mi n Typ Max Units Test Conditions/Comments
POWER SUPPLY ARBITRATION
VDDCAP 2.7 V Any VPn>=3.0V
2.7 VH>=4.5V
4.75 5.1 V Any VPn=6.0V
4.75 5.1 V VH=14.4V
POWER SUPPLY
Supply Current, I
DD
Additional current available from VDDCAP 1 mA Max. additional load that can be
SUPPLY FAULT DETECTORS
VH Input
Input Impedance 52 k⍀ From VH to GND
Threshold Ranges
Mid Range 2 6 V
Programming Step Size 15.6 mV
High Range 4.8 14.4 V
Programming Step Size 37.6 mV
VPn Inputs
Input Impedance 52 k⍀ From VPn to GND
Threshold Ranges
Ultra Low Range 0.6 1.8 V
Programming Step Size 4.7 mV
Low Range 1 3 V
Programming Step Size 7.8 mV
Mid Range 2 6 V
Programming Step Size 15.6 mV
VBn Inputs
Input Impedance 190 k⍀ From VBn to 2.25V (Internal Ref.)
Threshold Ranges
Negative Mode:
Mid Range -6 -2 V
Programming Step Size 15.6 mV
Positive Mode:
Low Range 1 3 V
Programming Step Size 7.8 mV
Mid Range 2 6 V
Programming Step Size 15.6 mV
Absolute Accuracy 2.5 %
Absolute Accuracy-
Calibrated Voltage Thresholds
4
Threshold Programming Resolution 8 Bits
3 mA VDDCAP=4.75V, no PDO FET
Drivers on, no loaded PDO pullups
to VDDCAP
5 mA VDDCAP=4.75V, all PDO FET
Drivers on (loaded with 1A), no
PDO pullups to VDDCAP
drawn from PDO pullups to
VDDCAP
52 k⍀ From VBn to GND (positive mode)
30 k⍀ From VBn to GND (negative mode)
1.0 % TA=0oC to 85oC, Threshold
Voltage>0.9V
Digital Glitch Filter 0 100 s See figure 3. 8 timeout options
between 0 and 100s
NOTES
1
These are target specifications and subject to change.
2
At least one VPn must be >=3.0V if used as supply. VH must be >=4.5V if used as supply.
3
Logic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V.
4
Calibrated Voltage Thresholds are set at Production.
–4–
REV.PrJ11/02
PRELIMINARY TECHNICAL DA T A
ADM1060–SPECIFICA TIONS
1
(VH=4.5V to 14.4V, VPn = 3.0V to 6.0V2, TA = -40oC to 85oC, unless otherwise noted.)
Parameter Min Typ Max Units Test Conditions/Comments
PROGRAMMABLE DRIVER
OUTPUTS
High Voltage (Charge Pump) Mode
(PDO’s 1 to 4)
Output Impedance, R
V
OH
OUT
10.5 12.5 14 V IOH=0
10 12 V I
I
OUTAVG
Standard (Digital Output) Mode
(PDO’s 1 to 9)
V
OH
2.4 V VPU(Pullup to VDDCAP or
V
V
OL
I
SINK
R
PULLUP-
I
SOURCE (VPn)
Weak Pull-up 20 k⍀ Internal pullup
Tristate Output Leakage Current 10 AV
DIGITAL INPUTS
(GPI 1-4,WDI,A0,A1)
Input High Voltage, V
Input Low Voltage, V
Input High Current, I
Input Low Current, I
IL
IH
IL
IH
2.0 V Max. VIN=5.5V
-1 AVIN = 5.5V
Input Capacitance TBD pF
Programmable Pulldown Current, I
PULLDOWN
SERIAL BUS DIGITAL INPUTS
(SDA,SCL)
Input High Voltage, V
Input Low Voltage, V
IH
IL
Output Low Voltage, V
OL
2.0 V
PROGRAMMABLE DELAY BLOCK
Timeout 0 500 ms 16 programmable options on both
440 k⍀
=1A
OH
20 A 2V<VOH<7V
VPn)=2.7V, I
4.5 V V
-0.3 V VPU<=2.7V, IOH=1mA
PU
to VPn=6.0V, IOH=0mA
PU
0.4 V IOL=2mA
1.2 V I
2.0 V I
=10mA
OL
=15mA
OL
20 mA Total Sink Current
2 mA Current Load on any VPn pull-ups
(ie) total source current available
through any number of PDO pull-up
switches configured on to any one
=14.4V
PDO
0.8 V Max. VIN=5.5V
1 AV
IN
= 0
10 A If known logic state required
0.8 V
0.4 V I
= -3.0mA
OUT
rising and falling edge
OH
=1mA
WATCHDOG TIMER INPUT
Timeout 0 12.8 s 8 programmable timeout options
SERIAL BUS TIMING
Clock Frequency, f
Glitch Immunity, t
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t
NOTES
1
These are target specifications and subject to change.
2
At least one supply connected to VH or VPn must be >=3.0V
3
Logic inputs will accept input high voltages up to 5.5V even when device is operating at supply voltages below 5V.
4
Timing specifications are tested at logic levels of V
REV.PrJ 11/02
SCLK
SW
BUF
SU;STA
HD;STA
LOW
HIGH
SU;DAT
HD;DAT
4.7 µs See Figure 8c
4.7 µs See Figure 8c
4 µs See Figure 8c
4.7 µs See Figure 8c
4 µs See Figure 8c
r
f
250 ns See Figure 8c
300 ns See Figure 8c
= 0.8V for a falling edge and V
IL
–5–
400 KHz See Figure 8c
50 ns See Figure 8c
1000 ns See Figure 8c
300 µs See Figure 8c
= 2.2V for a rising edge.
IH
PRELIMINARY TECHNICAL D A T A
2
3
4
5
6
7
8
9
10
11
12
13
14
1
ADM1060
PDO9
GPI1
GPI2
GPI3
GPI4
WDI
GND
VDDCAP
PDO7
27
26
25
24
23
22
21
20
19
18
17
16
15
28
VH
VP1
VP2
VP3
VB1
PDO8
PDO6
PDO5
SCL
SDA
A1
A0
VCCP
PDO1
PDO2
VP4
VB2
PDO3
PDO4
ADM1060
PIN FUNCTION DESCRIPTION
Pin Mnemonic Function
1 A0 Logic input. Controls the 7th bit (LSB) of the 7 bit Serial Bus Address.
2 A1 Logic input. Controls the 6th bit of the 7 bit Serial Bus Address.
3 SDA Serial Bus data I/O pin. Open- Drain output. Requires 2.2k pullup resistor
4 SCL Open- Drain Serial Bus Clock pin. Requires 2.2k pullup resistor
5 VDDCAP V
6 GND Ground. Connect to common of power supplies.
7 VCCP Reservoir Capacitor for Central Charge Pump. This charge pump powers all of the internal
8 VH High Voltage Supply Input. 2 input ranges. A supply of between 2V and 6V or between
9-12 VP1-4 Positive Only Supply Inputs. 2 input ranges. A supply of between 1V and 3V or between
13-14 VB1-2 Bipolar Supply Inputs. 2 modes. 2 input ranges in positive mode. 1 input range in negative
15-23 PDO_1-9 Programmable Driver Output pin. All 9 can be programmed as logic outputs with multiple
24 WDI Watchdog Input. Used to monitor a processor clock and asserts a fault condition if the clock
25-28 GPI_4-1 General Purpose Logic Input. TTL compatible Logic. Can be used as, say, a Manual
Reset, a Chip Enable pin or as an input for a control logic signal which may be critical to the power
bypass capacitor pin. A capacitor from this pin to GND stabilises the VDD Arbitrator.
DD
0.1F is recommended for this function.
circuits of the ADM1060 and provides the first stage in the tripler circuits used to produce
12V of gate drive on PDO’s 1- 4.
4.8V and 14.4V can be applied to this pin. The VDD arbitrator will select this supply to power
the ADM1060 if it is the highest supply supervised.
2V and 6V can be applied to this pin. The V
arbitrator will select one of these supplies to
DD
power the ADM1060 if it is the highest supply supervised.
mode. A supply of between -6V and -2V can be applied to this pin when set in negative mode.
A supply of between 1V and 3V or between 2V and 6V can be applied to this pin when set in
positive mode.
pull-up options to VDD or VPn. PDO’s 1 to 4 can also provide a charge-pump generated
gate drive for external N- Channel FET
fails to transition from low-to-high or high-to-low within a programmed timeout period (up to
18sec).
up/down sequence of the supplies under control.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VH Pin . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
Voltage on VP
Voltage on VB
Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . +7 V
Pins . . . . . . . . . . . . . . . . . . . . . -7 V to +7V
Voltage on A0,A1 . . . . . . . . . . . . . . -0.3V to (V
Voltage on Any Other Input . . . . . . . . . . . . . . -0.3V to 6.5V
Input Current at any pin . . . . . . . . . . . . . . . . . . . . . . ±5mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . ±20mA
Maximum Junction Temperature (T
max) . . . . . . .150 °C
J
Storage Temperature Range . . . . . . . . .–65°C to +150°C
Lead Temperature, Soldering
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . +215°C
ESD Rating all pins . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
*Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. This is a stress rating only;
functional operation of the device at these or any other conditions above
those indicated in the operational section of this specification is not
implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
THERMAL CHARACTERISTICS
28-Pin TSSOP Package:
⍜
JA
= 98°C/Watt
+0.3V)
CC
DRAFT
PINOUT
ADM1060 PIN CONFIGURATION
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
ADM1060ARU -40°C to +85°C 28-PinTSSOP RU-28
–6–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DA T A
ADM1060 INPUTS ADM1060
ADM1060 INPUTS
POWERING THE ADM1060
The ADM1060 is powered from the highest voltage input
on either the Positive Only supply inputs (VPn) or the
High Voltage supply input (VH). The same pins are used
for supply fault detection (discussed below) . A V
DD
Arbitrator on the device chooses which supply to use. The
arbitrator can be considered to be diode OR’ing the positive supplies together (as shown in figure 1). In addition
to this, the diodes are supplemented with switches in a
synchronous rectifier manner, to minimise voltage loss.
This loss can be reduced to ~0.2V, resulting in the ability
to power the ADM1060 from a supply as low as 3.0V.
Note that the supply on the VBn pins cannot be used to
power the device, even if the input on these pins is positive. Also, the minimum supply of 3.0V must appear on
one of the VPn pins in order to power up the ADM1060
correctly. A supply of no less than 4.5V can be used on
VH. This is because there is no synchronous rectifier
circuit on the VH pin, resulting in a voltage drop of ~1.5V
across the diode of the V
Arbitrator.
DD
An external cap to GND is required to decouple the onchip supply from noise. This cap should be connected to
the VDDCAP pin, as shown in figure 1. The cap has
another use during “brown outs” (momentary loss of
power). Under these conditions, where the input supply,
VPn, dips transiently below V
switch immediately turns off so that it doesn’t pull V
, the synchronous rectifier
DD
DD
down. The VDD cap can then act like a reservoir and keep
the chip active until the next highest supply takes over the
powering of the device. 0.1F is recommended for this
function.
Note that in the case where there are 2 or more supplies
within 100mV of each other, the supply which takes control of V
nected to a 3.3V supply, then V
first will keep control (e.g) if VP1 is con-
DD
will power up to
DD
approximately 3.1V through VP1. If VP2 is then connected to another 3.3V supply, VP1 will still power the
device, unless VP2 goes 100mV higher than VP1.
VH
PROGRAMMABLE SUPPLY FAULT DETECTORS
(SFD’S)
The ADM1060 has seven programmable Supply Fault
Detectors, 1 high voltage detector (2V to 14.4V), 2 bipolar detectors (2V to 6V, -2V to -6V) and 4 Positive only
voltage detectors (0.6V to 6V). Inputs are applied to these
detectors via the VH (High Voltage Supply input) pin,
VBn (Bipolar Supply input) pins and VPn (Positive Only
input) pins respectively. The SFD’s detect a fault condition on any of these input supplies. A fault is defined as
Undervoltage (where the supply drops below a
preprogrammed level), Overvoltage (where the supply
rises above a preprogrammed level) or Out-of-Window
(where the supply deviates outside either the programmed
overvoltage OR undervoltage threshold). Only one fault
type can be selected at a time.
An Undervoltage fault is detected by comparing the input
supply to a programmed reference (the undervoltage
threshold). If the input voltage drops below the
undervoltage threshold the output of the comparator goes
high, asserting a fault. The undervoltage threshold is
programmed using an 8 bit DAC. On a given range, the
UV threshold can be set with a resolution of:-
Step Size = Threshold Range/255
An Overvoltage (OV) fault is detected in exactly the same
way, using a second comparator and DAC to program the
reference.
All thresholds are programmed using 8 bit registers, one
register each for the 7 UV thresholds and 1 each for the 7
OV thresholds. The UV or OV threshold programmed by
the user is given by:-
V
= VR x N + V
T
B
255
where:V
= Desired Threshold Voltage (UV or OV)
T
V
= Threshold Voltage Range
R
N = Decimalized version of 8 bit code
V
= Bottom of Threshold Range
B
This results in the code for a given threshold being given
by:-
N=255 x (V
- VB)/V
T
R
VP1
VP2
VP3
VP4
Figure 1. VDD Arbitrator Operation
REV. PrJ 11/02
Limit current
surge to VDDI/
decoupling cap
VDDCAP pin
Off -chip
decoupling
capacitor
VDDI
Thus, for example, if the user wishes to set a 5V OV
threshold on VP1, the code to be programmed in the
PS1OVTH register (discussed later) would be given by:-
N=255 x (5-2)/4
–7–
PRELIMINARY TECHNICAL DA T A
ADM1060 ADM1060 INPUTS
Thus, N=192 (11000000 or C0H)
The available threshold ranges, and the resolution they are
programmed to are shown in table 1. Note that the low
end of the detection range is fixed to 33.33% of the top of
the range. Note also, that for a given SFD, the ranges
overlap (eg) VH goes from 2V to 6V then from 4.8V to
14.4V. This is to provide better threshold setting resolution as supplies decrease in value.
Input Name Voltage Ranges Resolution
VH 4.8V to 14.4V 37.6mV
2V to 6V 15.6mV
VBn 2V to 6V 15.6mV (Pos. Mode)
1V to 3V 7.8mV “
-6V to -2V 15.6mV (Neg. Mode)
VPn 2V to 6V 15.6mV
1V to 3V 7.8mV
0.6V to 1.8V 4.7mV
Table 1. Input threshold Ranges and Resolution
.
Figure 2 illustrates the function of the programmable
SFD (for the case of a positive supply).
VPn
RANGE SELECT
DAC (1- BIT)
VREF
DUAL 8-BIT DAC
FOR SETTING UV
AND OV THRESHOLDS
OV
Comparator
UV
Comparator
Fault Type
select
Glitch Filter
FAULT
OUTPUT
Figure 2. Positive Programmable Supply Fault Detector
SFD COMPARATOR HYSTERESIS
The OV and UV comparators, shown in figure 1, are always looking at VPn via a potential divider. In order to
avoid chattering (multiple transitions when the input is
very close to the threshold level set), these comparators
have digitally progammable hysteresis. The UV and OV
hysteresis can be programmed in two registers which are
similar but separate to the UV or OV threshold registers.
Only the 5 LSB’s of these registers can be set. The
hysteresis is added after the supply voltage goes out of
tolerance. Thus, the user can determine how much above
the UV threshold the input must rise again before a UV
fault is de-asserted. Similarly, the user can determine
how much below the OV threshold the input must fall
again before an OV fault is de-asserted. The hysteresis
figure is given by:-
V
H=VR
x N
THRESH
/255
where:-
V
= Desired Hysteresis Voltage
H
N
= Decimalized version of 5 bit hysteresis code
THRESH
Therefore, if the low range threshold detector was selected
(ie) 1V to 3V (V
(3V-1V) x 31/255 = 242mV (2
), the max hysteresis is then defined as:-
R
5
-1 =31)
The hysteresis programming resolution is the same as the
threshold detect ranges (ie) 37.5mV on the high range,
15.6mV on the mid range, 7.8mV on the low range and
4.7mV on the ultra low range.
BIPOLAR SFD’S
The 2 bipolar SFD’s also allow the detection of faults on
negative supplies. A polarity bit in the setup register for
this SFD (bit 7- register BSnSEL- see register map
overleaf) determines if a positive or negative input should
be applied to VBn. Only 1 range (-6V to -2V) is available
when the SFD’s are in negative mode. Note that the bipolar SFD’s cannot be used to power the ADM1060, even
if the voltage on VBn is positive.
SFD FAULT TYPES
3 types of faults can be asserted by the SFD- 1) An OV
fault, 2) an UV fault and 3) an out-of-window fault (where
the UV and OV faults are OR’ed together). The type of
fault required is programmed using the Fault Type Select
bits (bits 0,1- Register _SnSEL). If an application requires separate fault conditions to be detected on one supply (eg) assert PDO1 if an UV fault occurs on a 3.3V
supply, assert PDO9 if an OV fault occurs on the same
3.3V supply, that supply will need to be applied to more
than one input pin.
GLITCH FILTERING ON THE SFD’S
The final stage of the SFD is a glitch filter. This block
provides time domain filtering on spurious transitions of
the SFD fault output. These could be caused by bounce
on a supply at its initial turn- on. The comparators of the
SFD can have hysteresis digitally programmed into them
to ensure smooth transitions but further deglitching is
provided by the glitch filter stage. A fault must be asserted for greater than the programmed Glitch Filter
timeout before it is seen at the output of the glitch filter.
The max. programmable timeout period is 100s. Both
edges of the input are filtered by the same amount of time,
so if the input pulse is longer than the glitch filter timeout
and is seen at the output, the length of the output pulse is
the same as the input pulse. If the input pulse is shorter
than the programmed timeout, then nothing appears at the
output. Figure 2 shows the implementation of glitch filtering.
–8–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DA T A
ADM1060 INPUTS ADM1060
PROGRAMMING THE SFD’S ON THE SMBUS
The details of using the SMBus are described later, but
the register names associated with the Supply Fault Detector blocks, the bitmap of those registers, and the function
of each of the bits is described in the following tables.
The tables show how to set up UV threshold, UV hysteresis, OV threshold, OV hysteresis, glitch filtering and
fault type for each of the SFD’s on the ADM1060.
PROGRAMMED TIMEOUT
T
0
GLITCH FILTER INPUT
T
GF
PROGRAMMED TIMEOUT
T
0
T
GF
T
0
T
GF
GLITCH FILTER OUTPUT
T
0
T
GF
Figure 3 . Glitch Filtering on the SFD’s
SFD REGISTER NAMES
TABLE 2. LIST OF REGISTERS FOR THE SUPPLY FAULT DETECTORS
Hex Table Name Default Description
Address Power On Value
A0 3 BS1OVTH FFh Overvoltage Threshold for Bipolar Voltage SFD1 (BS1SFD)
A1 4 BS1OVHYST 00h Digital Hysteresis on OV threshold for BS1SFD
A2 5 BS1UVTH 00h Undervoltage Threshold for BS1SFD
A3 6 BS1UVHYST 00h Digital Hysteresis on UV threshold for BS1SFD
A4 7 BS1SEL 00h Glitch filter, Range and Fault Type select for BS1SFD
A8 3 BS2OVTH FFh Overvoltage Threshold for Bipolar Voltage SFD2 (BS2SFD)
A9 4 BS2OVHYST 00h Digital Hysteresis on OV threshold for BS2SFD
AA 5 BS2UVTH 00h Undervoltage Threshold for BS2SFD
A B 6 BS2UVHYST 00h Digital Hysteresis on UV threshold for BS2SFD
A C 7 BS2SEL 00h Glitch filter, Range and Fault Type select for BS2SFD
B0 8 HSOVTH FFh Overvoltage Threshold for High Voltage SFD (HVSFD)
B1 9 HSOVHYST 00h Digital Hysteresis on OV threshold for HVSFD
B2 10 HSUVTH 00h Undervoltage Threshold for HVSFD
B3 11 HSUVHYST 00h Digital Hysteresis on UV threshold for HVSFD
B4 12 HSSEL 00h Glitch filter, Range and Fault Type select for HVSFD
B8 13 PS1OVTH FFh Overvoltage Threshold for Positive Voltage SFD1 (PS1SFD)
B9 14 PS1OVHYST 00h Digital Hysteresis on OV threshold for PS1SFD
B A 15 PS1UVTH 00h Undervoltage Threshold for PS1SFD
B B 16 PS1UVHYST 00h Digital Hysteresis on UV threshold for PS1SFD
B C 17 PS1SEL 00h Glitch filter, Range and Fault Type select for PS1SFD
C0 13 PS2OVTH FFh Overvoltage Threshold for Positive Voltage SFD2 (PS2SFD)
C1 14 PS2OVHYST 00h Digital Hysteresis on OV threshold for PS2SFD
REV. PrJ 11/02
–9–
PRELIMINARY TECHNICAL DA T A
ADM1060 ADM1060 INPUTS
TABLE 2. LIST OF REGISTERS FOR THE SUPPLY FAULT DETECTORS (Contd.)
Hex Table Name Default Description
Address Power On Value
C2 15 PS2UVTH 00h Undervoltage Threshold for PS2SFD
C3 16 PS2UVHYST 00h Digital Hysteresis on UV threshold for PS2SFD
C4 17 PS2SEL 00h Glitch filter, Range and Fault Type select for PS2SFD
C8 13 PS3OVTH FFh Overvoltage Threshold for Positive Voltage SFD3 (PS3SFD)
C9 14 PS3OVHYST 00h Digital Hysteresis on OV threshold for PS3SFD
C A 15 PS3UVTH 00h Undervoltage Threshold for PS3SFD
C B 16 PS3UVHYST 00h Digital Hysteresis on UV threshold for PS3SFD
C C 17 PS3SEL 00h Glitch filter, Range and Fault Type select for PS3SFD
D0 13 PS4OVTH FFh Overvoltage Threshold for Positive Voltage SFD4 (PS4SFD)
D1 14 PS4OVHYST 00h Digital Hysteresis on OV threshold for PS4SFD
D2 15 PS4UVTH 00h Undervoltage Threshold for PS4SFD
D3 16 PS4UVHYST 00h Digital Hysteresis on UV threshold for PS4SFD
D4 17 PS4SEL 00h Glitch filter, Range and Fault Type select for PS4SFD
–10–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DA T A
ADM1060 INPUTS ADM1060
SFD REGISTER BITMAPS
BIPOLAR SUPPL Y FAIL DETECT (BSnSFD) REGISTERS
TABLE 3. REGISTER A0H,A8H BSnOVTH (POWER- ON DEFAULT FFH)
Bit Name R/W Description
7-0 OV7-OV0 R/W 8 bit digital value for overvoltage threshold on BSn SFD.
TABLE 4. REGISTER A1H,A9H BSnOVHYST (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7-5 Reserved N/A Cannot be used
4-0 HY4-HY0 R/ W 5 bit digital value for hysteresis on OV threshold of BSn SFD
TABLE 5. REGISTER A2H,AAH BSnUVTH (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7-0 UV7-UV0 R/W 8 bit digital value for undervoltage threshold on BSn SFD
TABLE 6. REGISTER A3H,ABH BSnUVHYST (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7-5 Reserved N/A Cannot be used
4-0 HY4-HY0 R/ W 5 bit digital value for hysteresis on UV threshold of BSn SFD
TABLE 7. REGISTER A4H,ACH BSnSEL (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7 POL R/W Polarity of Bipolar SFDn
POL Sign of Detection Range
0 Positive
1 Negative
6-4 GF2-GF0 R/W GF2 GF1 GF0 Glitch Filter Delay (
0000
0015
01010
01120
10030
10150
11075
111100
3 Reserved N /A Cannot be used
2 RSEL R/W Note: When POL is set to 1 (ie) SFD is in negative mode, then
RSEL is unused since there is only one range in this mode.
RSEL1 Bottom of Top of Step Size (mV)
Range Range
0 1V 3V 7.8
1 2V 6V 15.6
1-0 FS1-FS0 R/W FS1 FS0 Fault Select Type
0 0 Overvoltage
0 1 Undervoltage
1 0 Out-of-Window
1 1 Not Allowed
s)
REV. PrJ 11/02
–11–
PRELIMINARY TECHNICAL DA T A
ADM1060 ADM1060 INPUTS
HIGH VOLTAGE SUPPLY FAULT DETECT (HVSFD) REGISTERS
TABLE 8. REGISTER B0H HSOVTH (POWER- ON DEFAULT FFH)
Bit Name R/W Description
7-0 OV7-OV0 R/W 8 bit digital value for overvoltage threshold on HV SFD.
TABLE 9. REGISTER B1H HSOVHYST (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7-5 Reserved N/A Cannot be used
4-0 HY4-HY0 R/ W 5 bit digital value for hysteresis on OV threshold of HV SFD
TABLE 10. REGISTER B2H HSUVTH (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7-0 UV7-UV0 R/W 8 bit digital value for undervoltage threshold on HV SFD
TABLE 11. REGISTER B3H HSUVHYST (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7-5 Reserved N/A Cannot be used
4-0 HY4-HY0 R/ W 5 bit digital value for hysteresis on UV threshold of HV SFD
TABLE 12. REGISTER B4H HSSEL (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7 Reserved N /A Cannot be used
6-4 GF2-GF0 R/W GF2 GF1 GF0 Glitch Filter Delay (
0000
0015
01010
01120
10030
10150
11075
111100
3 Reserved N /A Cannot be used
2 RSEL W RSEL Bottom of Top of Step Size (mV)
Range Range
0 2V 6V 15.6
1 4.8V 14.4V 37.6
1-0 FS1-FS0 W F S1 FS0 Fault Select Type
0 0 Overvoltage
0 1 Undervoltage
1 0 Out-of-Window
1 1 Not Allowed
s)
–12–
REV. PrJ 11/02
PRELIMINARY TECHNICAL DA T A
ADM1060 INPUTS ADM1060
POSITIVE VOL T AGE SUPPL Y FA ULT DETECT (PSNSFD) REGISTERS
TABLE 13. REGISTER B8H,C0H,C8H,D0H PSNOVTH (POWER- ON DEFAULT FFH)
Bit Name R/W Description
7-0 OV7-OV0 R/W 8 bit digital value for overvoltage threshold on PSn SFD.
TABLE 14. REGISTER B9H,C1H,C9H,D1H PSnOVHYST (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7-5 Reserved N/A Cannot be used
4-0 HY4-HY0 R /W 5 bit digital value for hysteresis on OV threshold of PSn SFD
TABLE 15. REGISTER BAH,C2H,CAH,D2H PSnUVTH (POWER- ON DEFAULT 00H)
Bit Name W Description
7-0 UV7-UV0 R/W 8 bit digital value for undervoltage threshold on PSn SFD
TABLE 16. REGISTER BBH,C3H,CBH,D3H PSnUVHYST (POWER- ON DEFAULT 00H)
Bit Name W Description
7-5 Reserved N/A Cannot be used
4-0 HY4-HY0 R /W 5 bit digital value for hysteresis on UV threshold of PSn SFD
TABLE 17. REGISTER BCH,C4H,CCH,D4H PSnSEL (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7 Reserved N/ A Cannot be used
6-4 GF2-GF0 R/W GF2 GF1 GF0 Glitch Filter Delay (
0000
0015
01010
01120
10030
10150
11075
111100
3-2 RSEL1-RESL0 R/W RSEL1 RSEL0 Bottom of Top of Step Size (mV)
Range Range
0 0 2V 6V 15.6
011V 3V7.8
1 X 0.6V 1.8V 4.7
1-0 FS1-FS0 R/W FS1 FS0 Fault Select Type
0 0 Overvoltage
0 1 Undervoltage
1 0 Out-of-Window
1 1 Not Allowed
s)
REV. PrJ 11/02
–13–
PRELIMINARY TECHNICAL DA T A
ADM1060 ADM1060 INPUTS
WATCHDOG FAULT DETECTOR
The ADM1060 has a Watchdog Fault Detector. This can
be used to monitor a processor clock to ensure normal
operation. The detector monitors the WDI pin, expecting
there to be a low-to-high or high to low transition within a
preprogrammed period. The watchdog timeout period
can be programmed from 200msec to a maximum of
12.8sec.
can also be inverted, if required (eg) if a high- low- high
pulse was required by a processor to reset. Thus, a fault
on the watchdog can be used to generate a pulsed or
latched output on any or all of the 9 PDO’s.
The latched signal can be cleared low by reading LATF1,
then LATF2 across the SMBus interface (see Fault Registers section). The RAM register list and the bit map for
the Watchdog Fault Detector are shown below.
If no transition is detected, 2 signals are asserted. One is
a latched high signal, indicating a fault has occurred. The
other signal is a low- high- low pulse which can be used as
a RESET signal for a processor core. The width of this
pulse can be programmed (from 10s to a maximum of
10ms). These two Watchdog signals can be selected as
inputs to each of the PLB’s (see PLBA section). They
TABLE 18. LIST OF REGISTERS FOR WATCHDOG FAULT DETECTOR
Hex Table Name Defa u lt Description
Address Power On Value
9C 19 WDCFG 00h Program length Watchdog timeout and length of pulsed output
TABLE 19. REGISTER 9CH WDCFG (POWER- ON DEFAULT 00H)
Bit Name R/W Description
7-5 Reserved R/ W Unused
4-3 PULS1-PULS0 R/W Length of pulse outputted once the Watchdog Detector has timed out
PULS1 PULS0 Pulse Length Selected (
0010
0 1 100
1 0 1000
1 1 10000
2-0 PER3-PER0 R/W Watchdog Timeout Period
PER2 PER1 PER0 Watchdog Timeout selected (ms)
0 0 0 Disabled
001 200
010 400
011 800
1 0 0 1600
1 0 1 3200
1 1 0 6400
1 1 1 12800
s)
–14–
REV. PrJ 11/02
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