ANALOG DEVICES ADM1041A Service Manual

Secondary-Side Controller with

FEATURES

Digital calibration via internal EEPROM
Supports SSI specification
Comprehensive fault detection

Reduced component count on secondary side
Standalone or microcontroller control

SECONDARY-SIDE FEATURES

Generates error signal for primary-side PWM
Output voltage adjustment and margining
Current sharing
Current-limit adjustment
OrFET control
Programmable soft-start slew rate
Standalone or microcontroller operation
Differential load voltage sense
AC mains undervoltage detection (ac sense)

Overvoltage protection

Current Share and Housekeeping

ADM1041A

INTERFACE AND INTERNAL FEATURES

SMBus interface (I2C-compatible)
Voltage-error amplifier
Differential current sense
Sense resistor or current transformer option
Overvoltage protection
Undervoltage protection
Overcurrent protection
Overtemperature protection
Start-up undervoltage blanking
Programmable digital debounce and delays
352-byte EEPROM available for field data
160-byte EEPROM for calibration

Ground continuity monitoring

APPLICATIONS

Network servers
Web servers
Power supply control

RS

V

OTP

DD

BIAS

THERMISTOR

PWM

CONTROLLER

V

DD

ISOLATION BARRIER

V

DD

V

DD

Figure 1. Typical Application Circuit

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

OrFET

R

V

DD

ADM1041A

CBD

CS–/V

LS

C

+

S

V

DD

V

CMP

ICT
PULSE

AC_OK
DC_OK

MON2
PEN

C

CMP

SCMP
GND

SHRO
SHRS

V

V

PSON
ADD0

SCL

SDA

F

G

F

D

+

S

–

S

SHARE BUS

MICRO-

CONTROLLER

OPTIONAL

V

OUT

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

V

OUT

LOAD

GND

VS+
V

S

V

DD

–

05405-001

ADM1041A

TABLE OF CONTENTS

General Description ......................................................................... 3

I

Error Amplifier................................................................. 22

SHARE

Sample Application Circuit Description ................................... 3

Specifications..................................................................................... 6

Absolute Maximum Ratings.......................................................... 13

Thermal Characteristics ............................................................13

ESD Caution................................................................................ 13

Pin Configuration and Function Descriptions........................... 14

Terminology ................................................................................ 16

Theory of Operation ...................................................................... 18

Power Management.................................................................... 18

Gain Trimming and Configuration ......................................... 18

Differential Remote Sense Amplifier....................................... 19

Set Load Voltage ......................................................................... 19

Load Overvoltage (OV) ............................................................. 19

Local Voltage Sense .................................................................... 19

Local Overvoltage Protection (OVP) ...................................... 19

I

Clamp ................................................................................ 22

SHARE

SHARE_OK Detector ................................................................ 23

Pulse/AC

2............................................................................. 24

SENSE

Pulse ............................................................................................. 24

AC

.......................................................................................... 24

SENSE

OrFET Gate Drive...................................................................... 25

Oscillator and Timing Generators............................................... 27

Logic I/O and Monitor Pins...................................................... 27

SMBus Serial Port....................................................................... 30

Microprocessor Support............................................................ 30

Broadcasting................................................................................ 30

SMBus Serial Interface............................................................... 30

General SMBus Timing............................................................. 31

SMBus Protocols for RAM and EEPROM.............................. 33

SMBus Read Operations ........................................................... 35

Local Undervoltage Protection (UVP).................................... 19

False UV Clamp.......................................................................... 19

Voltage Error Amplifier............................................................. 20

Main Voltage Reference............................................................. 20

Current-Sense Amplifier ........................................................... 20

Current Sensing.......................................................................... 21

Current-Transformer Input ...................................................... 21

Current-Sense Calibration ........................................................ 21

Current-Limit Error Amplifier................................................. 21

Overcurrent Protection ............................................................. 22

Current Share.............................................................................. 22

Current-Share Offset.................................................................. 22

I

Drive Amplifier ................................................................ 22

SHARE

Differential Sense Amplifier ..................................................... 22

REVISION HISTORY

7/05—Revision 0: Initial Version

SMBus Alert Response Address (ARA) .................................. 36

Support for SMBus 1.1............................................................... 36

Layout Considerations............................................................... 36

Power-Up Auto-Configuration ................................................ 36

Extended SMBus Addressing.................................................... 37

Backdoor Access......................................................................... 37

Register Listing ............................................................................... 38

Detailed Register Descriptions ..................................................... 39

Manufacturing Data................................................................... 48

Microprocessor Support ................................................................ 49

Test Name Table.............................................................................. 51

Outline Dimensions....................................................................... 53

Ordering Guide .......................................................................... 53

Rev. 0 | Page 2 of 56

ADM1041A

GENERAL DESCRIPTION

The ADM1041A is a secondary-side and management IC spec­ifically designed to minimize external component counts and to
eliminate the need for manual calibration or adjustment on the
secondary-side controller. The principle application of this IC is
to provide voltage control, current share, and housekeeping
functions for single output in N+1 server power supplies.

The ADM1041A is manufactured with a 5 V CMOS process
and combines digital and analog circuitry. An internal
EEPROM provides added flexibility for trimming timing and
voltage and selecting various functions. Programming is done
via an SMBus serial port that also allows communication
capability with a microprocessor or microcontroller.

The usual configuration using this IC is on a one-per-output
voltage rail. Output from the IC can be wire-OR’ed together or
bused in parallel and read by a microprocessor. A key feature on
this IC is support for an OrFET circuit when higher efficiency
or power density is required.

SAMPLE APPLICATION CIRCUIT DESCRIPTION

Figure 1 shows a sample application circuit using the
ADM1041A. The primary side is not detailed and the focus is
on the secondary side of the power supply.

The ADM1041A controls the output voltage from the power
supply to the designed programmed value. This programmed
value is determined during power supply design and is digitally
adjusted via the serial interface. Digital adjustment of the
current sense and current limit is also calibrated via the serial
interface, as are all of the internal timing specifications.

The control loop consists of a number of elements, notably the
inputs to the loop and the output of the loop. The ADM1041A
takes the loop inputs and determines what, if any, adjustments

are needed to maintain a stable output. To maintain a stable
loop, the ADM1041A uses three main inputs:

• Remote voltage sense

• Load current sense

• Current sharing information

In this example, a resistor divider senses the output current as a
voltage drop across a sense resistor (RS) and feeds a portion
into the ADM1041A. Remote local voltage sense is monitored

+ and VS− pins. Finally, current sharing information is fed

via V

S

back via the share bus. These three elements are summed
together to generate a control signal (V
loop via an optocoupler to the primary side PWM controller.

), which closes the

CMP

Another key feature of the ADM1041A is its control of an
OrFET. The OrFET causes lower power dissipation across the
OR'ing diode. The main function of the OrFET is to disconnect
the power supply from the load in the event of a fault occurring
during steady state operation, for example, if a filter capacitor or
rectifier fails and causes a short. This eliminates the risk of
bringing down the load voltage that is supplied by the redun­dant configuration of other power supplies. In the case of a
short, a reverse voltage is generated across the OrFET. This
reverse voltage is detected by the ADM1041A and the OrFET is
shut down via the F

pin. This intervention prevents any

G

interruption on the power supply bus. The ADM1041A can
then be interrogated via the serial interface to determine why
the power supply has shut down.

This application circuit also demonstrates how temperature can
be monitored within a power supply. A thermistor is connected
between the VDD and MON2 pins. The thermistor’s voltage
varies with temperature. The MON2 input can be programmed
to trip a flag at a voltage corresponding to an overheating power
supply. The resulting action may be to turn on an additional
cooling fan to help regulate the temperature within the power
supply.

PWM +

PRIMARY

DRIVER

OPTO-

COUPLER

AC PULSE

SENSE

ERROR

AMP

VOLT, TEMP MONITOR

AND FAULT DETECTION

ADM1041A

Figure 2. Application Block Diagram

DIFF CURRENT

SOFT

START

EEPROM AND

RAM AND TRIM

SENSE

SENSE

OrFET

CONTROL

CURRENT

SHARE

DIFF LOAD AND LOCAL

VOLTAGE SENSE

SMBus

LOAD

SHARE

BUS

(μC OR STANDALONE

OPERATION)

μC

R

Differences Between the ADM1041A and ADM1041

For all new designs, it is recommended to use the ADM1041A.

The parts differ as follows:

• The ADM1041 allows the internal VREF voltage reference to

be accessed at Pin 18. This is not accessible using the
ADM1041A.

• The ADM1041A has longer V

OK debounce and VDDOV

DD

debounce than the ADM1041.

• The GND_OK Disable bit (Register 11h) does not disable

when using the ADM1041. It does disable when using the
ADM1041A.

05405-002

Rev. 0 | Page 3 of 56

ADM1041A

OUT

V

DRAINSOURCE

GATE

+ 10V

OUT

V = V

R1

R2

23

SHRS+

50kΩ

/SHRS–

S–

V

REMOTE

20

50kΩ

50kΩ

–VE SENSE

GAIN = (R1 + R2)/R2

50kΩ

50mV 50mV

SHARE BUS

1N4148

12V

DD

V

G

F

19

POLARITY

ORFET CONTROL

OrFET OK

REVERSEOK

ERROR

AMPLIFIER

SHARE

I

SCMP

22

SHARE

I

CLAMP

DRIVE

SHARE

I

SHRO

24

60μA

AMPLIFIER

SENSE

DIFFERENTIAL

CURRENT

REF

R

Q

CLK

1 mSec

R

V

AC SENSE

PENOK

LOADVOK

D

F

63

LS

/V

2

–/FS

S

C

+

S

C

PULSEOK

SQ

R

Q

CLK

1 Sec

REVERSE

VOLTAGE

DETECTOR

AC_OK

SQ

R

TO VOLTAGE ERROR AMP

DD

V

REF

V

,

SHARE

SHARE

OFFSET

(V

IOUT = 0)

CURRENT

REG 17h b7

9R

IRS/

R

SET

CURRENT

ICT

SHARE

ERROR AMP

CURRENT-LIMIT

V

SHAREOK

REF

LIMIT LEVEL

SET CURRENT-

CURRENT SHARE

SET GAIN

0.525V

1

SENSE

PULSE

AC

1.5V

SENSE

SELECT

AC

5.3kΩ

9

5.3kΩ

2

SENSE

AC

10

TRIM

HYSTERESIS

GAIN = 10

40kΩ

8

ICT

SENSE

CURRENT-

TRANSFORMER

CONFIGURATON

4

CMP

C

CURRENT

TRANSFORMER

CURRENT SENSE

05405-003

Figure 3. ADM1041A Diagram, Part 1

Rev. 0 | Page 4 of 56

ADM1041A

LINK

CMP

V

5

VOLTAGE

ERROR AMP

OTP/

MON5

18

MON1

MON2

MON3

MON4

9

16

10

PSON

16

AC_OK

DC_OK

171718

CBD/ALERT

11

PEN

12

70μA

ON

SCL/

AC_OKLink

ADD0

SDA/

PS

151413

CS

SCL

PEN

SERIAL

INTERFACE

LINES

CONTROL

LOGIC AND GPIO

1V 3V

CURRENT LIMIT

DIFF. VOLTAGE SENSE

CURRENT SHARE CAPTURE

REF

1.5V

V

RAMP UP

SOFT-START

2.5V

VOLTAGE ERROR AMP

MON5

OCP

1.25V

AC_OK

OK

DD

V

DC_OK

OV

DD

V

CBD

CONFIGURE

CONTROL

REGISTERS

PWRON

STATUS

CONFIGURE

(READ

REGISTERS)

(WRITE

REGISTERS)

LOGIC

PENOK

MON4

AC_OK

ORFETOK

PSON

CLOCK

SHAREOK

RESET

MON1

MON2

MON3

GENERAL

OVP

UVP

I/Os

PEN

OCP

1.25V

AC_OK

PENOK

ORFETOK

SHAREOK

OCPF

OV

OK

DD

DD

V

V

LOADVOK

REF

V

1.25V

UVP

OVP

2.5V

1.25V

POWER MANAGEMENT

INTERNAL

REFERENCE

SET LOAD

OVERVOLTAGE

CLAMP

FALSE UV

1.5V

EXTREFOK

REFERENCE

MONITOR

INTREFOK

SQ

S

RQ

RQ

SET

LOAD

VOLTAGE

35kΩ

35kΩ

1.3

35kΩ

×

35kΩ

SET UV CLAMP

SET OVP

THRESHOLD

SET UVP

THRESHOLD

AUXILIARY

THRESHOLD

MAIN

BAND GAP

REFERENCE

POR

UVLLO

UVLHI

10μs–20μs

OVP

GNDOK

GROUND

MONITOR

gndok_dis

0.2V

21

+

S

V

REMOTE

FROM

SENSE

LOAD

20

–

S

V

2

LS

V

VOLTAGE SENSE

1

DD

V

ANALOG I/O PIN

HIGH VOLTAGE

NOTES:

1.

2.0V

6.0V–6.5V

XX

XX

ARE DIGITALLY

PROGRAMMBALE

STANDARD I/O PIN

2.

ALL POTENTIOMETERS ( )

3.

THROUGH REGISTERS

7

20

–

S

V

GND

05405-004

4.4V

4.0V

Figure 4. ADM1041A Diagram, Part 2

Rev. 0 | Page 5 of 56

ADM1041A

SPECIFICATIONS

TA = –40 to +85°C, VDD = 5 V ± 10%, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLIES

VDD 4.5 5.0 5.5 V
IDD, Current Consumption 6 10 mA
Peak I

during EEPROM Erase Cycle

DD,

UNDERVOLTAGE LOCKOUT, VDD

1, 2

40 mA

Start-Up Threshold 4 4.3 4.5 V
Stop Threshold 3.7 4 4.2 V
Hysteresis 0.3 V

POWER BLOCK PROTECTION

VDD Overvoltage 5.8 6.2 6.5 V
VDD Overvoltage Debounce 300 500 700 μs Latching
Open Ground 0.1 0.2 0.35 V V
VDDOK Debounce 250 400 500 μs VDDOK

POWER-ON RESET

DC Level 1.5 2.2 2.75 V VDD rising

DIFFERENTIAL LOAD VOLTAGE SENSE INPUT,

−, VS+)

(V

S

VS− Input Voltage 0.5 V Voltage on Pin 20
VS+ Input Voltage VDD – 2 V Voltage on Pin 21
VS− Input Resistance 35 kΩ
VS+ Input Resistance 500 kΩ
V

Adjustment Range 1.7 to 2.3 V

NOM

Set Load Voltage Trim Step 0.10 to 0.14 % 1.7 V ≤ V

1.74 to 3.18 mV 8 bits, 255 steps
Reg 19h[7:0]. See Table 34
Set Load Overvoltage Trim Range 105 to 120 % 1.7 V ≤ V
Set Load Overvoltage Trim Step 0.09 % 8 bits, 255 step/s

1.6 mV Reg 08h[7:0]. See Table 17.
V
Recover from Load OV False to FG True 100 μs Reg 03h[1:0] = 00. See Table 12.
200 μs Reg 03h[1:0] = 01. See Table 12.
300 μs Reg 03h[1:0] = 10. See Table 12.
400 μs Reg 03h[1:0] = 11. See Table 12.
Operate Time from Load OV to FG False 2 μs

See Figure 9.

positive with respect to VS−

GND

See

Figure 6. V

= (VS+ – VS−); V

NOM

is typically 2 V

≤ 2.3 V typ

NOM

≤ 2.3 V min

NOM

+ = 2.24 V

S

NOM

Rev. 0 | Page 6 of 56

ADM1041A

Parameter Min Typ Max Unit Test Conditions/Comments

LOCAL VOLTAGE SENSE, VLS,

See

AND FALSE UV CLAMP

Input Voltage Range3 2.3 (VDD – 2) V Set by external resistor divider.
Stage Gain 1.3 At VLS = 1.8 V
False UV Clamp, VLS, Input Voltage Nominal,

1.3 1.85 2.1 V

and Trim Range

Clamp Trim Step 0.2 % V
Clamp Trim Step 3.1 mV

Local Overvoltage 1.9 2.4 2.85 V

Nominal and Trim Range
OV Trim Step 0.15 % V
OV Trim Step 3.7 mV

Noise Filter, for OVP Function Only 5 25 μs

Local Undervoltage 1.3 1.7 2.1 V

Nominal and Trim Range
UV Trim Step 0.18 % V
UV Trim Step 3.1 mV

Noise Filter, for UVP Function Only 300 600 μs

VOLTAGE ERROR AMPLIFIER, V

Reference Voltage V

REF_SOFT_START

See Figure 15.

CMP

1.49 1.51 V TA = 25°C
Temperature Stability2 ±100 μV/°C −40°C ≤ TA ≤ 85°C
Long-Term Voltage Stability2 ±0.2 % Over 1,000 hr, TJ = 125°C
Soft-Start Period Range 0 40 ms Ramp is 7 bit, 127 steps
Set Soft-Start Period 300 μs Reg 10h[3:2] = 00. See Table 25.
10 ms Reg 10h[3:2] = 01. See Table 25.
20 ms Reg 10h[3:2] = 10. See Table 25.
40 ms Reg 10h[3:2] = 11. See Table 25.
Unity Gain Bandwidth, GBW 1 MHz See Figure 11.
Transconductance 1.9 2.7 3.5 mA/V At I
Source Current 250 μA At V
Sink Current 250 μA At V

DIFFERENTIAL CURRENT SENSE INPUT,

−, CS+

C

S

Reg 17h[7] = 0. See

Common-Mode Range 0 (VDD – 2) V Set by external divider
External Divider Tolerance Trim Range

−5 mV Reg 16h[5:3] = 000. See

(With Respect to Input)

−10 mV Reg 16h[5:3] = 001. See Table 31.

−20 mV Reg 16h[5:3] = 010. See Table 31.
5 mV Reg 16h[5:3] = 100. See Table 31.
10 mV Reg 16h[5:3] = 101. See Table 31.
20 mV Reg 16h[5:3] = 110. See Table 31.
External Divider Tolerance Trim Step Size 20 μV VCM = 2.0 V
(With Respect to Input) 39 μV 8 bits, 255 steps
78 μV Reg 14h[7:0]. See Table 29.

Figure 9.

RANGE

8 bits, 255 steps, Reg 18h[7:0].

Table 33.

See

RANGE

8 bits, 255 steps Reg 0Ah[7:0].

Table 19.

See

RANGE

8 bits, 255 steps, Reg 09h[7:0]. See
Table 18.

= ±180 μA

VCMP

> 1 V

VCMP

< VDD − 1 V

VCMP

Table 18.

I

mode. See Figure 13.

SENSE

Table 31.

Rev. 0 | Page 7 of 56

ADM1041A

Parameter Min Typ Max Unit Test Conditions/Comments

DC Offset Trim Range (with Respect to Input) −8 mV Reg 17h[2:0] = 000. See Table 32 .

−15 mV Reg 17h[2:0] = 001. See Table 32.

−30 mV Reg 17h[2:0] = 010. See Table 32.
8 mV Reg 17h[2:0] = 100. See Table 32.
15 mV Reg 17h[2:0] = 101. See Table 32.
30 mV Reg 17h[2:0] = 110. See Table 32.
DC Offset Trim Step Size 30 μV VCM = 2.0 V, V
(with respect to input) 50 μV 8 bits, 255 steps
120 μV Reg 15h[7:0]. See Table 30.

CURRENT SENSE CALIBRATION

Total Current Sense Error2

(Gain and Offset)

= 2.0V, 0°C ≤ TA ≤ 85°C,

V

CSCM

SHRS = SHRO = 2 V. Gain = 230x.
±3 % Chopper on
±6 % Chopper off
Gain Range (I

) Max input voltage range at CS+, CS−

SENSE

Gain Setting 1 (Reg 16h[2:0] = 000) 65 V/V 34 mV – 44.5 mV. Gain = 65×.
Gain Setting 2 (Reg 16h[2:0] = 001) 85 V/V 26 mV – 34 mV. Gain = 85×.
Gain Setting 3 (Reg 16h[2:0] = 010) 110 V/V 20 mV – 26 mV. Gain = 110×.
Gain Setting 4 (Reg 16h[2:0] = 100) 135 V/V 16 mV – 20 mV. Gain = 135×.
Gain Setting 5 (Reg 16h[2:0] = 101) 175 V/V 12 mV – 16 mV. Gain = 175×.
Gain Setting 6 (Reg 16h[2:0] = 110) 230 V/V 9.5 mV – 12 mV. Gain = 230×
Full Scale (No Offset) 2.0 V VZO = 0
Attenuation Range 65 to 99 % Reg 06h[7:1]. See Table 15.
Current Share Trim Step (at SHRO) 0.4 % SHRS = SHRO = 1 V
8 mV 7 bits, 127 steps I
Gain Accuracy

Gain Accuracy

2, 4

, 40 mV at CS+, CS− −5 +5 %

2, 4

, 20 mV at CS+, CS− −5 ±1 +5 %

0 V ≤ V

CSCM

V

= input common mode.

CSCM

= 2.0 V, 0°C ≤ TA ≤ 85°C.

V

CSCM

Gain = 135×
Gain Accuracy

2, 4

, 40 mV at CS+, CS– −2.5 ±0.5 +2.5 %

= 2.0 V, 0°C ≤ TA ≤ 85°C.

V

CSCM

Gain = 65×

SHARE BUS OFFSET See Figure 13.

Current Share Offset Range 1.25 V

Reg 17h[7] = 1. See

Reg 17h[5] = 1. See
Zero Current Offset Trim Step 0 ≤ V

TRIM

0.4 % 8 bits, 255 steps, VCT = 1.0 V

5.5 mV Reg 05h[7:0]. See Table 14.

CURRENT TRANSFORMER SENSE INPUT, ICT

Reg 17h[7] = 1. See

Reg 06h = FEh. See
Gain Setting 0 4.5 V/V

Reg 17h[5] = 0, V

See Table 31
Gain Setting 1 2.57 V/V

Reg 17h[5] = 1. See

Reg 15h = 05h, approx 1 μA.

See Table 30. V
CT Input Sensitivity 0.45 0.5 0.68 V Gain setting = 4.5
CT Input Sensitivity 0.79 1.0 1.20 V Gain setting = 2.57
Input Impedance2 20 50 kΩ
Source Current 2.0 μA

Current-Transformer Input

See

Section.
Source Current Step Size 170 nA 15 steps Reg 15h[3:0]. See Table 30.
Reverse Current for Extended SMBus

Addressing (Source Current)

5

3.5 5 7 mA

Figure 38 and the Absolute

See

Maximum Ratings section.

= 0 V

DIFF

slope

SHARE

≤ 0.3 V. Gain = 65×.

Table 32.
Table 32.

≤ 1.25 V

Table 32.

Table 15.

= 2 V.

SHARE

Table 32.

= 2 V.

SHARE

Rev. 0 | Page 8 of 56

ADM1041A

Parameter Min Typ Max Unit Test Conditions/Comments

CURRENT LIMIT ERROR AMPLIFIER See Figure 13

Current Limit Trim Range2 105 130 % After I
Current Limit Trim Step 1.1 %
Current Limit Trim Step 26.5 mV

2.0 ≤ V

Reg 04h[7:3]. See
Transconductance 100 200 300 μA/V I
Output Source Current 40 μA V
Output Sink Current 40 μA V

CCMP

CCMP

CCMP

CURRENT SHARE DRIVER See Figure 15

Output Voltage6 (VDD – 0.4) V RL = 1 kΩ, V
Short Circuit Source Current 55 mA
Source Current 15 mA

Current at which V

by more than 5%
Sink Current 60 100 μA V

CURRENT SHARE DIFFERENTIAL SENSE

See

SHARE

AMPLIFIER

VS– Input Voltage 0.5 V Voltage on Pin 20
V

Input Voltage VDD – 2 V Voltage on Pin 23

SHRS

Input Impedance2 65 100 kΩ V

SHRS

Gain 1.0 V/V

CURRENT SHARE ERROR AMPLIFIER

Transconductance, SHRS to SCMP 100 200 300 μA/V I
Output Source Current 40 μA V
Output Sink Current 40 μA V

SCMP

SCMP

SCMP

Input Offset Voltage 40 50 60 mV Master/slave arbitration

Share OK Window Comparator Threshold SHRS = 2 V ± SHR
(Share Drive Error) ±100 mV Reg 04h[1:0] = 00. See Table 13.
±200 mV Reg 04h[1:0] = 01. See Table 13.
±300 mV Reg 04h[1:0] = 10. See Table 13.
±400 mV Reg 04h[1:0] = 11. See Table 13.

CURRENT LIMIT Figure 10

Current Limit Control Lower Threshold 1.3 V V

CCMP

Current Limit Control Upper Threshold 3.5 V VS+ = 0 V, V

CURRENT SHARE CAPTURE V

SCMP

Current Share Capture Range 0.7 1 1.3 % Reg 10h[5:4] = 00. See Table 25.

1.4 2 2.6 % Reg 10h[5:4] = 01. See Table 25.

2.1 3 3.9 % Reg 10h[5:4] = 10. See Table 25.

2.8 4 5.2 % Reg 10h[5:4] = 11. See Table 25.
Capture Threshold 0.6 1.0 1.4 V

FET OR GATE DRIVE Open-drain N-channel FET

Output Low Level (On) 0.4 V IIO = 5 mA

0.8 V IIO = 10 mA
Output Leakage Current −5 +5 μA

REVERSE VOLTAGE COMPARATOR, FS, FD V

Common-Mode Range 0.25 2.0 (VDD – 2) V

CS−

Voltage set by C

Voltage on C

calibration

SHARE

≤ 2.8 V typ, 5 bits, 31 steps.

SHARE

Table 13.

= ±20 μA. See Figure 12.

= >1 V
= <VDD – 1 V

≤ VDD – 2 V

SHRS

does not drop

OUT

= 2.0 V

Figure 15

= 0.5 V, VS− = 0.5 V

= ±20 μA

> 1 V
< VDD – 1 V

THRESH

= 0.7 V, VS+ = 1.5 V

= 0 V

SCMP

= 3.5 V.

= FS

resistor divider.

S

− pin, TA = 25°C.

S

Rev. 0 | Page 9 of 56

ADM1041A

Parameter Min Typ Max Unit Test Conditions/Comments

Reverse Voltage Detector Turn-Off Threshold VCS− = 2 V for threshold specs
100 mV Reg 03h[7:6] = 00. See Table 12.
150 mV Reg 03h[7:6] = 01. See Table 12.
200 mV Reg 03h[7:6] = 10. See Table 12.
250 mV Reg 03h[7:6] = 11. See Table 12.
Reverse Voltage Detector Turn-On Threshold VCS− = 2 V for threshold specs
20 mV Reg 03h[5:4] = 00. See Table 12.
30 mV Reg 03h[5:4] = 01. See Table 12.
40 mV Reg 03h[5:4] = 10. See Table 12.
50 mV Reg 03h[5:4] = 11. See Table 12.
FD Input Impedance 500 kΩ
FS Input Impedance 20 kΩ

AC

1/AC

SENSE

AC or Bulk Sense

Threshold Voltage 1.25 V
Threshold Adjust Range 1.10 1.40 V

Threshold Trim Step 0.8 % 1.10 ≤ V
10 mV

Hysteresis Adjust Range 200−550 mV V
Hysteresis Trim Step 50 mV

Noise Filter 0.6 1 1.2 ms

PULSE-IN

Threshold Voltage 0.525 V
PULSE_OK On Delay 1 μs

PULSE_OK Off Delay 0.8 1 1.2 s
OSCILLATOR −5 +5 % Unless otherwise specified
OCP

OCP Threshold Voltage2 0.3 0.5 0.7 V Force C

Reg 11h[2] = 0. See Table 26.

OCP Shutdown Delay Time (Continuous

Period in Current Limit)
2 s Reg 12h[4:3] = 01. See Table 27.
3 s Reg 12h[4:3] = 10. See Table 27.
4 s Reg 12h[4:3] = 11. See Table 27.
OCP Fast Shutdown Delay Time 0 100 ms

MON1, MON2, MON3, MON4

Sense Voltage 1.21 1.25 1.29 V
Hysteresis 0.1 V
OVP Noise Filter 5 25 μs
UVP Noise Filter 300 600 μs

OTP (MON5) Reg 0Fh[4:2] = 01x or 10x. See Table 24.

Sense Voltage Range 2.2 2.45 V
OTP Trim Step 24 mV 2.1 ≤ V

Hysteresis 100 130 160 μA V

2 COMPARATOR

SENSE

1 s Reg 12h[4:3] = 00. See

Reg 12h[2] = 0
Reg 0Dh[3:2] = 00. See

Table 22 .

Reg 12h[2] = 1
Reg 0Eh[7:6] = 00. See

Table 23.

Min: DAC = 0
Max: DAC = Full Scale

≤ 1.4 V

TRIM

5 bits, 31 steps
Reg 0Ch[7:3]. See

> 1 V, R

ACSENSE

200 ≤ V

TRIM

Reg 0Ch[2:0]. See

CMP

Table 21.

= 909R

THEVENIN

≤ 550 mV. 7 steps

Table 21.

for drop in V

CMP

Table 27.

Reg 11h[2] = 1. See

= 1.5 V

VC

CMP

≤ 2.45 V

TRIM

Table 26.

4 bits, 15 steps, Reg 0Bh[7:4].

Table 20.

See

= 2 V

OTP

Rev. 0 | Page 10 of 56

ADM1041A

Parameter Min Typ Max Unit Test Conditions/Comments

OVP Noise Filter 5 25 μs

UVP Noise Filter 300 600 μs

PSON7 Reg 0Eh[4:2] = 00x. See Table 23.

Input Low Level8 0.8 V
Input High Level8 2.0 V
Debounce 80 ms Reg 0Fh[1:0] = 00. See Table 24.
0 ms Reg 0Fh[1:0] = 01. See Table 24.
40 ms Reg 0Fh[1:0] = 10. See Table 24.
160 ms Reg 0Fh[1:0] = 11. See Table 24.

PEN7, DC_OK7, CBD, AC_OK

Open-Drain N-Channel Option
Output Low Level = On8 0.4 V I
Open-Drain P-Channel V
Output High Level = On8 2.4 V I
Leakage Current −5 +5 μA

DC_OK7 Reg 0Fh[7:5] = 00x. See Table 24.

DC_OK, On Delay (Power-On and OK Delay) 400 ms Reg 0Eh[1:0] = 00. See Table 23.
200 ms Reg 0Eh[1:0] = 01. See Table 23.
800 ms Reg 0Eh[1:0] = 10. See Table 23.
1600 ms Reg 0Eh[1:0] = 11. See Table 23.
DC_OK, Off Delay (Power-Off Early Warning) 2 ms Reg 10h[7:6] = 00. See Table 25.
0 ms Reg 10h[7:6] = 01. See Table 25.
1 ms Reg 10h[7:6] = 10. See Table 25.
4 ms Reg 10h[7:6] = 11. See Table 25.

SMBus, SDL/SCL

Input Voltage Low8 0.8 V
Input Voltage High8 2.2 V
Output Voltage Low8 0.4 V VDD = 5 V, I
Pull-Up Current 100 350 μA
Leakage Current −5 +5 μA

ADD0, HARDWIRED ADDRESS BIT

ADD0 Low Level8 0.4 V
ADD0 Floating VDD/2 V Floating
ADD0 High8 VDD − 0.5 V

SERIAL BUS TIMING See Figure 5

Clock Frequency 400 kHz
Glitch Immunity, tSW 50 ns
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t

4.7 μs

BUF

4.7 μs

SU;STA

4 μs

HD;STA

4.7 μs

LOW

4 μs

HIGH

SCL, SDA Rise Time, tR 1000 ns
SCL, SDA Fall Time, tF 300 ns
Data Setup Time, t
Data Hold Time, t

250 ns

SU;DAT

300 ns

HD;DAT

EEPROM RELIABILITY

Endurance9 100 250 k cycles
Data Retention10 100 Years

Reg 0Fh[4:2] = 010 or 100.

Table 24.

See
Reg 0Fh[4:2] = 011 or 101.

See Table 24.

= 4 mA

SINK

OH_PEN

= 4 mA

SOURCE

= 4 mA

SINK

Rev. 0 | Page 11 of 56

ADM1041A

A

1

This specification is a measure of IDD during an EEPROM page erase cycle. The current is a dynamic. Refer to Figure 29 for a typical IDD plot during an EEPROM page

erase.

2

This specification is not production tested, but is supported by characterization data at initial product release.

3

Four external divider resistors are the same ratio, which is selected to produce 2.0 V nominal at Pin 21 while at zero load current. Recommended values are

R
R

4

Chopper off.

5

The maximum specification here is the maximum source current of Pin 8 as specified by the Absolute Maximum Ratings.

6

All internal amplifiers accept inputs with common range from GND to VDD − 2 V. The output is rail-to-rail, but the input is limited to GND to VDD − 2 V. See Figure 6.

7

These pins can be configured as open-drain N-channel or P-channel, (except PSON) and as normal or inverted logic polarity.

8

A logic true or false is defined strictly according to the signal name. Low and high refer to the pin or signal voltages.

9

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22, Method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at +25°C is 250,000 cycles.

10

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6 V.

3.3 V 5.0 V 12 V

680R 1K.5 5K1

TOP

1K 1K 1K

BOTTOM

Derates with junction temperature.

SCL

SD

t

t

BUF

PS

HD:STA

t

LOW

t

R

t

HD:DAT

t

F

t

HIGH

t

SU:DAT

S

Figure 5. Serial Bus Timing Diagram

t

SU:STA

t

HD:STA

t

SU:STO

P

05405-005

SHRO

SHRS+

SHRS–

VA = V

R1

VBVAVB = V

R1

R1 + R2 ≥ 1kΩ

Figure 6. Amplifier Inputs and Outputs

DD

DD

– 0.4V

–2V

05405-006

Rev. 0 | Page 12 of 56

ADM1041A

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage (Continuous), VDD 6.5 V

Data Pins SDA, SCL, V

DATA

+ 0.5 V,

V

DD

GND − 0.3 V
Continuous Power at 25°C, P
Operating Temperature, T

AMB

450 mW

D-QSOP24

−40°C to +85°C
Junction Temperature, TJ 150°C
Storage Temperature, T
Lead Temperature

(Soldering, 10 Seconds), T

ESD Protection on All Pins, V

−60°C to +150°C

STG

300°C

L

2 kV

ESD

Thermal Resistance, Junction to Air, θJA 150°C/W
ICT Source Current1 7 mA

1

This is the maximum current that can be sourced out from Pin 8 (ICT pin).

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

24-lead QSOP: θJA = 150°C/W

Rev. 0 | Page 13 of 56

ADM1041A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PULSE/AC

AC

VLS/CS–/FS

1/MON1

SENSE

2/MON2

SENSE

CBD/ALERT

C
V

GND

PEN

V

DD

CS+

CMP
CMP

F

ICT

1
2
3
4
5
6

D

7
8

9
10
11
12

ADM1041A

TOP VIEW

(Not to Scale)

SHRO

24
23

SHRS+

22

SCMP

21

V

+

S

20

V

–/SHRS–

S

19

F

G

18

AC_OK/OTP/MON5

17

DC_OK/MON4

16

PSON/MON3
ADD0

15

SDA/PS

14
13

ON

SCL/AC_OKLink

LINK

05405-007

Figure 7. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Positive Supply for the ADM1041A. Normal range is 4.5 V to 5.5 V. Absolute maximum rating is 6.5 V.
2 VLS/CS–/FS

Inverting Differential Current Sense Input, Local Voltage Sense Pin, and OrFET Source. These three functions
are served by a common divider. The local voltage sense input is used for local overvoltage and undervoltage
sensing. This pin also provides an input to the false UV clamp that prevents shutdown during an external load
overvoltage condition. When supporting an OrFET circuit, this pin represents the FET source and is the
inverting input of a differential amplifier looking for the presence of a reverse voltage across the FET, which
might indicate a failure mode.

3 CS+

Noninverting Differential Current Sense Input. The differential sensitivity of C

+ and CS– is normally around 10

S

mV to 40 mV at the input to the ADM1041A. Nulling any external divider offset is achieved by injecting a
trimmable amount of current into either the inverting or noninverting input of the second stage of the
current sense amplifier. A compensation circuit is used to ensure the amount of current for zero-offset tracks
the common-mode voltage. Nulling of any amplifier offset is done in a similar manner except that it does not
track the common-mode voltage.

4 C

CMP

Current Error Amplifier Compensation. This pin is the output of the current limit transconductance error
amplifier. A series resistor and a capacitor to ground are required for loop compensation.

5 V

CMP

Voltage Error Amplifier Compensation. This is the output of a voltage error transconductance amplifier.
Compensate with a series capacitor and resistor to ground. An external emitter-follower or buffer is typically
used to drive an optocoupler. Output voltage positioning may be obtained by placing a second resistor
directly to ground. Refer to Analog Devices applications notes on voltage positioning.

6 FD

A divider from the OrFET drain is connected here. A differential amplifier is then used to detect the presence
of a reverse voltage across the FET, which indicates a fault condition and causes the OrFET gate to be pulled
low.

7 GND

Ground. This pin is double bonded for extra reliability. If the ground pin goes positive with respect to the
remote sense return (V

–) for a sustained period indicating that the negative remote sense line is

S

disconnected, PEN is disabled.

8 ICT

Input for Current Transformer. The sensitivity of this pin is suitable for the typical 0.5 V to 1 V signal that is
normally available. If this function is enabled, the C

+ amplifier is disabled. This pin is also used for extended

S

SMBus addressing, that is, pulled below ground to allow additional SMBus addresses.

9

PULSE/AC
MON1

SENSE

Pulse Present, AC/Bulk Sense 1, or Monitor 1 Input.

1/

PULSE: This tells the OrFET circuit that the voltage from the power transformer is normal. A peak hold allows
the OrFET circuit to pass through the pulse skipping that occurs with very light loads, but turns off the circuit
about one second after the last pulse is recognized.

1: This sense function also uses the peak voltage on this pin to measure the bulk capacitor voltage. If

AC

SENSE

too low, AC_OK and DC_OK can warn of an imminent loss of power. Threshold level and hysteresis can be
trimmed. When not selected, AC

1 defaults to true.

SENSE

MON1: When MON1 is selected for this pin, its input is compared against a 1.25 V comparator that could be
used for monitoring a postregulated output; includes overvoltage, undervoltage, and overtemperature
conditions.

Rev. 0 | Page 14 of 56

ADM1041A

Pin No. Mnemonic Description

10 AC

11 CBD/ALERT

12 PEN

13 SCL/AC_OKLink SCL: SMBus Serial Clock Input.

14 SDA/PSONLINK SDA: SMBus Serial Data Input and Output.

15 ADD0

16 PSON/MON3

17 DC_OK/MON4

18

19 FG

20 VS–/SHRS–

21 VS+

22 SCMP

2/MON2 AC/Bulk Sense Input 2 or Monitor 2 Input.

SENSE

AC

2: This alternative AC

SENSE

for the OrFET. It also allows dc and optocoupled signals that are not suitable for the OrFET control.
MON2: When MON2 is selected for this pin, its input is compared against a 1.25 V comparator that could be

used for monitoring a postregulated output; includes overvoltage, undervoltage, and overtemperature
conditions.

CBD: The crowbar drive pin allows implementation of a fast shutdown in case of a load overvoltage fault. The
pin can be configured as an open-drain N-channel or P-channel and is suitable for driving a sensitive gate SCR
crowbar. An external transistor is required if a high gate current is needed. Either polarity may be selected.

ALERT: This pin can be configured to provide an ALERT function in microprocessor-supported applications
where any of several ICs in a redundant system that detects a problem can interrupt and shut down the
power supply. An alternative use is as a general-purpose logic output signal.

Power Enable. This pin can be configured as an open-drain N-channel or P-channel that typically drives the
PEN optocoupler. Providing that the PSON pin has been asserted to turn the output on, and that there are no
faults, this pin drives an optocoupler on enabling the primary PWM circuit. Either polarity may be selected.

AC_OKLink: In nonmicroprocessor applications, this pin can be programmed to give the status of AC
the ICs on the same bus. The main effect is to turn on undervoltage blanking whenever the sense circuit
monitoring ac or bulk dc detects a low voltage.

PSONLINK: In non-microprocessor applications, this pin can be programmed to provide the PSON status to
other ICs. This allows just one IC to be the PSON interface to the host system, or the PS
PSON interface.

Chip Address Pin. There are three addresses possible using this pin, which are achieved by tying ADD0 to
ground, tying to V

, or being left to float. One address bit is available via programming at the

DD

device/daughter card level, so the total number of addressable ICs can be increased to six.
PSON: In nonmicroprocessor configurations, this is power supply on. As a standard I/O, this pin is rugged

enough for direct interface with a customer’s system. Either polarity may be selected.
MON3: When MON3 is selected for this pin, its input is compared against a 1.25 V comparator that could be

used for monitoring a postregulated output; includes overvoltage, undervoltage, and overtemperature
conditions.

DC_OK: This pin is the output of a general-purpose digital I/O that can be configured as open-drain
N-channel or open-drain P-channel suitable for wire-OR'ing with other ICs and direct interfacing with a
customer’s system. Either polarity may be selected.

MON4: When MON4 is selected for this pin, its input is compared against a 1.25 V comparator that could be
used for overtemperature protection and for monitoring a postregulated output; includes overvoltage,
undervoltage, and overtemperature conditions.

AC_OK/OTP/
MON5

Buffered Output, Overtemperature Protection, or Monitor 5.
AC_OK: This option can be configured as N-channel or P-channel and as normal or inverted polarity. At

system level, a true AC_OK is used to indicate that the primary bulk voltage is high enough to support the

system and, when false, that dc output is about to fail.
MON5: A further option is to configure this as an analog input, MON5, with a flexible hysteresis and

trimmable 2.5 V reference. This makes the pin particularly suitable for overtemperature protection (OTP)
sensing. Since hysteresis uses a switched 100 μA current source, hysteresis can be adjusted via the source
impedance of the external circuit. It can also be used for OVP and UVP functions.

FET Gate Enable. When supporting an OrFET circuit, this is the gate drive pin. Because the open-drain voltage
on the chip is limited to V

DD

the OrFET. This pin is configured as an open-drain N-channel. Either output polarity, low = on or low = off,
may be selected.

This pin is used as the ground input reference for the current share and load voltage sense circuits. It should
be tied to ground at the common remote sense location. The input impedance is about 35 kΩ to ground.

This pin is the positive remote load voltage sense input and is normally divided down from the power supply
output voltage to 2.0 V at no-load using an external voltage divider. The input impedance is high.

Output of the Current Share Transconductance Error Amplifier. Compensation is a series capacitor and
resistor to ground. While V

DD

enabled (PEN true) and the clamp is released, the compensation capacitor charges, providing a slow walk-in.
The error amplifier input has a built-in bias so that all slaves in a parallel supply system do not compete with
the master for control of the share bus.

input can be used when the AC

SENSE

source must be different from that used

SENSE

LINK itself can be the

ON

SENSE

to all

, an external level shifter is required to drive the higher gate voltages suitable for

is normal and PEN is false, this pin is clamped to ground. When the converter is

Rev. 0 | Page 15 of 56

ADM1041A

Pin No. Mnemonic Description

23 SHRS+

24 SHRO

Table 4. Default Pin States During EEPROM Download

Pin No. Mnemonic State

11 CBD High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).

12 PEN High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).

17 DC_OK Active low (low if DC_OK true) at power-up. This pin is reconfigured during the EEPROM download.
18 AC_OK Active low (low if DC_OK true) at power-up. This pin is reconfigured during the EEPROM download.
19 FG High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).

Current Share Sense. This is the noninverting input of a differential sense amplifier looking at the voltage on
the share bus. For testing purposes, this pin is normally connected to SHRO. Calibration always expects this
pin to be at 2.0 V with respect to SHRS–/V
or an additional gain stage, must be used.

Current Share Output. This output is capable of driving the share bus of several power supplies between 0 V

– 0.4 V (10 kΩ bus pull-down in each supply). Where a higher share bus voltage is required, an

and V

DD

external amplifier is necessary. The current share output from the supply, when bused with the share output
of other power supplies working in parallel, allows each of the supplies to contribute essentially equal
currents to the load.

This pin is reconfigured at the end of the EEPROM download.

This pin is reconfigured at the end of the EEPROM download.

This pin is reconfigured at the end of the EEPROM download.

–. If a higher share voltage is required, a resistor divider from SHRO

S

TERMINOLOGY

Table 5.

Mnemonic Description
POR

UVL

CVMode

CCMode

UVP

OVP

OCP

OTP

UVB

Power-On Reset. When VDD is initially applied to the ADM1041A, the POR function clears all latches and puts
the logic into a state that allows a clean start-up.

Undervoltage Lockout. This is used on VDD to prevent spurious modes of operation that might occur if VDD
is below a specific voltage.

Constant Voltage Mode. This is the normal mode of operation of the power supply main output. The output
voltage remains constant over the whole range of current specified.

Constant Current Mode. This mode of operation occurs when the output is overloaded until or unless a
shutdown event is triggered. The output current control level remains constant down to 0 V.

Undervoltage Protection. If the output being monitored is detected as going under voltage, the UVP function
sends a fault signal. After a delay, PEN goes false, the output is disabled, and either latch-off or an autorestart
occurs, depending on the mode selected. The DC_OK output also goes false immediately to show that the
output is out of tolerance.

Overvoltage Protection. If the output being monitored is detected as going over voltage, the OVP function
latches and sends a fault signal, PEN goes false, and CBD goes true. The DC_OK output also goes false
immediately. OVP faults are always latching and require the cycling of PSON or VDD or SMBus command to
reset the latch.

Overcurrent Protection. If the output being monitored is detected as going over current for a certain time,
the OCP function sends out a fault signal that triggers a shutdown that can be latched or allowed to
autorestart, depending on the mode selected. Prior to shutting down, the DC_OK output goes false warning
the system that output is going to be lost. The latch is the same one used for OVP. For autorestart, the OCP
timeout period is configurable.

Overtemperature Protection. If the temperature being sensed is detected as going over the selected limit, the
OTP function sends out a fault signal that triggers a shutdown that can be latched or allowed to auto-restart
depending on the mode selected. Prior to shutting down, the DC_OK output goes false warning the system
that output is going to be lost. The latch is the same one used for OVP.

Undervoltage Blanking. The UVP function is blanked (disabled) during power-up or if the ACSENSE function is
false (ac line voltage is low). When in constant current mode, UVB is disabled. The status of ACSENSE must be
known to the IC, either by virtue of the on-board ACSENSE or communicated by the SMBus with the help of
an external microprocessor or by using AC_OKLink. When in constant-current mode, due to an overload, UVB
is applied for the overcurrent ride-through period.

Rev. 0 | Page 16 of 56

ADM1041A

Mnemonic Description
DC_OK

AC_OK

DC_OK on delay The DC_OK output is kept false for typically 100 ms to 900 ms during power-up.
DC_OK off delay

Debounce Digital Noise
Filter

ACSENSE1

Pulse OK

AC Hysteresis

ACSENSE2

Soft-Start

VDD–OVP

VDD–UVL

Auto Restart Mode

VREF–MON

GND–MON

The DC_OK function advises the system on the status of the power supply. When it is false, the system is
assured of at least 1 ms of operation if ac power is lost for any reason. Other turn-off modes provide more
warning time. This pin is an open-drain output. It can be configured as a P-channel pull-up or an N-channel
pull-down. It may also be configured as positive or negative (inverted) logic.

The AC_OK function advises the system whether or not sufficient bulk voltage is present to allow reliable
operation. The system may choose to shut down if this pin is false. The power supply normally tries to
maintain normal operation as long as possible, although DC_OK goes false when only a millisecond or so of
operation time is left. This pin is an open-drain output. It can be configured as a P-channel pull-up or an N­channel pull-down. It may also be configured as positive or negative (inverted) logic.

When the system is to be shut down in response to PSON going low, or in response to an OCP or OTP event, a
signal is first sent to the DC_OK output to go false as a warning that power is about to be lost. PEN is signaled
false typically 2 ms later (configurable).

All of the inputs to the logic core are first debounced or digitally filtered to improve noise immunity. The
debounce period for OV events is in the order of 16 μs, for UV events it is 450 μs, and for PSON it is typically
80 ms (configurable).

A voltage from the secondary of the power transformer, which can provide an analog of the bulk supply, is
rectified and lightly filtered and measured by the ac sense function. At start-up, if this voltage is adequate,
this function signals the end-user system that it is okay to start. If a brown-out occurs or ac power is removed,
this function can provide early warning that power is about to be lost and allow the system to shut down in
an orderly manner. While ACSENSE is low, UVB is enabled, which means undervoltage protection is not
initiated. If ac power is so low that the converter cannot continue to operate, other protection circuits on the
primary side normally shut down the converter. When an adequate voltage level is resumed, a power-up
cycle is initiated.

As well as providing ACSENSE, the preceding connection to the transformer is used to gate the operation of
the OrFET circuit. If the output of the transformer is good, the OrFET circuit allows gate drive to the OrFET.

ACSENSE Hysteresis. Configurable voltage on the ACSENSE input allows the ACSENSE upper and lower
threshold to be adjusted to suit different amounts of low frequency ripple present on the bulk capacitor.

An alternate form of ac sense can be accepted by the ADM1041A. This may in the form of an opto-coupled
signal from the primary side where the actual level sensing might be done. As with the above, while ac is low
and UVB is disabled, AC_OK is false and DC_OK is true. Any brownout protection that might be required on
the primary is done on the primary side.

At start-up, the voltage reference to the voltage error amplifier is brought up slowly in approximately 127
steps to provide a controlled rate of rise of the output voltage.

An OVP fault on the auxiliary supply to the ADM1041A causes a standard OVP operation (see the OVP
function in this table).

A UVL fault on the auxiliary supply to the IC causes a standard UVP operation (see the UVP function in this
table).

In this mode, the housekeeping circuit attempts to restart the supply after an undervoltage event at about 1
second intervals. No other fault can initiate auto-restart.

The internal precision reference is monitored by a separate reference for overvoltage and allows truly
redundant OVP. The externally available reference is also monitored for an undervoltage that would indicate
a short on the pin.

The internal ground is constantly monitored against the VS- pin. If the chip ground goes positive with respect
to this pin, it indicates that the chip ground is open-circuit either inside the ADM1041A or the external wiring.
The ADM1041A would be latched off, similar to an OV event.

Rev. 0 | Page 17 of 56