Analog Devices ADM1041 a Datasheet

Secondary-Side Controller with

PRODUCT FEATURES

Digital calibration via internal EEPROM
Supports SSI specification

Comprehensive fault detection
Reduced component count on secondary side
Standalone or microcontroller control

SECONDARY-SIDE FEATURES

Generates error signal for primary-side PWM
Output voltage adjustment and margining
Current sharing
Current limit adjustment
OrFET control
Programmable soft-start slew rate
Standalone or microcontroller operation
Differential load voltage sense
AC mains undervoltage detection (ac sense)
Overvoltage protection

Current Share and Housekeeping

ADM1041

INTERFACE AND INTERNAL FEATURES

SMBus interface (I2C compatible)
Low-drift precision 2.5 V reference
Voltage error amplifier
Differential current sense
Sense resistor or current transformer option
Overvoltage protection
Undervoltage protection
Overcurrent protection
Overtemperature protection
Start-up undervoltage blanking
Programmable digital debounce and delays
352-byte EEPROM available for field data
160-byte EEPROM for calibration

Ground continuity monitoring

APPLICATIONS

Network servers
Web servers
Power supply control

RS

V

OTP

DD

BIAS

THERMISTOR

PWM

CONTROLLER

V

DD

ISOLATION BARRIER

V

DD

V

DD

Figure 1. Typical Application Circuit

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

OrFET

V

OUT

R

LOAD

GND

V

DD

ADM1041

F

G

F

LS

D

SHRO
SHRS

+

V

S

V

–

S

AC_OK
DC_OK

PSON
ADD0

SCL

SDA

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

CBD
CS–/V
C

+

S

V

DD

V

CMP

ICT

PULSE

MON2

PEN

C

CMP

SCMP

GND

SHARE BUS

MICRO-

CONTROLLER

OPTIONAL

V

OUT

VS+

–

V

S

Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

V

DD

04521-0-031

ADM1041

TABLE OF CONTENTS

Specifications..................................................................................... 6

Pulse ............................................................................................. 27

Absolute Maximum Ratings.......................................................... 13

ESD Caution................................................................................ 13

Pin Configuration and Function Descriptions........................... 14

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 19

Power Management.................................................................... 19

Gain Trimming and Configuration ......................................... 19

Differential Remote Sense Amplifier............................................ 20

Set Load Voltage.......................................................................... 20

Load Overvoltage (OV) ............................................................. 20

Local Voltage Sense .................................................................... 20

Local OverVoltage Protection (OVP)...................................... 20

Local UnderVoltage Protection (UVP) ................................... 20

False UV Clamp.......................................................................... 20

Voltage Error Amplifier ............................................................. 21

AC

.......................................................................................... 27

SENSE

OrFET Gate Drive...................................................................... 28

Oscillator and Timing Generators ............................................... 30

Logic I/O and Monitor Pins...................................................... 30

SMBus Serial Port....................................................................... 33

Microprocessor Support............................................................ 33

Broadcasting................................................................................ 34

SMBus Serial Interface............................................................... 34

General SMBus Timing............................................................. 34

SMBus Protocols for RAM and EEPROM.............................. 36

SMBus Read Operations ........................................................... 38

SMBus Alert Response Address (ARA)................................... 39

Support for SMBus 1.1............................................................... 39

Layout Considerations............................................................... 39

Power-Up Auto-Configuration ................................................ 39

Main Voltage Reference ............................................................. 21

Current Sense Amplifier............................................................ 21

Current Sensing.......................................................................... 22

Current Transformer Input....................................................... 22

Current Sense Calibration......................................................... 22

Current Limit Error Amplifier.................................................. 22

Overcurrent Protection .............................................................22

Current Share.................................................................................. 24

Current Share Offset .................................................................. 24

I

Drive Amplifier.................................................................24

SHARE

Differential Sense Amplifier...................................................... 24

I

Error Amplifier................................................................. 24

SHARE

I

Clamp................................................................................. 24

SHARE

Share_ok Detector...................................................................... 24

Pulse/AC

2................................................................................. 27

SENSE

Extended SMBus Addressing.................................................... 40

Backdoor Access......................................................................... 40

Register Listing ............................................................................... 41

Detailed Register Descriptions ..................................................... 42

Manufacturing Data................................................................... 51

Microprocessor Support ................................................................ 52

Trim Table........................................................................................ 54

Appendix A—Configuration Table.............................................. 55

Appendix B—Test Name Table..................................................... 61

Outline Dimensions....................................................................... 64

Ordering Guide .......................................................................... 64

REVISION HISTORY

3/04-

Revision Sp0: Initial Version

5/04-Changed from Rev. Sp0 to Rev. A

Rev. A | Page 2 of 64

ADM1041

GENERAL DESCRIPTION

The ADM1041 is a secondary-side and management IC specifi­cally designed to minimize external component counts and to
eliminate the need for manual calibration or adjustment on the
secondary-side controller. The principle application of this IC is
to provide voltage control, current share, and housekeeping
functions for single output in N+1 server power supplies.

The ADM1041 is manufactured with a 5 V CMOS process and
combines digital and analog circuitry. An internal EEPROM
provides added flexibility in the trimming of timing and voltage
and selection of various functions. Programming is done via an
SMBus serial port that also allows communication capability
with a microprocessor or microcontroller.

The usual configuration using this IC is on a one per output
basis. Outputs from the IC can be wire-ORed together or bused
in parallel and read by a microprocessor. A key feature on this
IC is support for an OrFET circuit when higher efficiency or
power density is required.

SAMPLE APPLICATION CIRCUIT DESCRIPTION

Figure 1 shows a sample application circuit using the ADM1041.
The primary side is not detailed and the focus is on the secon­dary side of the power supply.

The ADM1041 controls the output voltage from the power
supply to the designed programmed value. This programmed
value is determined during power supply design and is digitally
adjusted via the serial interface. Digital adjustment of the
current sense and current limit is also calibrated via the serial
interface, as are all of the internal timing specifications.

The control loop consists of a number of elements, notably the
inputs to the loop and the output of the loop. The ADM1041
takes the loop inputs and determines what, if any, adjustments

PWM +

PRIMARY

DRIVER

are needed to maintain a stable output. To maintain a stable
loop, the ADM1041 uses three main inputs:

• Remote voltage sense

• Load current sense

• Current sharing information

In this example, a resistor divider senses the output current as a
voltage drop across a sense resistor (RS) and feeds a portion
into the ADM1041. Remote local voltage sense is monitored via

+ and VS− pins. Finally, current sharing information is fed

V

S

back via the share bus. These three elements are summed
together to generate a control signal (V

), which closes the

CMP

loop via an optocoupler to the primary side PWM controller.

Another key feature of the ADM1041 is its control of an OrFET.
The OrFET causes lower power dissipation across the ORing
diode. The main function of the OrFET is to disconnect the
power supply from the load in the event of a fault occurring
during steady state operation, for example, if a filter capacitor or
rectifier fails and causes a short. This eliminates the risk of
bringing down the load voltage that is supplied by the redun­dant configuration of other power supplies. In the case of a
short, a reverse voltage is generated across the OrFET. This
reverse voltage is detected by the ADM1041 and the OrFET is
shut down via the F

pin. This intervention prevents any

G

interruption on the power supply bus. The ADM1041 can then
be interrogated via the serial interface to determine why the
power supply has shut down.

This application circuit also demonstrates how temperature can
be monitored within a power supply. A thermistor is connected
between the V

and MON2 pins. The thermistor’s voltage varies

DD

with temperature. The MON2 input can be programmed to trip
a flag at a voltage corresponding to an overheating power supply.
The resulting action may be to turn on an additional cooling
fan to help regulate the temperature within the power supply.

R

SENSE

LOAD

OPTO-

COUPLER

AC PULSE

SENSE

ERROR

AMP

VOLT, TEMP MONITOR

AND FAULT DETECTION

ADM1041

Figure 2. Application Block Diagram

DIFF CURRENT

SENSE

SOFT

START

DIFF LOAD AND LOCAL

EEPROM AND

RAM AND TRIM

Rev. A | Page 3 of 64

OrFET

CONTROL

CURRENT

SHARE

VOLTAGE SENSE

SMBus

SHARE

BUS

(µC OR STANDALONE

OPERATION)

µC

04521-0-002

ADM1041

OUT

V

DRAINSOURCE

GATE

+ 10V

OUT

V = V

R1

R2

23

50kΩ

SHRS+

REMOTE

–VE SENSE

/SHRS–

GAIN = (R1 + R2)/R2

S–

V

20

50kΩ

50kΩ

50kΩ

50mV 50mV

SHARE BUS

1N4148

12V

DD

V

G

F

19

POLARITY

ORFET CONTROL

OrFET OK

REVERSEOK

ERROR

AMPLIFIER

SHARE

I

SCMP

22

SHARE

I

CLAMP

DRIVE

AMPLIFIER

SHARE

I

SHRO

24

60µA

SENSE

DIFFERENTIAL

CURRENT

REF

R

Q

CLK

1 mSec

R

V

AC SENSE

PENOK

LOADVOK

D

F

63

LS

/V

2

–/FS

S

C

+

S

C

PULSEOK

SQ

R

Q

CLK

1 Sec

REVERSE

VOLTAGE

DETECTOR

AC_OK

SQ

R

TO VOLTAGE ERROR AMP

DD

V

REF

V

,

SHARE

SHARE

OFFSET

(V

IOUT = 0)

CURRENT

REG 17h b7

9R

IRS/

SET

CURRENT

ICT

R

SHARE

SHAREOK

ERROR AMP

CURRENT LIMIT

REF

V

SET CURRENT

CURRENT SHARE

LIMIT LEVEL

SET GAIN

0.525V

1

SENSE

PULSE

AC

1.5V

SENSE

SELECT

AC

5.3kΩ

9

5.3kΩ

2

SENSE

AC

10

TRIM

HYSTERESIS

GAIN = 10

40kΩ

8

ICT

SENSE

CURRENT

TRANSFORMER

CONFIGURATON

4

CMP

C

CURRENT

TRANSFORMER

CURRENT SENSE

04521-0-037

Figure 3. Chip Diagram, Part 1

Rev. A | Page 4 of 64

ADM1041

LINK

ON

SCL/

ACONLink

ADD0

SDA/

PS

151413

LOGIC AND GPIO

CS

SCL

PEN

(READ

REGISTERS)

SERIAL

INTERFACE

WRITE

REGISTERS

LINES

CONTROL

70µA

CURRENT LIMIT

CMP

V

5

VOLTAGE

ERROR AMP

1V 3V

CURRENT SHARE CAPTURE

DIFF. VOLTAGE SENSE

1.5V

REF

V

RAMP UP

SOFT START

VOLTAGE ERROR AMP

2.5V

OTP/

MON5

MON5

OCP

1.25V

MON1

9

MON1

OVP

MON2

10

MON2

UVP

MON3

16

MON4

MON3

LOGIC

GENERAL

PENOK

AC_OK

PSON

16

MON4

ORFETOK

REF

V

PSON

CLOCK

SHAREOK

REF

AC_OK

DC_OK

CBD/ALERT

1717181818

DC_OK

OV

DD

V

11

CBD

PEN

12

PEN

CONFIGURE

CONTROL

REGISTERS

PWRON

I/Os

STATUS

CONFIGURE

V

AC_OK

OK

DD

RESET

V

OCP

1.5V

1.25V

AC_OK

PENOK

ORFETOK

SHAREOK

LOADVOK

REF

V

1.25V

OCPF

OVP

UVP

2.5V

1.25V

OV

OK

DD

DD

V

V

POWER MANAGEMENT

INTERNAL

REFERENCE

CLAMP

FALSE UV

1.5V

EXTREFOK

SET LOAD

OVERVOLTAGE

SET

LOAD

VOLTAGE

35kΩ

LOAD

35kΩ

35kΩ

×1.3

20

–

S

V

2

LS

V

SET UV CLAMP

35kΩ

21

+

S

V

FROM

SENSE

REMOTE

SET OVP

THRESHOLD

THRESHOLD

SET UVP

THRESHOLD

VOLTAGE SENSE

MAIN

BAND GAP

1

18

DD

REF

V

V

REFERENCE

MONITOR

XX

INTREFOK

AUXILIARY

REFERENCE

POR

2.0V

XX

S

UVLLO

4.0V

UVLHI

4.4V

RQ

SQ

OVP

6.0V–6.5V

10µs–20µs

RQ

GROUND

MONITOR

0.2V

20

–

S

V

GNDOK

gndok_dis

7

GND

Figure 4. Chip Diagram, Part 2

Rev. A | Page 5 of 64

HIGH VOLTAGE

NOTES:

1

ANALOG I/O PIN

STANDARD I/0 PIN3 ALL POTENTIOMETERS ( )

2

ARE DIGITALLY

PROGRAMMBALE

THROUGH REGISTERS

04521-0-038

ADM1041

SPECIFICATIONS

TA = –40 to +85°C, VDD = 5 V ± 10%, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

SUPPLIES

VDD 4.5 5.0 5.5 V
IDD, Current Consumption 6 10 mA
Peak I

during EEPROM Erase Cycle

DD,

UNDERVOLTAGE LOCKOUT, VDD

1, 2

40 mA

Start-Up Threshold 4 4.3 4.5 V
Stop Threshold 3.7 4 4.2 V
Hysteresis 0.3 V

V

REF

, 2.5 V

Reg 0Fh[4:2] = 111. See Table 24.

REFOUT

Output Voltage 2.49 2.50 2.51 V I
Line Regulation –5 0 +5 mV 4.5 V ≤ VDD ≤ 5.5 V
Load Regulation –5 0 +5 mV 0 mA ≤ I
Temperature Stability2 ±100 ppm/°C I
Long-Term Stability2 ±5 mV Over 1,000 hr, TJ = 125°C
Current Limit 10 20 mA V
Output Resistance2 0.5 Ω
Load Capacitance 1 nF Recommended for stability
Ripple Due to Autozero2 ±5 mV p-p V

POWER BLOCK PROTECTION

VDD Overvoltage 5.8 6.2 6.5 V
VDD Overvoltage Debounce 10 20 µs Latching
V

Overvoltage 2.9 V Internal

REF

V

Undervoltage 2.1 V External

REFOUT

Open Ground 0.1 0.2 0.35 V V
Debounce 100 200 µs VDDOK

POWER-ON RESET

DC Level 1.5 2.2 2.75 V VDD rising

DIFFERENTIAL LOAD VOLTAGE SENSE INPUT,
(V

−, VS+)

S

See Figure 6. V

VS− Input Voltage 0.5 V Voltage on Pin 20
VS+ Input Voltage VDD – 2 V Voltage on Pin 21
VS− Input Resistance 35 kΩ
VS+ Input Resistance 500 kΩ
V

Adjustment Range 1.7 to 2.3 V

NOM

Set Load Voltage Trim Step 0.10 to 0.14 % 1.7 V ≤ V

1.74 –> 3.18 mV 8 bits, 255 steps
Reg 19h[7:0]. See Table 34
Set Load Overvoltage Trim Range 105 to 120 % 1.7 V ≤ V
Set Load Overvoltage Trim Step 0.09 % 8 bits, 255 step/s

1.6 mV Reg 08h[7:0]. See Table 17.
V
Recover from Load OV False to FG True 100 µs Reg 03h[1:0] = 00. See Table 12.
200 µs Reg 03h[1:0] = 01. See Table 12.
300 µs Reg 03h[1:0] = 10. See Table 12.
400 µs Reg 03h[1:0] = 11. See Table 12.
Operate Time from Load OV to FG False 2 µs

See Figure 9.

= 1 mA, TA = 25°C

REF

≤ 2 mA

REF

= 1 mA

REF

= 2.4 V

REF

refreshed at 30 kHz

REF

positive with respect to VS−

GND

= (VS+ – VS−)

NOM

V

is typically 2 V

NOM

≤ 2.3 V typ

NOM

≤ 2.3 V min

NOM

+ = 2.24 V

S

Rev. A | Page 6 of 64

ADM1041

Parameter Min Typ Max Unit Test Conditions/Comments

LOCAL VOLTAGE SENSE, VLS,
AND FALSE UV CLAMP

Input Voltage Range3 2.3 VDD–2 V Set by external resistor divider.
Stage Gain 1.3 At VLS = 1.8 V
False UV Clamp, VLS, Input Voltage Nominal,

and Trim Range

Clamp Trim Step 0.2 % V
Clamp Trim Step 3.1 mV

Local Overvoltage 1.9 2.4 2.85 V

Nominal and Trim Range
OV Trim Step 0.15 % V
OV Trim Step 3.7 mV

Noise Filter, for OVP Function Only 5 25 µs
Local Undervoltage 1.3 1.7 2.1 V

Nominal and Trim Range
UV Trim Step 0.18 % V
UV Trim Step 3.1 mV

Noise Filter, for UVP Function Only 300 600 µs

VOLTAGE ERROR AMPLIFIER, V

Reference Voltage V

REF_SOFT_START

See Figure 14.

CMP

1.49 1.51 V TA = 25°C
Temperature Stability2 ±100 µV/°C −40°C ≤ TA ≤ 85°C
Long-Term Voltage Stability2 ±0.2 % Over 1,000 hr, TJ = 125°C
Soft-start Period Range 0 40 ms Ramp is 7 bit, 127 steps
Set Soft-start Period 300 µs Reg 10h[3:2] = 00. See Table 25.
10 ms Reg 10h[3:2] = 01. See Table 25.
20 ms Reg 10h[3:2] = 10. See Table 25.
40 ms Reg 10h[3:2] = 11. See Table 25.
Unity Gain Bandwidth, GBW 1 MHz See Figure 11.
Transconductance 1.9 2.7 3.5 mA/V At I
Source Current 250 µA At V
Sink Current 250 µA At V

DIFFERENTIAL CURRENT SENSE INPUT,

−, CS+

C

S

Common-Mode Range 0 VDD–2 V Set by external divider
External Divider Tolerance Trim Range
(with respect to input)

−10 mV Reg 16h[5:3] = 001. See Table 31.

−20 mV Reg 16h[5:3] = 010. See Table 31.
5 mV Reg 16h[5:3] = 100. See Table 31.
10 mV Reg 16h[5:3] = 101. See Table 31.
20 mV Reg 16h[5:3] = 110. See Table 31.
External Divider Tolerance Trim Step Size 20 µV VCM = 2.0 V
(with respect to input) 39 µV 8 bits, 255 steps
78 µV Reg 14h[7:0]. See Table 29.

See Figure 9.

1.3 1.85 2.1 V

RANGE

8 bits, 255 steps, Reg 18h[7:0].
See Table 33.

RANGE

8 bits, 255 steps Reg 0Ah[7:0].
See Table 33.

RANGE

8 bits, 255 steps, Reg 09h[7:0].
See Table 18.

= ±180 µA

VCMP

> 1 V

VCMP

< VDD − 1 V

VCMP

Reg 17h[7] = 0. See Table 18.

mode. See Figure 13.

I

SENSE

−5 mV Reg 16h[5:3] = 000. See Table 31.

Rev. A | Page 7 of 64

ADM1041

Parameter Min Typ Max Unit Test Conditions/Comments

DC Offset Trim Range (with respect to input) −8 mV Reg 17h[2:0] = 000. See Table 32 .

−15 mV Reg 17h[2:0] = 001. See Table 32.

−30 mV Reg 17h[2:0] = 010. See Table 32.
8 mV Reg 17h[2:0] = 100. See Table 32.
15 mV Reg 17h[2:0] = 101. See Table 32.
30 mV Reg 17h[2:0] = 110. See Table 32.
DC Offset Trim Step Size 30 µV VCM = 2.0 V, V
(with respect to input) 50 µV 8 bits, 255 steps
120 µV Reg 15h[7:0]. See Table 30.

CURRENT SENSE CALIBRATION

Total Current Sense Error2
(Gain and Offset)

= 2.0V, 0°C ≤ TA ≤ 85 OC SHRS =

V

CSCM

SHRO = 2 V. Gain = 230x

±3 % Chopper ON
±6 % Chopper OFF
Gain Range (I

) Input voltage range at CS+, CS−

SENSE

Gain Setting 1 (Reg 16h[2:0] = 000) 65 V/V 34.0 mV – 44.5 mV. Gain = 65×
Gain Setting 2 (Reg 16h[2:0] = 001) 85 V/V 26.0 mV – 34.0 mV. Gain = 85×
Gain Setting 3 (Reg 16h[2:0] = 010) 110 V/V 20.0 mV – 26.0 mV. Gain = 110×
Gain Setting 4 (Reg 16h[2:0] = 100) 135 V/V 16.0 mV – 20.0 mV. Gain = 135×
Gain Setting 5 (Reg 16h[2:0] = 101) 175 V/V 12.0 mV – 16.0 mV. Gain = 175×
Gain Setting 6 (Reg 16h[2:0] = 110) 230 V/V 9.5 mV – 12.0 mV. Gain = 230×

Full Scale (No Offset) 2.0 V VZO = 0

Attenuation Range 65 to 99 % Reg 06h[7:1]. See Table 15.
Current Share Trim Step (at SHRO) 0.4 % SHRS = SHRO = 1 V
8 mV 7 bits, 127 steps I
Gain Accuracy

Gain Accuracy

2, 4

, 40 mV at CS+, CS− −5 +5 % 0 V ≤ V

V

2, 4

, 20 mV at CS+, CS− −5 ±1 +5 % V

CSCM

= Input Common Mode

CSCM

= 2.0V, 0°C ≤ TA ≤ 85°C

CSCM

Gain = 135×

Gain Accuracy

2, 4

, 40 mV at CS+, CS– −2.5 ±0.5 +2.5 % V

= 2.0 V, 0°C ≤ TA ≤ 85°C

CSCM

Gain = 65×

SHARE BUS OFFSET See Figure 13.

Current Share Offset Range 1.25 V Reg 17h[7] = 1. See Table 32.

Reg 17h[5] = 1. See Table 32.

Zero Current Offset Trim Step 0 ≤ V

TRIM

0.4 % 8 bits, 255 steps, VCT = 1.0 V

5.5 mV Reg 05h[7:0]. See Table 14.

CURRENT TRANSFORMER SENSE INPUT, ICT

Reg 17h[7] = 1. See Table 32.

Reg 06h = FEh. See Table 15.
Gain Setting 0 4.5 V/V Reg 17h[5] = 0, V
Gain Setting 1 2.57 V/V Reg 17h[5] = 1. See Table 32.

Reg 15h = 05h, approx 1 µA.

See Table 30. V
CT Input Sensitivity 0.45 0.5 0.68 V Gain setting = 4.5
CT Input Sensitivity 0.79 1.0 1.20 V Gain setting = 2.57
Input Impedance2 20 50 kΩ
Source Current 2.0 µA

See Current Transformer Input

Section.
Source Current Step Size 170 nA 15 steps Reg 15h[3:0].

See Table 30.
Reverse Current for Extended SMBus

Addressing (Source Current)

5

3.5 5 7 mA

See Figure 38. See Absolute

Maximum Ratings.

= 0 V

DIFF

slope

SHARE

≤ 0.3 V. Gain = 65×

≤ 1.25 V

= 2 V. Table 31

SHARE

= 2 V.

SHARE

Rev. A | Page 8 of 64

ADM1041

Parameter Min Typ Max Unit Test Conditions/Comments

CURRENT LIMIT ERROR AMPLIFIER See Figure 13

Current Limit Trim Range2 105 130 % After I
Current Limit Trim Step 1.1 %
Current Limit Trim Step 26.5 mV

2.0 ≤ V

Reg 04h[7:3]. See Table 13.
Transconductance 100 200 300 µA/V I
Output Source Current 40 µA V
Output Sink Current 40 µA V

CCMP

CCMP

CCMP

CURRENT SHARE DRIVER See Figure 14.

Output Voltage6 VDD – 0.4 V RL = 1 kΩ, V
Short Circuit Source Current 55 mA
Source Current 15 mA

Current at which V

by more than 5%
Sink Current 60 100 µA V

CURRENT SHARE DIFFERENTIAL SENSE

See Figure 14.

SHARE

AMPLIFIER

VS– Input Voltage 0.5 V Voltage on Pin 20
V

Input Voltage VDD – 2 V Voltage on Pin 23

SHRS

Input Impedance2 65 100 kΩ V

SHRS

Gain 1.0 V/V

CURRENT SHARE ERROR AMPLIFIER

Transconductance, SHRS to SCMP 100 200 300 µA/V I
Output Source Current 40 µA V
Output Sink Current 40 µA V

SCMP

SCMP

SCMP

Input Offset Voltage 40 50 60 mV Master/slave arbitration

Share OK Window Comparator Threshold SHRS = 2 V ± SHR
(Share Drive Error) ±100 mV Reg 04h[1:0] = 00. See Table 13.
±200 mV Reg 04h[1:0] = 01. See Table 13.
±300 mV Reg 04h[1:0] = 10. See Table 13.
±400 mV Reg 04h[1:0] = 11. See Table 13.

CURRENT LIMIT

Figure 10.
Current Limit Control Lower Threshold 1.3 V V

CCMP

Current Limit Control Upper Threshold 3.5 V VS+ = 0 V, V

CURRENT SHARE CAPTURE V

SCMP

Current Share Capture Range 0.7 1 1.3 % Reg 10h[5:4] = 00. See Table 25.

1.4 2 2.6 % Reg 10h[5:4] = 01. See Table 25.

2.1 3 3.9 % Reg 10h[5:4] = 10. See Table 25.

2.8 4 5.2 % Reg 10h[5:4] = 11. See Table 25.
Capture Threshold 0.6 1.0 1.4 V

FET OR GATE DRIVE Open-drain N-channel FET

Output Low Level (On) 0.4 V IIO = 5 mA

0.8 V IIO = 10 mA
Output Leakage Current −5 +5 µA

REVERSE VOLTAGE COMPARATOR, FS, FD V

CS−

Common-Mode Range 0.25 2.0 VDD – 2 V Voltage set by CS resistor divider

Voltage on C

calibration

SHARE

≤ 2.8 V typ. 5 bits, 31 steps.

SHARE

= ±20 µA. See Figure 12.

= > 1 V
= < VDD – 1 V

≤ VDD – 2 V

SHRS

does not drop

OUT

= 2.0 V

= 0.5 V, V

− = 0.5 V

S

= ±20 µA

> 1 V
< VDD – 1 V

THRESH

= 0.7 V, VS+ = 1.5 V

= 0 V

SCMP

= 3.5 V.

= FS

− pin. TA = 25°C.

S

Rev. A | Page 9 of 64

ADM1041

Parameter Min Typ Max Unit Test Conditions/Comments

Reverse Voltage Detector Turn-Off Threshold
100 mV Reg 03h[7:6] = 00. See Table 12.
150 mV Reg 03h[7:6] = 01. See Table 12.
200 mV Reg 03h[7:6] = 10. See Table 12.
250 mV Reg 03h[7:6] = 11. See Table 12.
Reverse Voltage Detector Turn-On Threshold
20 mV Reg 03h[5:4] = 00. See Table 12.
30 mV Reg 03h[5:4] = 01. See Table 12.
40 mV Reg 03h[5:4] = 10. See Table 12.
50 mV Reg 03h[5:4] = 11. See Table 12.
FD Input Impedance 500 kΩ
FS Input Impedance 20 kΩ

AC

SENSE

1/AC

2 COMPARATOR Reg 12h[2] = 0

SENSE

(AC or Bulk Sense) Reg 12h[2] = 1

Threshold Voltage 1.25 V
Threshold Adjust Range 1.10 1.40 V Min: DAC = 0

Threshold Trim Step 0.8 % 1.10 ≤ V
10 mV 5 bits, 31 steps

Hysteresis Adjust Range 200−550 mV V
Hysteresis Trim Step 50 mV

Noise Filter 0.6 1 1.2 ms

PULSE-IN

Threshold Voltage 0.525 V
PULSE_OK On Delay 1 µs

PULSE_OK Off Delay 0.8 1 1.2 s
OSCILLATOR −5 +5 % Unless otherwise specified
OCP

OCP Threshold Voltage2 0.3 0.5 0.7 V Force C

Reg 11h[2] = 0. See Table 26.

OCP Shutdown Delay Time (Continuous

1 s Reg 12h[4:3] = 00. See Table 27.

Period in Current Limit)
2 s Reg 12h[4:3] = 01. See Table 27.
3 s Reg 12h[4:3] = 10. See Table 27.
4 s Reg 12h[4:3] = 11. See Table 27.
OCP Fast Shutdown Delay Time 0 100 ms Reg 11h[2] = 1. See Table 26.

MON1, MON2, MON3, MON4

Sense Voltage 1.21 1.25 1.29 V
Hysteresis 0.1 V
OVP Noise Filter 5 25 µs
UVP Noise Filter 300 600 µs

OTP (MON5) Reg 0Fh[4:2] = 01x or 10x. Table 24.

Sense Voltage Range 2.2 2.45 V
OTP Trim Step 24 mV 2.1 ≤ V
4 bits, 15 steps, Reg 0Bh[7:4].

Hysteresis 100 130 160 µA V

V

= 2 V for threshold specs

CS

−

V

= 2 V for threshold specs

CS

−

Reg 0Dh[3:2] = 00. See Table 22 .

Reg 0Eh[7:6] = 00. See Table 23.

Max: DAC = Full Scale

≤ 1.4 V

TRIM

Reg 0Ch[7:3]. See Table 21.

ACSENSE

200 ≤ V

> 1 V, R

≤ 550 mV. 7 steps

TRIM

THEVENIN

= 909R

Reg 0Ch[2:0]. See Table 21.

VC

= 1.5 V

CMP

for drop in V

CMP

≤ 2.45 V

TRIM

CMP

See Table 20.

= 2 V

OTP

Rev. A | Page 10 of 64

ADM1041

Parameter Min Typ Max Unit Test Conditions/Comments

OVP Noise Filter 5 25 µs

UVP Noise Filter 300 600 µs

PSON7 Reg 0Eh[4:2] = 00x. See Table 23.

Input Low Level8 0.8 V
Input High Level8 2.0 V
Debounce 80 ms Reg 0Fh[1:0] = 00. See Table 24.
0 ms Reg 0Fh[1:0] = 01. See Table 24.
40 ms Reg 0Fh[1:0] = 10. See Table 24.
160 ms Reg 0Fh[1:0] = 11. See Table 24.

PEN7, DC_OK7, CBD, AC_OK

Open-Drain N-Channel Option
Output Low Level = On8 0.4 V I
Open-Drain P-Channel V
Output High Level = On8 2.4 V I
Leakage Current −5 +5 µA

DC_OK7 Reg 0Fh[7:5] = 00x. See Table 24.

DC_OK, On Delay (Power-On and OK Delay) 400 ms Reg 0Eh[1:0] = 00. See Table 23.
200 ms Reg 0Eh[1:0] = 01.See Table 23.
800 ms Reg 0Eh[1:0] = 10. See Table 23.
1600 ms Reg 0Eh[1:0] = 11. See Table 23.
DC_OK, Off Delay (Power-Off Early Warning) 2 ms Reg 10h[7:6] = 00. See Table 25.
0 ms Reg 10h[7:6] = 01. See Table 25.
1 ms Reg 10h[7:6] = 10. See Table 25.
4 ms Reg 10h[7:6] = 11. See Table 25.

SMBus, SDL/SCL

Input Voltage Low8 0.8 V
Input Voltage High8 2.2 V
Output Voltage Low8 0.4 V VDD = 5 V, I
Pull-Up Current 100 350 µA
Leakage Current −5 +5 µA

ADD0, HARDWIRED ADDRESS BIT

ADD0 Low Level8 0.4 V
ADD0 Floating VDD/2 V Floating
ADD0 High8 VDD − 0.5 V

SERIAL BUS TIMING See Figure 5.

Clock Frequency 400 kHz
Glitch Immunity, tSW 50 ns
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t
SCL Low Time, t
SCL High Time, t

4.7 µs

BUF

4.7 µs

SU;STA

4 µs

HD;STA

4.7 µs

LOW

4 µs

HIGH

SCL, SDA Rise Time, tR 1000 ns
SCL, SDA Fall Time, tF 300 ns
Data Setup Time, t
Data Hold Time, t

250 ns

SU;DAT

300 ns

HD;DAT

EEPROM RELIABILITY

Endurance9 100 250 k cycles
Data Retention10 100 Years

Reg 0Fh[4:2] = 010 or 100.
See Table 24.

Reg 0Fh[4:2] = 011 or 101.
See Table 24.

= 4 mA

SINK

OH_PEN

= 4 mA

SOURCE

= 4 mA

SINK

Rev. A | Page 11 of 64

ADM1041

A

1

This specification is a measure of IDD during an EEPROM page erase cycle. The current is a dynamic. Refer to Figure 29 for a typical IDD plot during an EEPROM page

erase.

2

Specification is not production tested, but is supported by characterization data at initial product release.

3

Four external divider resistors are the same ration, which is selected to produce 2.0 V nominal at Pin 21 while at zero load current. Recommended values are

4

Chopper off.

5

The maximum specification here is the maximum source current of Pin 8 as specified by the Absolute Maximum Ratings.

6

All internal amplifiers accept inputs with common range from GND to VDD − 2 V. The output is rail to rail but the input is limited to GND to VDD − 2 V. See Figure 6.

7

These pins can be configured as open-drain N-channel or P-channel, (except PSON) and as normal or inverted logic polarity. Refer to Table 45.

8

A logic true or false is defined strictly according to the signal name. Low and high refer to the pin or signal voltages.

9

Endurance is qualified to 100,000 cycles as per JEDEC std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 250,000 cycles.

10

Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V. Derates
with junction temperature.

R

TOP

R

BOTTOM

3.3 V 5.0 V 12 V

680R 1K.5 5K1
1K 1K 1K

SCL

t

HD:STA

t

LOW

t

R

t

HD:DAT

t

HIGH

t

F

t

SU:DAT

t

SU:STA

t

HD:STA

t

SU:STO

SD

t

BUF

PS

S

Figure 5. Serial Bus Timing Diagram

SHRO

SHRS+

SHRS–

VA = V

R1

VBVAVB = V

R1

R1 + R2 ≥ 1kΩ

Figure 6. Amplifier Inputs and Outputs

DD

DD

– 0.4V

–2V

04521-0-004

P

04521-0-005

Rev. A | Page 12 of 64

ADM1041

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage (Continuous), VDD 6.5 V

Data Pins SDA, SCL, V

DATA

+ 0.5 V,

V

DD

GND − 0.3 V
Continuous Power at 25°C, P
Operating Temperature, T

AMB

450 mW

D-QSOP24

−40°C to +85°C
Junction Temperature, TJ 150°C
Storage Temperature, T
Lead Temperature

(Soldering, 10 Seconds), T
ESD Protection on All Pins, V

−60°C to +150°C

STG

300°C

L

2 kV

ESD

Thermal Resistance, Junction to Air, θJA 150°C/W
ICT Source Current1 7 mA

1

This is the maximum current that can be sourced out from Pin 8 (ICT pin).

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Thermal Characteristics

24-Lead QSOP Package:

= 150°C/W

θ

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. A | Page 13 of 64

ADM1041

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

V

1

DD

CS+

C

CMP

V

CMP

GND

ICT
1/MON1
2/MON2

PEN

F

D

2
3
4
5

ADM1041

6

TOP VIEW

7

(Not to Scale)

8

9
10
11
12

PULSE/AC

SENSE

AC

SENSE

CBD/ALERT

VLS/CS–/FS

Figure 7. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Positive Supply for the ASIC. Normal range is 4.5 V to 5.5 V. Absolute maximum rating is 6.5 V.
2 VLS/CS–/FS

Inverting Differential Current Sense Input, Local Voltage Sense Pin, and OrFET Source. These three
functions are served by a common divider. The local voltage sense input is used for local overvoltage
and undervoltage sensing. This pin also provides an input to the false UV clamp that prevents
shutdown during an external load overvoltage condition. When supporting an OrFET circuit, this pin
represents the FET source and is the inverting input of a differential amplifier looking for the presence
of a reverse voltage across the FET, which might indicate a failure mode.

3 CS+

Noninverting Differential Current Sense Input. The differential sensitivity of C
around 10 mV to 40 mV at the input to the ASIC. Nulling any external divider offset is achieved by
injecting a trimmable amount of current into either the inverting or noninverting input of the second
stage of the current sense amplifier. A compensation circuit is used to ensure the amount of current
for zero-offset tracks the common-mode voltage. Nulling of any amplifier offset is done in a similar
manner except that it does not track the common-mode voltage.

4 C

CMP

Current Error Amplifier Compensation. This pin is the output of the current limit transconductance
error amplifier. A series resistor and a capacitor to ground are required for loop compensation.

5 V

CMP

Voltage Error Amplifier Compensation. This is the output of a voltage error transconductance
amplifier. Compensate with a series capacitor and resistor to ground. An external emitter-follower or
buffer is typically used to drive an optocoupler. Output voltage positioning may be obtained by
placing a second resistor directly to ground. Refer to Analog Devices applications notes on voltage
positioning.

6 FD

A divider from the OrFET drain is connected here. A differential amplifier is then used to detect the
presence of a reverse voltage across the FET, which indicates a fault condition and causes the OrFET
gate to be pulled low.

7 GND

Ground. This pin is double bonded for extra reliability. If the ground pin goes positive with respect to
the remote sense return (V

–) for a sustained period indicating that the negative remote sense line is

S

disconnected, PEN will be disabled.

8 ICT

Input for Current Transformer. The sensitivity of this pin is suitable for the typical 0.5 V to 1 V signal
that is normally available. If this function is enabled, the C
for extended SMBus addressing, i.e., pulled below ground to allow additional SMBus addresses.

9 PULSE/AC

1/MON1 Pulse Present, AC/Bulk Sense 1, or Monitor 1 Input.

SENSE

PULSE: This tells the OrFET circuit that the voltage from the power transformer is normal. A peak hold
allows the OrFET circuit to pass through the pulse skipping that occurs with very light loads but turns
off the circuit about one second after the last pulse is recognized.

AC

1: This sense function also uses the peak voltage on this pin to measure the bulk capacitor

SENSE

voltage. If too low, AC_OK and DC_OK can warn of an imminent loss of power. Threshold level and
hysteresis can be trimmed. When not selected, AC

MON1: When MON1 is selected for this pin, its input is compared against a 1.25 V comparator that
could be used for monitoring a post regulated output; includes overvoltage, undervoltage, and
overtemperature conditions.

SHRO

24
23

SHRS+

22

SCMP

21

V

+

S

20

V

–/SHRS–

S

19

F

G

18

V

/AC_OK/OTP/MON5

REF

DC_OK/MON4

17

PSON/MON3

16

ADD0

15

SDA/PS

14
13

SCL/AC_OKLink

LINK

ON

1 defaults to true.

SENSE

04521-0-030

+ and CS– is normally

S

+ amplifier is disabled. This pin is also used

S

Rev. A | Page 14 of 64

ADM1041

Pin No. Mnemonic Description

10 AC

11 CBD/ALERT

12 PEN

13 SCL/AC_OKLink SCL: SMBus Serial Clock Input.

14 SDA/PSONLINK SDA: SMBus Serial Data Input and Output.

15 ADD0

16 PSON/MON3

17 DC_OK/MON4

18 V

19 FG

20 VS–/SHRS–

2/MON2 AC/Bulk Sense Input 2 or Monitor 2 Input.

SENSE

AC

2: This alternative AC

SENSE

input can be used when the AC

SENSE

source must be different from

SENSE

that used for the OrFET. It also allows dc and opto-coupled signals that are not suitable for the OrFET
control.

MON2: When MON2 is selected for this pin, its input is compared against a 1.25 V comparator that
could be used for monitoring a post regulated output; includes overvoltage, undervoltage, and
overtemperature conditions.

CBD: The crowbar drive pin allows implementation of a fast shutdown in case of a load overvoltage
fault. The pin can be configured as an open-drain N-channel or P-channel and is suitable for driving a
sensitive gate SCR crowbar. An external transistor is required if a high gate current is needed. Either
polarity may be selected.

ALERT: This pin can be configured to provide an ALERT function in microprocessor-supported
applications whereby any of several ICs in a redundant system that detects a problem can interrupt
and shut down the power supply. An alternative use is as a general-purpose logic output signal.

Power Enable. This pin can be configured as an open-drain N-channel or P-channel that typically
drives the PEN optocoupler. Providing that the PSON pin has been asserted to turn the output on, and
that there are no faults, this pin drives an optocoupler on enabling the primary PWM circuit. Either
polarity may be selected.

AC_OKLink: In non-microprocessor applications, this pin can be programmed to give the status of

to all the ICs on the same bus. The main effect is to turn on undervoltage blanking whenever

AC

SENSE

the sense circuit monitoring ac or bulk dc detects a low voltage.

LINK: In non-microprocessor applications, this pin can be programmed to provide the PSON

PS

ON

status to other ICs. This allows just one IC to be the PSON interface to the host system, or the PS
itself can be the PSON interface.

Chip Address Pin. There are three addresses possible using this pin, which are achieved by tying ADD0
to ground, tying to V

, or being left to float. One address bit is available via programming at the

DD

device/daughter card level so the total number of addressable ICs can be increased to six.
PSON: In non-microprocessor configurations, this is power supply on. As a standard I/O, this pin is

rugged enough for direct interface with a customer’s system. Either polarity may be selected.
MON3: When MON3 is selected for this pin, its input is compared against a 1.25 V comparator that

could be used for monitoring a post-regulated output; includes overvoltage, undervoltage, and
overtemperature conditions.

DC_OK: This pin is the output of a general-purpose digital I/O that can be configured as open-drain
N-channel or open-drain P-channel suitable for wire-ORing with other ICs and direct interfacing with a
customer’s system. Either polarity may be selected.

MON4: When MON4 is selected for this pin, its input is compared against a 1.25 V comparator that
could be used for overtemperature protection and for monitoring a post-regulated output; includes
overvoltage, undervoltage, and overtemperature conditions.

/AC_OK/OTP/MON5 Voltage Reference, Buffered Output, Overtemperature Protection, or Monitor 5.

REF

V

: This is a 2.5 V precision reference voltage capable of sourcing 2 mA. This function is continuously

REF

monitored, and if the voltage falls below 2.0 V, PEN is disabled. Forcing this pin's voltage does not
affect the integrity of the internal reference.

AC_OK: This option can be configured as N-channel or P-channel and as normal or inverted polarity.
At system level, a true AC_OK is used to indicate that the primary bulk voltage is high enough to
support the system, and when false, that dc output is about to fail.

MON5: A further option is to configure this as an analog input, MON5, with a flexible hysteresis and
trimmable 2.5 V reference that makes this pin particularly suitable for overtemperature protection
(OTP) sensing. Since hysteresis uses a switched 100 µA current source, hysteresis can be adjusted via
the source impedance of the external circuit. It can also be used for overvoltage and undervoltage
functions.

FET Gate Enable. When supporting an OrFET circuit, this is the gate drive pin. Since the open-drain
voltage on the chip is limited to V

, an external level shifter is required to drive the higher gate

DD

voltages suitable for the OrFET. This pin is configured as an open-drain N-channel. Either output
polarity, low = on or low = off, may be selected.

This pin is used as the ground input reference for the current share and load voltage sense circuits. It
should be tied to ground at the common remote sense location. The input impedance is about 35 kΩ
to ground.

ON

LINK

Rev. A | Page 15 of 64

ADM1041

Pin No. Mnemonic Description

21 VS+

22 SCMP

23 SHRS+

24 SHRO

Table 4. Default Pin States during EEPROM Download

Pin No. Mnemonic State

11 CBD High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).

12 PEN High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).

17 DC_OK Active low (low if DC_OK true) at power-up.

18 AC_OK Active low (low if DC_OK true) at power-up.

19 FG High impedance (Hi-Z) at power-up and until the end of the EEPROM download (approximately 20 ms).

This pin is the positive remote load voltage sense input and is normally divided down from the power
supply output voltage to 2.0 V at no load using an external voltage divider. The input impedance is
high.

Output of the Current Share Transconductance Error Amplifier. Compensation is a series capacitor and
resistor to ground. While V

is normal and PEN is false, this pin is clamped to ground. When the

DD

converter is enabled (PEN true) and the clamp is released, the compensation capacitor charges
providing a slow walk-in. The error amplifier input has a built-in bias so that all slaves in a parallel
supply system do not compete with the master for control of the share bus.

Current Share Sense. This is the noninverting input of a differential sense amplifier looking at the
voltage on the share bus. For testing purposes, this pin is normally connected to SHRO. Calibration
always expects this pin to be at 2.0 V with respect to SHRS–/V

–. If a higher share voltage is required, a

S

resistor divider from SHRO or an additional gain stage, as shown in the application notes, must be
used.

Current Share Output. This output is capable of driving the share bus of several power supplies
between 0 V and V

– 0.4 V (10 kΩ bus pull-down in each supply). Where a higher share bus voltage is

DD

required, an external amplifier is necessary. The current share output from the supply which, when
bused with the share output of other power supplies working in parallel, allows each of the supplies
to contribute essentially equal currents to the load.

This pin is reconfigured at the end of the EEPROM download.

This pin is reconfigured at the end of the EEPROM download.

This pin is reconfigured during the EEPROM download.

This pin is reconfigured during the EEPROM download.

This pin is reconfigured at the end of the EEPROM download.

Rev. A | Page 16 of 64

ADM1041

TERMINOLOGY

Table 5.

Mnemonic Description

POR

Power-On Reset. When V
the logic into a state that allows a clean start-up.

UVL

CVMode

Undervoltage Lockout. This is used on V

is below a specific voltage.

V

DD

Constant Voltage Mode. This is the normal mode of operation of the power supply main output. The
output voltage remains constant over the whole range of current specified.

CCMode

Constant Current Mode. This mode of operation occurs when the output is overloaded until or unless
a shutdown event is triggered. The output current control level remains constant down to 0 V.

UVP

Undervoltage Protection. If the output being monitored is detected as going under voltage, the UVP
function sends a fault signal. After a delay, PEN goes false, the output is disabled, and either latch-off
or an auto-restart occurs, depending on the mode selected. The DC_OK output also goes false
immediately to show that the output is out of tolerance.

OVP

Overvoltage Protection. If the output being monitored is detected as going over voltage, the OVP
function latches and sends a fault signal, PEN goes false, and CBD goes true. The DC_OK output also
goes false immediately. OVP faults are always latching and require the cycling of PSON or V
SMBus command to reset the latch.

OCP

Overcurrent Protection. If the output being monitored is detected as going over current for a certain
time, the OCP function sends out a fault signal that triggers a shutdown that can be latched or
allowed to auto-restart, depending on the mode selected. Prior to shutting down, the DC_OK output
goes false warning the system that output will be lost. The latch is the same one used for OVP. For
auto-restart, the OCP time out period is configurable.

OTP

Overtemperature Protection. If the temperature being sensed is detected as going over the selected
limit, the OTP function sends out a fault signal that triggers a shutdown that can be latched or allowed
to auto-restart depending on the mode selected. Prior to shutting down, the DC_OK output goes false
warning the system that output will be lost. The latch is the same one used for OVP.

UVB

Undervoltage Blanking. The UVP function is blanked (disabled) during power-up or if the AC
function is false (ac line voltage is low). When in constant current mode, UVB is disabled. The status of
AC

must be known to the IC, either by virtue of the on-board AC

SENSE

SMBus with the help of an external microprocessor or by using AC_OKLink. When in constant current
mode, due to an overload, UVB is applied for the overcurrent ride through period.

DC_OK

The DC_OK function advises the system on the status of the power supply. When it is false, the system
is assured of at least 1 ms of operation if ac power is lost for any reason. Other turn-off modes provide
more warning time. This pin is an open-drain output. It can be configured as a P-channel pull-up or an
N-channel pull-down. It may also be configured as positive or negative (inverted) logic.

AC_OK

The AC_OK function advises the system whether or not sufficient bulk voltage is present to allow
reliable operation. The system may choose to shut down if this pin is false. The power supply normally
tries to maintain normal operation as long as possible, although DC_OK goes false when only a
millisecond or so of operation time is left. This pin is an open-drain output. It can be configured as a
P-channel pull-up or an N-channel pull-down. It may also be configured as positive or negative

(inverted) logic.
DC_OKondelay The DC_OK output is kept false for typically 100 ms to 900 ms during power-up.
DC_OKoffdelay

When the system is to be shut down in response to PSON going low, or in response to an OCP or OTP

event, a signal is first sent to the DC_OK output to go false as a warning that power is about to be lost.

PEN is signaled false typically 2 ms later (configurable).
Debounce Digital Noise Filter

All of the inputs to the logic core are first debounced or digitally filtered to improve noise immunity.

The debounce period for OV events is in the order of 16 µs, for UV events it is 450 µs, and for PSON it is

typically 80 ms (configurable).
AC

SENSE

1

A voltage from the secondary of the power transformer, which can provide an analog of the bulk

supply, is rectified and lightly filtered and measured by the ac sense function. At start-up, if this

voltage is adequate, this function signals the end user system that it is okay to start. If a brown-out

occurs or ac power is removed, this function can provide early warning that power is about to be lost

and allow the system to shut down in an orderly manner. While AC

means undervoltage protection is not initiated. If ac power is so low that the converter cannot

continue to operate, other protection circuits on the primary side normally shut down the converter.

When an adequate voltage level is resumed, a power-up cycle is initiated.

is initially applied to the ASIC, the POR function clears all latches and puts

DD

to prevent spurious modes of operation that might occur if

DD

or

DD

SENSE

or communicated by the

SENSE

is low, UVB is enabled, which

SENSE

Rev. A | Page 17 of 64

ADM1041

Mnemonic Description

Pulse_OK

AC Hysteresis

AC

2

SENSE

Soft-start

VDD–OVP

VDD–UVL A UVL fault on the auxiliary supply to the IC causes a standard UVP operation (see the UVP function).
AutoRestart Mode

V

–MON

REF

GND–MON

As well as providing ac sense, the preceding connection to the transformer is used to gate the
operation of the OrFET circuit. If the output of the transformer is good and has no problems, the
OrFET circuit allows gate drive to the OrFET.

AC Sense Hysteresis. Configurable voltage on the ac sense input allows the ac sense upper and lower
threshold to be adjusted to suit different amounts of low frequency ripple present on the bulk
capacitor.

An alternate form of ac sense can be accepted by the ASIC. This may in the form of an opto-coupled
signal from the primary side where the actual level sensing might be done. As with the above, while
ac is low and UVB is disabled, AC_OK is false and DC_OK is true. Any brownout protection that might
be required on the primary is done on the primary side.

At start-up, the voltage reference to the voltage error amplifier is brought up slowly in approximately
127 steps to provide a controlled rate of rise of the output voltage.

An OVP fault on the auxiliary supply to the ASIC causes a standard OVP operation (see the OVP
function).

In this mode, the housekeeping circuit attempts to restart the supply after an undervoltage event at
about 1 second intervals. No other fault can initiate auto-restart.

The internal precision reference is monitored by a separate reference for overvoltage and allows truly
redundant OVP. The externally available reference is also monitored for an undervoltage that would
indicate a short on the pin.

The internal ASIC ground is constantly monitored against the remote sense negative pin. If the chip
ground goes positive with respect to this pin, it indicates that the chip ground is open-circuit either
inside the ASIC or the external wiring. The ASIC would be latched off, similar to an OV event.

Rev. A | Page 18 of 64

ADM1041

THEORY OF OPERATION

POWER MANAGEMENT

This block contains VDD undervoltage lockout circuitry and a
power-on/reset function. It also provides precision references

. If V

for internal use and a buffered reference voltage, V

REF

configured to an output pin, overloading, shorting to ground, or
shorting to V

During power-on, V

do not effect the internal references. See Figure 8.

DD

does not come up until VDD exceeds the

REF

upper UVL threshold. Housekeeping functions in this block
include reference voltage monitors, V

overvoltage, and a

DD

ground fault detector.

The ground fault detector monitors ADM1041 ground with
respect to the remote sense pin V

V

REF

V

DD

−. If GND becomes positive

S

18

1

MAIN

BAND GAP

REF

is

with respect to V
is true only when all the following conditions are met: ground is
negative with respect to V
normally, V

GAIN TRIMMING AND CONFIGURATION

The various gain settings and configurations throughout the
ADM1041 are digitally set up via the SMBus after it has been
loaded onto its printed circuit board. There is no need for
external trim potentiometers. An initial adjustment process
should be carried out in a test system. Other adjustments such
as current sense and voltage calibration should be carried out in
the completed power supply.

EXTREFOK

− an on-chip signal, VDDOK, goes false. VDDOK

S

−, INTREF and EXTREF are operating

S

> UVLHI, and VDD < VDD OVP threshold.

DD

INTERNAL

REFERENCE

2.5V

1.25V

REFERENCE

MONITOR

S

RQ

SQ

RQ

INTREFOK

OK

V

DD

V

OV

DD

04521-0-006

VS–

GND

6.0V–6.5V

20

7

2.0V

4.0V

4.4V

0.2V

AUXILIARY

REFERENCE

POR RESET

UVLLO

UVLHI

OVP

10µs–20µs

GROUND

MONITOR

GNDOK

gndok_dis

Figure 8. Block Diagram of Power Management Section

Rev. A | Page 19 of 64

ADM1041

DIFFERENTIAL REMOTE SENSE AMPLIFIER

This amplifier senses the load voltage and is the main voltage
feedback input. A differential input is used to compensate for
the voltage drop on the negative output cable of the power
supply. An external voltage divider should be designed to set the

+ pin to approximately 2.0 V with respect to VS–. The amplifier

V

S

gain is 1.0. See Figure 9.

SET LOAD VOLTAGE

The load voltage may be trimmed via the SMBus by a trim stage
at the output of the differential remote sense amplifier. The
voltage at the output of the trimmer is 1.50 V when the voltage
loop is closed. See Figure 9.

LOAD OVERVOLTAGE (OV)

A comparator at the output of the load voltage trim stage
detects load overvoltage. The load OV threshold can be
trimmed via the SMBus. The main purpose is to turn off the
OrFET when the load voltage rises to an intermediate over­voltage level that is below the local OVP level. This circuit is not
latching. See Figure 9.

LOCAL VOLTAGE SENSE

This amplifier senses the output voltage of the power supply just
before the OrFET. Its input is derived from one of the pins used
for current sensing and is set to 2.0 V by an external voltage
divider. The amplifier gain is 1.3. See Figure 9.

LOCAL OVERVOLTAGE PROTECTION (OVP)

This is the main overvoltage detection for the power supply. It is
detected locally so that only the faulty power supply shuts down
in the event of an OVP condition in an N+1 redundant power
system. This occurs only after a load OV event. The local OVP
threshold may be trimmed via the SMBus. See Figure 9.

LOCAL UNDERVOLTAGE PROTECTION (UVP)

This is the main undervoltage detection for the power supply. It
is also detected locally so that a faulty power supply can be
detected in an N+1 redundant power system. The local UVP
threshold may be trimmed via the SMBus. See Figure 9.

FALSE UV CL AMP

If a faulty power supply causes an OVP condition on the system
bus, the control loops in the good power supplies is driven to
zero output. Therefore, a means is required to prevent the good
power supplies from indicating an undervoltage, and they must
recover quickly after the faulty power supply has shut down.
The false UV clamp achieves this by clamping the output voltage
just above the local UVP threshold. It may be trimmed via the
SMBus. The OCPF signal disables the clamp during overcurrent
faults. See Figure 9.

V

–

S

REMOTE

SENSE

FROM

LOAD

21

35kΩ

20

V

+

S

2

V

LS

NOTE:
ALL POTENTIOMETERS ( ) ARE DIGITALLY PROGRAMMABLE THROUGH REGISTERS.

35kΩ

×1.3

35kΩ

35kΩ

SET LOAD

VOLTAGE

SET UV CLAMP

THRESHOLD

SET OVP

THRESHOLD

SET UVP

THRESHOLD

SET LOAD

OVERVOLTAGE

FALSE UV

25kΩ

1.25V

CLAMP

1.5V

Figure 9. Block Diagram of Voltage Sense Amplifier

CURRENT LIMIT

DIFF. VOLTAGE SENSE

CURRENT SHARE

LOADVOK

OCPF

OVP

UVP

TO
GENERAL
LOGIC

TO
GENERAL
LOGIC

1V 3V
CAPTURE

V

REF

1.5V

RAMP UP

70µA

VOLTAGE

ERROR AMP

SOFT-

START

5

V

CMP

04521-0-032

Rev. A | Page 20 of 64