ANALOG DEVICES ADM1029 Service Manual

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Dual PWM Fan Controller and Temperature

a

FEATURES
Software Programmable and Automatic Fan Speed

Control

Automatic Fan Speed Control Allows Control

Independent of CPU Intervention after Initial Setup

Control Loop Minimizes Acoustic Noise and Power

Consumption
Remote and Local Temperature Monitoring
Dual Fan Speed Measurement
Supports Backup and Redundant Fans

FUNCTIONAL BLOCK DIAGRAM

ADM1029

SLAVE ADDRESS

REGISTER

PRESENT1

FAULT1

FAN 1 STATUS

REGISTER

FAN 1 MIN

SPEED REGISTER

Monitor for High Availability Systems

ADM1029*

Supports Hot Swapping of Fans
Cascadable Fault Output Allows Fault Signaling

between Multiple ADM1029s
Address Pin Allows Up to Eight ADM1029s in A System
Small 24-Lead QSOP Package

APPLICATIONS
Network Servers and Personal Computers
Microprocessor-Based Office Equipment
High Availability Telecommunications Equipment

V

CC

SERIAL BUS

INTERFACE

ADDRESS POINTER

REGISTER

INTERRUPT MASK

REGISTERS

INTERRUPT STATUS

REGISTERS

INTERRUPT

MASKING

SCL

SDA

INT

CFAULT

DRIVE1

TACH1

TACH2

PRESENT2

FAULT2

DRIVE2

*Protected by U.S. Patent Numbers 6,255,973 and 6,188,189

PWM

CONTROLLER

PWM

CONTROLLER

FAN 1 ALARM

SPEED REGISTER

FAN 1 HOT-PLUG

SPEED REGISTER

FAN SPEED

COUNTER

FAN 2 STATUS

REGISTER

FAN 2 MIN

SPEED REGISTER

FAN 2 ALARM

SPEED REGISTER

FAN 2 HOT-PLUG

SPEED REGISTER

REFERENCE

GND

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

LIMIT COMPARATOR

VALUE AND LIMIT

REGISTERS

G.P. I/O REGISTER

ADC

ANALOG

MUX

BANDGAP

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © Analog Devices, Inc., 2001

REMOTE SENSOR

SIGNAL

CONDITIONING

BANDGAP

TEMP SENSOR

RESET

GPIO2

AIN1/GPIO1

AIN0/GPIO0

D2+/GPIO6

D2–/GPIO5

D1+/GPIO4

D1–/GPIO3

TMIN/INSTALL

ADD

1, 2

ADM1029–SPECIFICATIONS

(TA = T

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Supply Voltage, V
Supply Current, I

CC

CC

3.0 3.30 5.5 V

TEMPERATURE-TO-DIGITAL CONVERTER

Internal Sensor Accuracy ± 1 ± 3 °C
Resolution 1 °C
External Diode Sensor Accuracy ± 3 ± 5 °C0°C ≤ T
Resolution 1 °C
Remote Sensor Source Current 90 µA High Level

ANALOG-TO-DIGITAL CONVERTER

Total Unadjusted Error, TUE ± 1 % Note 3
Differential Nonlinearity, DNL ± 1 LSB
Power Supply Sensitivity ± 1 %/ V
Conversion Time

Analog Input or Internal Temperature 11.6 ms
External Temperature 185.6 ms

FAN RPM-TO-DIGITAL CONVERTER

Accuracy ± 6%60°C ≤ TA ≤ 100°C: VCC = 3.3 V
Full-Scale Count 255
FAN 1 and FAN 2 Nominal Input RPM

4

Internal Clock Frequency 56.4 60.0 63.6 kHz

OPEN-DRAIN DIGITAL OUTPUTS (INT, CFAULT)

Output Low Voltage, V
High Level Output Current, I

OL

OH

OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)

Output Low Voltage, V
High Level Output Leakage Current, I

OL

OH

SERIAL BUS DIGITAL INPUTS (SCL, SDA)

Input High Voltage, V
Input Low Voltage, V

IL

IH

2.1 V

Hysteresis 500 mV

DIGITAL INPUT LOGIC LEVELS RESET,
GPIO1-6, FAULT1/2, TACH1/2, PRESENT1/2

Input High Voltage, V
Input Low Voltage, V

IL

IH

2.1 V

DIGITAL INPUT CURRENT

Input High Current, I
Input Low Current, I
Input Capacitance, C

SERIAL BUS TIMING

Clock Frequency, f
Glitch Immunity, t
Bus Free Time, t
Start Setup Time, t
Start Hold Time, t

IH

IL

IN

5

SCLK

SW

BUF

SU:STA

HD:STA

Stop Condition Setup Time, t

SU:STO

–1 µAV

10 100 kHz See Figure 1

4.7 µs See Figure 1

4.7 µs See Figure 1
4 µs See Figure 1
4 µs See Figure 1

to T

MIN

, VCC = V

MAX

MIN

to V

, unless otherwise noted.)

MAX

1.7 3.0 mA Interface Inactive, ADC Active

1.5 mA ADC Inactive, DAC Active
10 60 µA Shutdown Mode

≤ 100°C

A

5.5 µA Low Level

8800 rpm Divisor = 1, Fan Count = 153
4400 rpm Divisor = 2, Fan Count = 153
2200 rpm Divisor = 4, Fan Count = 153
1100 rpm Divisor = 8, Fan Count = 153

0.4 V I

0.1 1 µAV

0.4 V I

0.1 1 µAV

= –6.0 mA, VCC = 3 V

OUT

= V

OUT

CC

= –6.0 mA, VCC = 3 V

OUT

= V

OUT

CC

0.8 V

0.8 V

= V

IN

+1 µAV

IN

CC

= 0

20 pF

50 ns See Figure 1

–2–

REV. 0

ADM1029

Parameter Min Typ Max Unit Test Conditions/Comments

5

SERIAL BUS TIMING

SCL Low Time, t
SCL High Time, t
SCL, SDA Rise Time, t
SCL, SDA Fall Time, t
Data Setup Time, t
Data Hold Time, t

NOTES

1

All voltages are measured with respect to GND, unless otherwise specified.

2

Typicals are at TA = 25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.

3

TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer.

4

The total fan count is based on two pulses per revolution of the fan tachometer output.

5

Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.

Specifications subject to change without notice.

(continued)

LOW

HIGH

SU:DAT

HD:DAT

1.3 µs See Figure 1
450µs See Figure 1

R

F

1000 ns See Figure 1

300 ns See Figure 1
250 ns See Figure 1
300 ns See Figure 1

ABSOLUTE MAXIMUM RATINGS*

Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . 6.5 V

Voltage on Pins 13–18 . . . . . . . . . . . . –0.3 V to (V

+ 0.3 V)

CC

Voltage on Any Other Input or Output Pin . . . . –0.3 V to +6.5 V

Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ±5 mA

Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA

Maximum Junction Temperature (T

max) . . . . . . . . . . 150°C

J

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200°C

ESD Rating All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

24-Lead QSOP Package:

= 105°C/W, θJC = 39°C/W

θ

JA

ORDERING GUIDE

Temperature Package Package

Model Range Description Option

ADM1029ARQ 0°C to 100°C Shrink Small Outline RQ-24

Package (QSOP)

PIN CONFIGURATION

1

DRIVE1

2

FAULT1

3

TACH1

SCL

SDA

GND

V

INT

GPIO2

RESET

CC

4

5

6

7

(Not To Scale)

8

9

10

11

12

ADM1029

TOP VIEW

PRESENT1

CFAULT

24

DRIVE2

23

FAULT2

22

TACH2

21

PRESENT2

20

AIN1/GPIO1

19

AIN0/GPIO0

18

TMIN/INSTALL

17

D2+/GPIO6

16

D2–/GPIO5

15

ADD

14

D1+/GPIO4

13

D2–/GPIO3

REV. 0

SCL

SDA

t

R

t

LOW

t

HD;STA

t

BUF

S

P

t

HD;DAT

t

HIGH

t

F

t

SU;DAT

t

HD;STA

t

t

SU;STA

S

SU;STO

P

Figure 1. Diagram for Serial Bus Timing

–3–

ADM1029

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1 DRIVE1 Open Drain Digital Output. Pulsewidth Modulated (PWM) output to control the speed of

Fan 1. Requires 10 kΩ typical pull-up resistor.

2 FAULT1 Open Drain Digital I/O. When used with a fan having a fault output, a Logic 0 input to this pin

signals a fault on Fan 1. Also used as a fault output.

3 TACH1 Open Drain Digital Input. Digital fan tachometer input for Fan 1. Will accept logic signals up

to 5 V even when V

4 PRESENT1

Open Drain Digital Input. A shorting link in the fan connector holds this pin low when

Fan 1 is connected.
5 SCL Open Drain Digital Input. Serial Bus Clock. Requires 2.2 kΩ pull-up typical.
6 SDA Digital I/O. Serial Bus bidirectional data. Open-drain output requires 2.2 kΩ pull-up.
7 GND System Ground
8V

CC

Power (3.0 V to 5.5 V). Typically powered from 3.3 V power rail. Bypass with the parallel

combination of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors.
9 CFAULT

Open Drain Digital I/O. Cascade fault input/output used for fault signaling between

multiple ADM1029s.
10 INT Digital Output. Interrupt Request (Open Drain). The output is enabled when Bit 1 of the

Configuration Register is set to 0. The default state is enabled.
11 GPIO2 Open Drain Digital I/O. General-purpose logic I/O pin.
12 RESET Open Drain Digital Input. Active low reset input.
13 D1–/GPIO3 Analog Input/Open Drain Digital I/O. Connected to cathode of external temperature-sensing

diode, or may be reconfigured as a general-purpose logic input/output.
14 D1+/GPIO4 Analog Input/Open Drain Digital I/O. Connected to anode of external temperature-sensing

diode, or may be reconfigured as a general-purpose logic input/output.
15 ADD Eight-Level Analog Input. Used to set the three LSBs of the serial bus address.
16 D2–/GPIO5 Analog Input/Open Drain Digital I/O. Connected to cathode of external temperature-sensing

diode, or may be reconfigured as a general-purpose logic input/output.
17 D2+/GPIO6 Analog Input/Open Drain Digital I/O. Connected to anode of external temperature-sensing

diode, or may be reconfigured as a general-purpose logic input/output.
18 TMIN/INSTALL Eight-Level Analog Input. The voltage on this pin defines whether automatic fan speed control

is enabled, the minimum temperature at which the fan(s) will turn on in automatic speed con-

trol mode, and the number of fans that should be installed.
19 AIN0/GPIO0 Analog Input/Open Drain Digital I/O. May be configured as a 0 V to 2.5 V analog input or as a

general-purpose digital I/O pin.
20 AIN1/GPIO1 Analog Input/Open Drain Digital I/O. May be configured as a 0 V to 2.5 V analog input or as a

general-purpose digital I/O pin.
21 PRESENT2 Open Drain Digital Input. A shorting link in the fan connector holds this pin low when Fan 2

is connected.
22 TACH2 Open Drain Digital Input. Digital fan tachometer input for Fan 2. Will accept logic signals up

to 5 V even when V
23 FAULT2 Open Drain Digital I/O. When used with a fan having a fault output, a Logic 0 input to this pin

signals a fault on Fan 2. Also used as a fault output.
24 DRIVE2 Open Drain Digital Output. Pulsewidth Modulated (PWM) output to control the speed of

Fan 2. Requires 10 kΩ typical pull-up resistor.

is lower than 5 V.

CC

is lower than 5 V.

CC

–4–

REV. 0

Typical Performance Characteristics–ADM1029

110

100

90

80

70

60

50

40

30

20

10

0

0 10 20 30 40 50 60 70 80 90 100 110

READING

MEASURED TEMPERATURE

1
0

–1
–2
–3
–4
–5
–6
–7
–8

–9
–10
–11
–12
–13
–14
–15
–16

1.0 2.2 3.3 4.7 10.0 22.0 47.0

REMOTE TEMPERATURE ERROR – ⴗC

DXP – DXN CAPACITANCE – nF

15

10

5

0

–5

–10

–15

REMOTE TEMPERATURE ERROR – ⴗC

–20

0 3.3 10 30 100

LEAKAGE RESISTANCE – M⍀

DXP TO GND

DXP TO VCC(3.3V)

TPC 1. Remote Temperature Error vs. PC Board Track
Resistance

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

REMOTE TEMPERATURE ERROR – ⴗC

V

–0.5

–1.0

0 1 4 8 12 16 20 50 100 200 300

= 100mV p-p

IN

VIN = 250mV p-p

FREQUENCY – MHz

400

500

600

TPC 2. Remote Temperature Error vs. Power Supply
Noise Frequency

TPC 4. Pentium® III Temperature Measurement vs.
ADM1029 Reading

TPC 5. Remote Temperature Error vs. Capacitance
Between D+ and D–

10

9

8

7

6

5

4

3

Pentium is a registered trademark of Intel Corporation.

REV. 0

2

1

REMOTE TEMPERATURE ERROR – ⴗC

0

–1

0 0.4 0.8 10 600150 40050 250 500100 200 350 450 550300

FREQUENCY – MHz

TPC 3. Remote Temperature Error vs. Common-Mode
Noise Frequency

V

= 100mV p-p

IN

V

= 60mV p-p

IN

VIN = 40mV p-p

–5–

80

70

60

50

40

30

SUPPLY CURRENT – ␮A

20

10

0

0 1 5 10 25 50 75 100 250 500 750 1000

SCLK FREQUENCY – kHz

VCC = 5V

VCC = 3.3V

TPC 6. Standby Current vs. Clock Frequency

ADM1029

13

12

11

10

9

8

7

6

5

4

3

2

1

REMOTE TEMPERATURE ERROR – ⴗC

0

–1

0

12 40020 300100 5001 4 8 16 50 200

VIN = 40mV p-p

VIN = 30mV p-p
V

IN

FREQUENCY – MHz

= 20mV p-p

600

TPC 7. Remote Temperature Error vs. Differential-Mode
Noise Frequency

32

30

28

26

24

22

20

18

16

14

12

10

SUPPLY CURRENT – ␮A

8

6

4

2

0

1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6
SUPPLY VOLTAGE – V

TPC 8. Standby Supply Current vs. Supply Voltage

10

9

8

7

6

5

4

3

2

1

LOCAL TEMPERATURE ERROR – ⴗC

0

–1

0 1 4 8 12 16 20 50 100 200 300 400 500 600

FREQUENCY – MHz

VIN = 250mV p-p

VIN = 100mV p-p

TPC 10. Local Sensor Temperature Error vs. Power Supply
Noise Frequency

120

110

100

90

80

70

60

50

40

TEMPERATURE – ⴗC

30

20

10

0

0 1 2 3 4 5 6 7 8 9 10

TIME – Seconds

TPC 11. ADM1029 Response to Thermal Shock

1.80

1.75

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

SUPPLY CURRENT – mA

1.20

1.15

1.10

1.05

1.00

2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0 4.2 4.4 4.6 4.8 5.0

SUPPLY VOLTAGE – V

TPC 9. Supply Current vs. Supply Voltage

–6–

0.10

0.00

–0.10

–0.20

–0.30

–0.40

–0.50

–0.60

ERROR – ⴗC

–0.70

–0.80

–0.90

–1.00

–1.10

–1.20

0 20 40 60 80 85 100 105 120

TEMPERATURE – ⴗC

TPC 12. Remote Temperature Error

REV. 0

ADM1029

0.05

0.00

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

ERROR – ⴗC

–0.35

–0.40

–0.45

–0.50

–0.55

–0.60

0 20 40 60 80 85 100 105 120

TEMPERATURE – ⴗC

TPC 13. Local Temperature Error

PRODUCT DESCRIPTION

The ADM1029 is a versatile fan controller and monitor for use
in personal computers, servers, telecommunications equipment,
or any high-availability system where reliable control and moni­toring of multiple cooling fans is required. Each ADM1029 can
control the speed of one or two fans and can measure the speed
of fans that have a tachometer output. The ADM1029 can also
measure the temperature of one or two external sensing diodes
or an internal temperature sensor, allowing fan speed to be
adjusted to keep system temperature within acceptable limits. The
ADM1029 has FAULT inputs for use with fans that can signal
failure conditions, and inputs to detect whether or not fans are
connected.

The ADM1029 communicates with the host processor over an
System Management (SMBus) serial bus. It supports eight
different serial bus addresses, so that up to eight devices can
be connected to a common bus, controlling up to sixteen fans.
This makes software support and hardware design scalable.

The ADM1029 has an interrupt output (INT) that allows it
to signal fault conditions to the host processor. It also has a
separate, cascadable fault output (CFAULT) that allows the
ADM1029 to signal a fault condition to other ADM1029s.

The ADM1029 has a number of useful features including an
automatic fan speed control option implemented in hardware
with no software requirement, automatic use of backup fans in
the event of fan failure, and supports hot-swapping of failed fans.

Table I. Resistor Ratios for Setting Serial Bus Address

FUNCTIONAL DESCRIPTION

SERIAL BUS INTERFACE

Control of the ADM1029 is carried out via the serial bus. The
ADM1029 is connected to this bus as a slave device, under the
control of a master device.

The ADM1029 has a 7-bit serial bus address. The four MSBs of
the address are set to 0101. The three LSBs can be set by the
user to give a total of eight different addresses, allowing up to
eight ADM1029s to be connected to a single serial bus segment.
To minimize device pin count and size, the three LSBs are set
using a single pin (ADD, Pin 15). This is an 8-level input whose
input voltage is set by a potential divider. The voltage on ADD
is sampled immediately after power-up and digitized by the
on-chip ADC to determine the value of the 3 LSBs. Since ADD
is sampled only at power-up, any changes made while power is
on will have no effect.

V

CC

R1

ADD

R2

GND

ADM1029

Figure 2. Setting the Serial Address

Table I shows resistor values for setting the 3 LSBs of the serial
bus address. The same principle is used to set the voltage on Pin
18 (TMIN/INSTALL), which controls the automatic fan speed
control function, and also tells the ADM1029 how many fans
should be installed, as described later.

If several ADM1029s are used in a system, their ADD inputs
can tap off a single potential divider, as shown in Figure 3.

V

CC

ADDRESS XXXX111

1.5k⍀

ADDRESS XXXX110

1k⍀

ADDRESS XXXX101

1k⍀

ADDRESS XXXX100

1k⍀

ADDRESS XXXX011

1k⍀

ADDRESS XXXX010

1k⍀

ADDRESS XXXX001

1.5k⍀

ADDRESS XXXX000

GND

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADD

ADM1029 #1

ADM1029 #2

ADM1029 #3

ADM1029 #4

ADM1029 #5

ADM1029 #6

ADM1029 #7

ADM1029 #8

Figure 3. Setting Address of up to Eight ADM1029s

3 MSBs Ideal Ratio R1 R2 Actual Error
of ADC R2/(R1 + R2) (k⍀)(k⍀) R2/(R1 + R2) % Address

111 N/A 0 ∞ 1 0 0101111
110 0.8125 18 82 0.82 +0.75 0101110
101 0.6875 22 47 0.6812 –0.63 0101101
100 0.5625 12 15 0.5556 –0.69 0101100
011 0.4375 15 12 0.4444 +0.69 0101011
010 0.3125 47 22 0.3188 +0.63 0101010
001 0.1875 82 18 0.18 –0.75 0101001
000 N/A ∞ 0 0 0 0101000

REV. 0

–7–

ADM1029

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START
condition, defined as a high-to-low transition on the serial
data line SDA, while the serial clock line SCL remains high.
This indicates that an address/data stream will follow. All
slave peripherals connected to the serial bus respond to the
START condition, and shift in the next eight bits, consisting
of a 7-bit address (MSB first) plus an R/W bit, which deter­mines the direction of the data transfer, i.e., whether data
will be written to or read from the slave device.

The peripheral whose address corresponds to the transmitted
address responds by pulling the data line low during the low
period before the ninth clock pulse, known as the Acknowl­edge Bit. All other devices on the bus now remain idle while
the selected device waits for data to be read from or written
to it. If the R/W bit is a 0, the master will write to the slave
device. If the R/W bit is a 1 the master will read from the
slave device.

2. Data is sent over the serial bus in sequences of nine clock
pulses, eight bits of data followed by an acknowledge bit
from the slave device. Transitions on the data line must

191

SCL

occur during the low period of the clock signal and remain
stable during the high period, as a low-to-high transition
when the clock is high may be interpreted as a STOP signal.
The number of data bytes that can be transmitted over the
serial bus in a single READ or WRITE operation is limited
only by what the master and slave devices can handle.

3. When all data bytes have been read or written, stop condi­tions are established. In WRITE mode, the master will pull
the data line high during the tenth clock pulse to assert a
STOP condition. In READ mode, the master device will
override the acknowledge bit by pulling the data line high
during the low period before the ninth clock pulse. This is
known as No Acknowledge. The master will then take the
data line low during the low period before the tenth clock
pulse, high during the tenth clock pulse to assert a STOP
condition.

Any number of bytes of data may be transferred over the serial
bus in one operation, but it is not possible to mix read and write
in one operation, because the type of operation is determined at
the beginning and cannot subsequently be changed without
starting a new operation.

9

SDA

START BY

MASTER

0

101A2

SERIAL BUS ADDRESS BYTE

FRAME 1

SCL (CONTINUED)

SDA (CONTINUED)

A0

A1

R/W

ACK. BY

ADM1029

1

D7 D6 D5

D6

D7

ADDRESS POINTER REGISTER BYTE

D4 D3 D2 D1

D5

FRAME 2

D4 D3 D2 D1

FRAME 3

DATA BYTE

D0

ACK. BY

ADM1029

D0

ACK. BY

ADM1029

9

STOP BY

MASTER

Figure 4a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

SCL

SDA

START BY

MASTER

191

0

101A2

SERIAL BUS ADDRESS BYTE

FRAME 1

A0 D7

A1

R/W

ACK. BY

ADM1029

D6

ADDRESS POINTER REGISTER BYTE

D4 D3 D2 D1

D5

FRAME 2

D0

ACK. BY

ADM1029

9

STOP BY
MASTER

Figure 4b. Writing to the Address Pointer Register Only

191

SCL

9

SDA

START BY

MASTER

0

101A2

SERIAL BUS ADDRESS BYTE

D6 D5

D4 D3 D2 D1

DATA BYTE FROM ADM1029

FRAME 2

FRAME 1

A0 D7

A1

R/W

ACK. BY

ADM1029

Figure 4c. Reading Data from a Previously Selected Register

–8–

D0

NO ACK.

BY MASTER

STOP BY
MASTER

REV. 0

ADM1029

In the case of the ADM1029, write operations contain either
one or two bytes, and read operations contain one byte, and
perform the following functions:

To write data to one of the device data registers or read data
from it, the Address Pointer Register must be set so that the
correct data register is addressed, data can be written into that
register or read from it. The first byte of a write operation always
contains an address that is stored in the Address Pointer Regis­ter. If data is to be written to the device, the write operation
contains a second data byte that is written to the register
selected by the address pointer register.

This is illustrated in Figure 4a. The device address is sent over
the bus followed by R/W set to 0. This is followed by two data
bytes. The first data byte is the address of the internal data
register to be written to, which is stored in the Address Pointer
Register. The second data byte is the data to be written to the
internal data register.

When reading data from a register there are two possibilities:

1. If the ADM1029’s Address Pointer Register value is unknown
or not the desired value, it is first necessary to set it to the
correct value before data can be read from the desired data
register. This is done by performing a write to the ADM1029
as before, but only the data byte containing the register address
is sent, as data is not to be written to the register. This is
shown in Figure 4b.

A read operation is then performed consisting of the serial
bus address, R/W bit set to 1, followed by the data byte read
from the data register. This is shown in Figure 4c.

2. If the Address Pointer Register is known to be already at the
desired address, data can be read from the corresponding
data register without first writing to the Address Pointer
Register, so Figure 4b can be omitted.

Note: although it is possible to read a data byte from a data
register without first writing to the Address Pointer Register,
if the Address Pointer Register is already at the correct value,
it is not possible to write data to a register without writing to
the Address Pointer Register, because the first data byte of a
write is always written to the Address Pointer Register.

ALERT RESPONSE ADDRESS

The ADM1029 has an interrupt (INT) output that is asserted
low when a fault condition occurs. Several INT outputs can be
wire OR’d to a common interrupt line. When the host processor
receives an interrupt request, it would normally need to read the
interrupt status register of each device to identify which device
had made the interrupt request. However, the ADM1029 sup­ports the optional Alert Response Address function of the SMBus
protocol. When the host processor receives an interrupt request
it can send a general call address (0001100) over the bus. The
device asserting INT will then send its own slave address back
to the host processor, so the device asserting INT can be identi­fied immediately.

If more than one device is asserting INT, all devices will try to
respond with their slave address, but an arbitration process
ensures that only the lowest address will be received by the host.

After sending its slave address, the first device will then clear its
INT output. The host can then check if the INT is still low and
send the general call again if necessary until all devices asserting
INT have responded.

The ARA function can be disabled by setting Bit 2 of the Con­figuration Register (address 01h).

TEMPERATURE MEASUREMENT SYSTEM

LOCAL TEMPERATURE MEASUREMENT

The ADM1029 contains an on-chip bandgap temperature sensor,
whose output is digitized by the on-chip ADC. The temperature
data is stored in the Local Temp Value Register (address A0h).
As both positive and negative temperatures can be measured, the
temperature data is stored in two’s complement format, as shown
in Table II. Theoretically, the temperature sensor and ADC can
measure temperatures from –128°C to +127°C with a resolution
of 1°C, but temperatures outside the operating temperature
range of the device cannot be measured by the internal sensor.

REMOTE TEMPERATURE MEASUREMENT

The ADM1029 can measure the temperature of one or two
remote diode-connected transistors, connected to Pins 13 and
14 and/or 16 and 17. The data from the temperature measure­ments is stored in the Remote 1 and Remote 2 Temp Value
Registers (addresses A1h and A2h).

If two remote temperature measurements are not required, Pins
16 and 17 can be reconfigured as general-purpose logic I/O
pins, as explained later.

The forward voltage of a diode or diode-connected transistor,
operated at a constant current, exhibits a negative temperature
coefficient of about –2 mV/°C. The absolute value of V

varies

BE

from device to device and individual calibration is required to
null this out so, unfortunately, the technique is unsuitable for
mass production.

The technique used in the ADM1029 is to measure the change
in V

when the device is operated at two different currents.

BE

This is given by:

∆V

= KT/q × ln(N)

BE

where:

K is Boltzmann’s constant
q is charge on the carrier
T is absolute temperature in Kelvins
N is ratio of the two currents

Figure 5 shows the input signal conditioning used to measure
the output of a remote temperature sensor. This figure shows
the external sensor as a substrate transistor, provided for tem­perature monitoring on some microprocessors, but it could equally
well be a discrete transistor.

If a discrete transistor is used, the collector will not be grounded,
and should be linked to the base. If a PNP transistor is used, the
base is connected to the D– input and the emitter to the D+
input. If an NPN transistor is used, the emitter is connected to
the D– input and the base to the D+ input.

REV. 0

–9–

ADM1029

V

DD

I

N ⴛ I

REMOTE

SENSING

TRANSISTOR

I

D+

D–

BIAS

DIODE

BIAS

LOW-PASS FILTER

f

C

= 65kHz

Figure 5. Signal Conditioning for Remote Diode Temperature Sensors

V

OUT

TO ADC

V

OUT

+

–

To prevent ground noise interfering with the measurement, the
more negative terminal of the sensor is not referenced to ground,
but biased above ground by an internal diode at the D– input. If
the sensor is used in a noisy environment, a capacitor of value
up to 1000 pF may be placed between the D+/D– pins.

To measure ∆V

, the sensor is switched between operating currents

BE

of I and N × I. The resulting waveform is passed through a 65 kHz
low-pass filter to remove noise, and to a chopper-stabilized amplifier
that performs the functions of amplification and rectification of
the waveform to produce a dc voltage proportional to ∆VBE. This
voltage is measured by the ADC to give a temperature output in
8-bit two’s complement format. To further reduce the effects of
noise, digital filtering is performed by averaging the results of 16
measurement cycles. An external temperature measurement takes
nominally 9.6 ms.

The results of external temperature measurements are stored in
8-bit, two’s complement format, as illustrated in Table II.

OFFSET REGISTERS

Digital noise and other error sources can cause offset errors in
the temperature measurement, particularly on the remote sen­sors. The ADM1029 offers a way to minimize these effects. The
offsets on the three temperature channels can be measured during
system characterization and stored as two’s complement values
in three offset registers at addresses 30h to 32h. The offset
values are automatically added to, or subtracted from, the tem­perature values, depending on whether the two’s complement
number corresponds to a positive or negative offset. Offset val­ues from –15°C to +15°C are allowed.

The default value in the offset registers is zero, so if no offsets
are programmed, the temperature measurements are unaltered.

TEMPERATURE LIMITS

The contents of the Local and Remote Temperature Value Regis­ters (addresses A0h to A2h) are compared to the contents of the
High and Low Limit Registers at addresses 90h to 92h and 98h
to 9Ah. How the ADM1029 responds to overtemperature/
undertemperature conditions depends on the status of the Tem­perature Fault Action Registers (addresses 40h to 42h). The
response of CFAULT, INT, and fan-speed-to-temperature events
depends on the setting of these registers, as explained later.

Table II. Temperature Data Format

Temperature Digital Output

–128°C 1000 0000
–125°C 1000 0011
–100°C 1001 1100
–75°C 1011 0101
–50°C 1100 1110
–25°C 1110 0111
0°C 0000 0000
+10°C 0000 1010
+25°C 0001 1001
+50°C 0011 0010
+75°C 0100 1011
+100°C 0110 0100
+125°C 0111 1101
+127°C 0111 1111

–10–

REV. 0

ADM1029

LAYOUT CONSIDERATIONS

Digital boards can be electrically noisy environments, and care
must be taken to protect the analog inputs from noise, particu­larly when measuring the very small voltages from a remote diode
sensor. The following precautions should be taken:

1. Place the ADM1029 as close as possible to the remote sens-

ing diode. Provided that the worst noise sources such as
clock generators, data/address buses, and CRTs are avoided,
this distance can be 4 to 8 inches.

2. Route the D+ and D– tracks close together, in parallel, with

grounded guard tracks on each side. Provide a ground plane
under the tracks if possible.

3. Use wide tracks to minimize inductance and reduce noise

pickup. Ten mil track minimum width and spacing is
recommended.

GND

D+

D–

GND

10MIL

10MIL

10MIL

10MIL

10MIL

10MIL

10MIL

Figure 6. Arrangement of Signal Tracks

4. Try to minimize the number of copper/solder joints, which

can cause thermocouple effects. Where copper/solder joints
are used, make sure that they are in both the D+ and D–
path and at the same temperature.

Thermocouple effects should not be a major problem as 1°C
corresponds to about 240 µV, and thermocouple voltages are
about 3 µV/

o

C of temperature difference. Unless there are two
thermocouples with a big temperature differential between
them, thermocouple voltages should be much less than 200 µV.

5. Place 0.1 µF bypass and 1000 pF input filter capacitors close
to the ADM1029.

6. If the distance to the remote sensor is more than 8 inches,
the use of twisted pair cable is recommended. This will work
up to about 6 to 12 feet.

7. For really long distances (up to 100 feet), use shielded
twisted pair such as Belden #8451 microphone cable. Con­nect the twisted pair to D+ and D– and the shield to GND
close to the ADM1029. Leave the remote end of the shield
unconnected to avoid ground loops.

Because the measurement technique uses switched current
sources, excessive cable and/or filter capacitance can affect the
measurement. When using long cables, the filter capacitor may
be reduced or removed.

Cable resistance can also introduce errors. 1 Ω series resistance
introduces about 0.5°C error.

TEMPERATURE-RELATED REGISTERS

Table III is a list of registers on the ADM1029 that are specific
to temperature measurement and control.

Table III. Temperature-Specific Registers

Address Description

0x06 Temp Devices Installed
0x30 Local Temp Offset
0x31 Remote 1 Temp Offset
0x32 Remote 2 Temp Offset
0x40 Local Temp Fault Action
0x41 Remote 1 Temp Fault Action
0x42 Remote 2 Temp Fault Action
0x48 Local Temp Cooling Action
0x49 Remote 1 Temp Cooling Action
0x4A Remote 2 Temp Cooling Action
0x80 Local Temp TMIN
0x81 Remote 1 Temp TMIN
0x82 Remote 2 Temp TMIN
0x88 Local Temp TRANGE/THYST
0x89 Remote 1 Temp TRANGE/THYST
0x8A Remote 2 Temp TRANGE/THYST
0x90 Local Temp High Limit
0x91 Remote 1 Temp High Limit
0x92 Remote 2 Temp High Limit
0x98 Local Temp Low Limit
0x99 Remote 1 Temp Low Limit
0x9A Remote 2 Temp Low Limit
0xA0 Local Temp Value
0xA1 Remote 1 Temp Value
0xA2 Remote 2 Temp Value

The flowchart in Figure 7 shows how to configure the ADM1029
to measure temperature. It also shows how to configure the
ADM1029’s behavior for out-of-limit temperature measurements.

FAN INTERFACING

The ADM1029 can be interfaced to many types of fan. It can be
used to control the speed of a simple two-wire fan. It can mea­sure the speed of a fan with a tach output, and it can accept a
logic input from fans with a FAULT output. By means of a
shorting link in the fan connector it can also determine if a fan is
present or not and if fans have been hot-swapped.

The ADM1029 can control or monitor one or two fans. Bits 0
and 1 of the Fans Supported In System Register (03h) tell the
ADM1029 how many fans it should be controlling/monitoring.

In the following descriptions “installed” means that the corre­sponding bit of register 03h is set and the ADM1029 expects to
see a fan interfaced to it. It does not necessarily mean that the
fan is actually, physically, connected.

If a fan is installed, events such as a fault output and hot-swapping
of the fan can cause INT and CFAULT to be asserted, unless
they are masked for that particular event. If a fan is not installed,
but is still physically connected to the ADM1029, these events will
be ignored with respect to asserting INT or CFAULT, but will
still be reflected in the corresponding Fan Status Register.

Setting Bit 0 indicates that Fan 1 is installed and is set to 1
at power-up by default. Setting Bit 1 indicates that Fan 2 is
installed and depends on the state of Pin 18 (TMIN/INSTALL)
at power-up.

REV. 0

–11–

ADM1029

DEFAULTS

LOCAL = 60ⴗC
REMOTE 1 = 70ⴗC
REMOTE 2 = 70ⴗC

DEFAULTS

LOCAL = 80ⴗC

REMOTE 1 = 100ⴗC
REMOTE 2 = 100ⴗC

DEFAULTS

LOCAL = 0ⴗC
REMOTE 1 = 0ⴗC
REMOTE 2 = 0ⴗC

CONFIGURE

TEMPERATURE LOW

LIMITS

LOCAL (REG 0x98)
REMOTE 1 (REG 0x99)
REMOTE 2 (REG 0x9A)

CONFIGURE

TEMPERATURE HIGH

LIMITS

LOCAL (REG 0x90)
REMOTE 1 (REG 0x91)
REMOTE 2 (REG 0x92)

CONFIGURE

TEMPERATURE FAULT

ACTION

LOCAL (REG 0x40)
REMOTE 1 (REG 0x41)
REMOTE 2 (REG 0x42)

CONFIGURE

TEMPERATURE COOLING

ACTION

LOCAL (REG 0x48)
REMOTE 1 (REG 0x49)
REMOTE 2 (REG 0x4A)

CONFIGURE

TEMPERATURE OFFSETS

LOCAL (REG 0x30)
REMOTE 1 (REG 0x31)
REMOTE 2 (REG 0x32)

BIT 0 = 1 ASSERT CFAULT ON OVER-TEMPERATURE
BIT 1 = 1 RUN FAN(S) ALARM SPEED ON OVER-TEMPERATURE
BIT 2 = 1 ASSERT INT ON OVER-TEMPERATURE
BIT 3 = 0 ALARM BELOW LOW TEMP LIMIT
BIT 3 = 1 ALARM ABOVE LOW TEMP LIMIT
BIT 4 = 1 ASSERT CFAULT WHEN LOW TEMP LIMIT CROSSED
BIT 5 = 1 RUN FAN ALARM SPEED ON UNDER-TEMPERATURE
BIT 6 = 1 ASSERT INT ON UNDER-TEMPERATURE
BIT 7 LATCHES A TEMPERATURE OUT-OF-LIMIT EVENT

7 6 5 4 3 2 1 0

IS

TEMPERATURE

>

HIGH LIMIT?

YES

IS

TEMPERATURE

>

HIGH LIMIT?

YES

ALARM ABOVE OR

BELOW LOW TEMP

LIMIT?

0 = ALARM BELOW TEMP LIMIT

IS

TEMPERATURE

>

HIGH LIMIT?

YES

CFAULT

FANS RUN

ALARM SPEED

INT

MEASURE

TEMPERATURE

LOCAL (REG 0xA0)
REMOTE 1 (REG 0xA1)
REMOTE 2 (REG 0xA2)

LOW TEMP LIMIT

LOW TEMP LIMIT

CROSSED?

YES

AUTOMATIC FAN SPEED CONTROL (SEE TABLE X LATER)

BIT 0 = 1 FAN 1 RUNS AT ALARM SPEED FOR OUT-OF-LIMIT TEMPERATURE EVENTS;

BIT 1 = 1 FAN 2 RUNS AT ALARM SPEED FOR OUT-OF-LIMIT TEMPERATURE EVENTS;

XXXXXX10

OTHERWISE, FAN 1 RUNS AT SPEED DETERMINED BY AUTOMATIC FAN
CONTROL.

OTHERWISE, FAN 2 RUNS AT SPEED DETERMINED BY AUTOMATIC FAN
CONTROL.

LOW TEMP LIMIT

CROSSED?

YES

CROSSED?

1 = ALARM ABOVE TEMP LIMIT

CFAULT

YES

FANS RUN ALARM SPEED

INT

Figure 7. Temperature Sensing Flowchart

–12–

REV. 0

ADM1029

If two fans are installed, Bit 0 would be 1 by default and Pin
18 would be tied high* to set Bit 1. If only one fan is installed, it
would normally be Fan 1 and Pin 18 would be tied low* to
clear Bit 1. However, both of these bits can be modified by
writing to the register, so it is possible to have Fan 2 installed
and not Fan 1, or even have no fans installed.

*Note that Pin 18 also sets TMIN for automatic fan speed control. If this function

is used, Pin 18 would be set to some other level according to Table VIII.

FAULT INPUTS/OUTPUTS

The ADM1029 can be used with fans that have a fault output
which indicates if the fan has stalled or failed. If one or both of
the FAULT inputs (Pin 2 or Pin 23) goes low, both INT and
CFAULT will be asserted.

Events on the fault inputs are also reflected in Bits 2 and 3 of the
corresponding Fan Status Registers at addresses 10h and 11h.
Bit 2 reflects the inverse state of the FAULT pin (0 if FAULT is
high, 1 if FAULT is low), while Bit 3 is latched high if a FAULT
input goes low. It must be cleared by writing a zero to it.

If the fan(s) being used do not have a FAULT output, the FAULT
input(s) on the ADM1029 should be pulled high to V

CC

.

The FAULT pins can also be configured as open-drain outputs
by setting Bit 5 of the corresponding Fan Fault Action Register
(18h or 19h). If a FAULT pin is configured as an output, it will
still function as an input. This means that when a fault input
occurs it will be latched low by the fault output, even if the fault
input is removed. The fault output can be used to drive a fan
failure indicator such as an LED.

If the FAULT pin is used as an output, any input to the FAULT
pin should also be open-drain. This will avoid the fault input
trying to source a high current into the FAULT pin if the fault
input goes high while the fault output is low.

FAN PRESENT INPUTS

The fan PRESENT signal is implemented by a shorting link
to ground in the fan connector. When the fan is plugged in,
the corresponding PRESENT input (Pin 4 or Pin 21) on the
ADM1029 is pulled low. If the fan is unplugged, the PRESENT
input will be pulled high. INT and CFAULT will be asserted
(unless masked) and the event will be reflected in Bits 0 and
Bit 1 of the corresponding Fan Status Register.

Appearance or disappearance of a PRESENT input signal dur­ing normal operation signals to the ADM1029 that a fan has
been hot-plugged or unplugged. INT and CFAULT will be
asserted (unless masked). When a fan is hot-plugged, Bit 7 of
the corresponding Fan Status Register will be set and a Fan
Free Wheel Test commences automatically.

FAN SPEED MEASUREMENT

The fan counter does not count the fan tach output pulses
directly, because at low fan speeds it would take several seconds
to accumulate a reasonably large and accurate count. Instead,
the period of the fan revolution is measured by gating an on­chip oscillator into the input of an 8-bit counter.

The fan speed measuring circuit is initialized on the first rising
edge of a fan tach pulse after monitoring is enabled by setting
Bit 4 of the Configuration Register. It then starts counting on
the rising edge of the second tach pulse and counts for four fan
tach periods, until the rising edge of the sixth tach pulse, or
until the counter overranges if the fan tach period is too long.

After the speed of the first fan has been measured, the speed of
the second fan (if installed) will be measured in the same way.
The measurement cycle will repeat until monitoring is disabled.
The fan speed measurements are stored in the Fan Tach Value
registers at addresses 70h and 71h.

If both fans are installed, Fan 1 will be measured first. If only
one fan is installed, the ADM1029 will still try to measure
both fans, starting with Fan 1, but the measurement on the
noninstalled fan will time out when the Fan Tach Value count
overranges.

The fan speed count is given by:

Count = f  4  60/R/N

where:

f is oscillator frequency in Hz
factor 4 is because 4 tach periods are counted
factor 60 is to convert minutes to seconds
R = fan speed in RPM
N is number of tach pulses per revolution

The frequency of the oscillator can be adjusted to suit the expected
frequency range of the fan tach pulses, which depends on the
fan speed and the number of tach pulses produced for each
revolution of the fan, which is either 1, 2, or 4. The oscillator
frequency is set by Bits 7 and 6 of the Fan Configuration Regis­ters (68h for Fan 1 and 69h for Fan 2).

Table III. Oscillator Frequencies

Bit 7 Bit 6 Oscillator Frequency (Hz)

0 0 Measurement Disabled
0 1 470
1 0 940
1 1 1880

CLOCK

CONFIG

REG. BIT 4

FAN 1

TACH

FAN 2

TACH

START OF

MONITORING

CYCLE

FAN 1

MEASUREMENT

PERIOD

FAN 2

MEASUREMENT

PERIOD

Figure 8. Fan Speed Measurement

FAN SPEED LIMITS

Fans generally do not overspeed if run from the correct voltage,
so the failure condition of interest is under-speed due to electri­cal or mechanical failure. For this reason only low-speed limits
are programmed into the Tach Limit Registers for the fans.
These registers are at address 78h for Fan 1 and 79h for Fan

2. It should be noted that, since fan period rather than speed is
being measured, the fan speed count will be larger the slower
the fan speed. Therefore a fan failure fault will occur when the
measurement exceeds the limit value.

REV. 0

–13–

ADM1029

For the most accurate fan failure indication, the oscillator
frequency should be chosen to give as large a limit value as
possible without the counter overranging. A count close to 3/4
full-scale or 191 is the optimum value.

For example, if a fan produces two tach pulses per revolution
and the fan failure speed is to be 600 rpm, the oscillator fre­quency should be set to 940 Hz. This will give a count at the fail
speed of:

940  4  60/600/2 = 188

If the oscillator frequency were only 470 Hz, the count would
be 94, while an oscillator frequency of 1880 Hz cannot be used
because the count would be 376 and the counter would overrange.

FAN MONITORING CYCLE TIME

Five complete tach periods are required to carry out a fan speed
measurement Therefore, if the start of a fan measurement just
misses a rising edge, the measurement can take almost six tach
periods for each fan.

The worst-case monitoring cycle time is when both fans are
under speed and the fan speed counter counts up to its maxi­mum value. The actual count takes 256 oscillator pulses over
four tach periods, plus a further two tach periods or 128 oscilla­tor pulses before the count starts. The total monitoring cycle
time is therefore:

t

MEAS

= 384/f

OSC(FAN 1)

+ 384/f

OSC(FAN 2)

In order to read a valid result from the Fan Tach Value Registers,
the total monitoring time allowed after starting the monitoring
cycle should be greater than this.

TACH SIGNAL CONDITIONING

Signal conditioning in the ADM1029 accommodates the slow
rise and fall times typical of fan tachometer outputs. The maxi­mum input signal range is 0 V to 5 V, even if V

is less than

CC

5 V. In the event that these inputs are supplied from fan outputs
that exceed 0 V to 5 V, either resistive attenuation of the fan
signal or diode clamping must be included to keep inputs within
an acceptable range.

Figures 9a to 9d show circuits for most common fan tach outputs.

If the fan tach output has a resistive pull-up to V

, it can be

CC

connected directly to the fan input, as shown in Figure 9a.

12V

PULL-UP

4.7k⍀
TYP

TACH
OUTPUT

TACH1

OR TACH2

Figure 9a. Fan with Tach Pull-Up to +V

V

CC

FAN SPEED

COUNTER

CC

If the fan output has a resistive pull-up to 12 V (or other voltage
greater than 6.5 V), the fan output can be clamped with a Zener
diode, as shown in Figure 9b. The Zener voltage should be
chosen so that it is greater than V

but less than 6.5 V, allowing

IH

for the voltage tolerance of the Zener. A value of between 3 V
and 5 V is suitable.

12V

PULL-UP

4.7k⍀

*CHOOSE ZD1 VOLTAGE APPROX. 0.8 ⴛ V

TYP

TACH
OUTPUT

OR TACH2

TACH1

ZD1*
ZENER

V

CC

FAN SPEED

COUNTER

CC

Figure 9b. Fan with Tach. Pull-Up to Voltage >6.5 V (e.g.,
12 V) Clamped with Zener Diode

If the fan has a strong pull-up (less than 1 kΩ) to 12 V, or a
totem-pole output, a series resistor can be added to limit the
Zener current, as shown in Figure 9c. Alternatively, a resistive
attenuator may be used, as shown in Figure 9d.

R1 and R2 should be chosen such that:

2 V < V

PULLUP

× R2/(R

+ R1 + R2) < 5 V

PULLUP

The fan inputs have an input resistance of nominally 160 kΩ to
ground, so this should be taken into account when calculating
resistor values.

With a pull-up voltage of 12 V and pull-up resistor less than
1 kΩ, suitable values for R1 and R2 would be 100 kΩ and 47 kΩ.
This will give a high input voltage of 3.83 V.

12V

TACH
O/P

PULL-UP

TYP <1k⍀

OR TOTEM-POLE

*CHOOSE ZD1 VOLTAGE APPROX. 0.8 ⴛ V

R1

10k⍀

TACH1

OR TACH2

ZD1
ZENER*

V

CC

FAN SPEED

COUNTER

CC

Figure 9c. Fan with Strong Tach. Pull-Up to >VCC or
Totem-Pole Output, Clamped with Zener and Resistor

12V

<1k⍀

R1*

TACH
OUTPUT

OR TACH2

R2*

*SEE TEXT

TACH1

V

CC

FAN SPEED

COUNTER

Figure 9d. Fan with Strong Tach. Pull-Up to >VCC or
Totem-Pole Output, Attenuated with R1/R2

FAN SPEED CONTROL

Fan speed is controlled using pulsewidth modulation (PWM).
The PWM outputs (Pins 1 and 24) give a pulse output with a
programmable frequency (default 250 Hz) and a duty-cycle
defined by the contents of the relevant fan speed register, or by
the automatic fan speed control when this mode is enabled. The
speed at which a fan runs is determined by fault conditions and
the settings of various control and mask registers.

A fan can only be driven if it is defined as being supported by
the controller in register 02h. The ADM1029 supports up to
two fans, so Bits 0 and 1 of this register are permanently set.
This register is read-only.

–14–

REV. 0

ADM1029

A fan will only be driven if it is defined as being supported by
the system in register 03h. If Bit 0 of this register is set, it indi­cates that Fan 1 is installed. This is the power-on default. If
Bit 1 is set, it indicates that Fan 2 is installed. This bit is set by
the state of Pin 18 at power-up. This register is read/write and
the default/power-on setting can be overwritten. If a fan is not
supported in register 03h it will not be driven, even if it is physi­cally installed.

The PWM outputs are open-drain outputs. They require pull-up
resistors and must be amplified and buffered to drive the fans.

Minimum Speed

The normal operating fan speed is set by the four LSBs of the
Fan 1 and Fan 2 Minimum/Alarm Speed Registers (addresses
60h, 61h). These bits also set the minimum speed at which a fan
will run in automatic control mode. These bits should be set to
05h. This corresponds to 33% PWM duty-cycle, which is the
lowest speed at which most fans will run reliably.

Fan(s) will run at minimum speed if there is no fault condition,
automatic fan speed is disabled, and there are no other over­riding conditions.

Alarm Speed

Alarm speed is set by the four MSBs of the Fan 1 and Fan 2
Minimum/Alarm Speed Registers (addresses 60h, 61h). Fan(s)
will run at alarm speed if any of the following conditions occurs,
assuming the condition has not been masked out using the Fan
Event Mask Registers:

•

Setting Bit 0 of register 07h forces Fan 1 to run at alarm speed

(Set Fan x Alarm Speed Register).

•

Setting Bit 1 of register 07h forces Fan 2 to run at alarm speed
(Set Fan x Alarm Speed Register).

If monitoring is disabled by clearing Bit 4 of the Con­figuration Register, all fans controlled by the ADM1029
will run at alarm speed.

•

When a GPIO pin is configured as an input by setting Bit 0 of
the corresponding GPIO Behavior Register, and Bit 4 of the
GPIO Behavior Register is also set, all fans controlled by the
ADM1029 will go to alarm speed when the logic input is
asserted (high or low, depending on the polarity bit, Bit 1 of
the corresponding GPIO Behavior Register).

•

If Bit 7 of a Fan Fault Action Register is set (18h—Fan 1, 19h
—Fan 2) the corresponding fan will go to alarm speed when
CFAULT is pulled low by an external source.

•

If a tach measurement exceeds the set limit, all fans controlled
by the ADM1029 will run at alarm speed.

•

If a fan fault input pin is asserted (low), all fans controlled by
the ADM1029 will run at alarm speed.

•

If Bit 1 of a Temp. Fault Action Register is set (40h—Local
Sensor, 41h—Remote 1, 42h—Remote 2), all fans controlled
by the ADM1029 will go to alarm speed if the corresponding
temperature high limit is exceeded.

•

If Bit 5 of a Temp. Fault Action Register is set, all fans con­trolled by the ADM1029 will go to alarm speed if a temperature
input crosses the corresponding temperature low limit, the
direction depending on the setting of Bit 3 of the Temp. Con­trol register. (0 = alarm when input goes below low limit, 1 =
alarm when input goes above low limit).

•

If Bit 1 of an AIN Behavior Register is set (50h—AIN0,
51h—AIN1), all fans controlled by the ADM1029 will go to
alarm speed if the corresponding AIN high limit is exceeded.

•

If Bit 5 of an AIN Behavior Register is set, all fans controlled
by the ADM1029 will go to alarm speed if an analog input
crosses the corresponding AIN low limit, the direction depend­ing on the setting of Bit 3 of the AIN control register. (0 =
alarm when input goes below low limit, 1 = alarm when input
goes above low limit).

•

If a thermal override occurs while the ADM1029 is in sleep
mode, all fans controlled by the ADM1029 will run at
alarm speed.

Hot-Plug Speed

Hot-plug speed is set by the four LSBs of the Fan 1 and Fan 2
Configuration Registers (addresses 68h and 69h). The PWM
frequency is set by Bits 4 and 5 of these registers, while Bits 6
and 7 set the number of pulses per revolution for fan speed
measurement.

Fan(s) will run at hot-plug speed if any of the following condi­tions occur, assuming the condition has not been masked using
the Fan Event Mask Registers:

•

If a fan is unplugged, the other fan (if any) controlled by the
ADM1029 will run at hot-plug speed.

•

Setting Bit 0 of register 08h forces Fan 1 to run at hot-plug
speed (Set Fan x Hot-Plug Speed).

•

Setting Bit 1 of register 08h forces Fan 2 to run at hot-plug
speed (Set Fan x Hot-Plug Speed).

•

When a GPIO pin is configured as an input by setting Bit 0 of
the corresponding GPIO Behavior Register, and Bit 5 of the
GPIO Behavior Register is also set, all fans controlled by the
ADM1029 will go to hot-plug speed when the logic input is
asserted (high or low, depending on the polarity bit, Bit 1 of
the corresponding GPIO Behavior Register).

•

If Bit 6 of a Fan Fault Action Register is set (18h for Fan 1,
19h for Fan 2) the corresponding fan will go to hot-plug speed
when CFAULT is pulled low by an external source.

Note: If operating conditions and register settings are such that
both alarm speed and hot-plug speed would be triggered, which
one takes priority is determined by Bit 5 of the Fan 1 and Fan 2
Status Registers (addresses 10h and 11h). If this bit is set, hot-plug
speed takes priority. If it is cleared, alarm speed takes priority.

Full Speed

Fans will run at full speed if the corresponding bits in the Set
Fan x Full Speed Register (address 09h) are set: Bit 0 for Fan 1
and Bit 1 for Fan 2.

Fan Mask Registers

The effect of various conditions on fan speed can be enabled or
disabled by mask registers. In all these registers, setting Bit 0 of
the register enables Fan 1 to go to alarm speed or hot-plug speed if
the corresponding event occurs, while setting Bit 1 enables Fan

2. Clearing these bits masks the effect of the corresponding
event on fan speed.

Registers 20h and 21h are Fan Event Mask Registers. Bits 0 and
1 of register 20h enable (bit set) or mask (bit clear) the effect of
a Fan 1 fault (underspeed or fault input) on Fan 1 and Fan 2
speed. Similarly, Bits 0 and 1 of register 21h enable (bit set)

REV. 0

–15–