Analog Devices ADM1026JST Datasheet

PRELIMINARY TECHNICAL DA T A

Complete Thermal and System

Management Controller

Preliminary Technical Data ADM1026

FEATURES Up to 19 Analog Measurement Channels (Including Inter-

nal Measurements) Up to 8 Fan Speed Measurement Channels Up to 17 General-Purpose Logic I/O Pins Remote Temperature Measurement with Remote Diode

(Two Channels) On-Chip Temperature Sensor

Analog and PWM Fan Speed Control Outputs 2-wire serial System Management Bus (SMBus) 8K bytes on-chip E

PROM Full SMBus 1.1 support including Packet Error Checking (PEC)

FUNCTIONAL BLOCK DIAGRAM

GPIO15 GPIO14 GPIO13

+5V

-12V +12V +V

D2+/A

D2-/A

GPIO12 GPIO11 GPIO10

GPIO9 GPIO8

FAN7/GPIO7 FAN6/GPIO6

FAN5GPIO5 FAN4/GPIO4 FAN3/GPIO3 FAN2/GPIO2 FAN1/GPIO1 FAN0/GPIO0

(0 - +4.0V )

BAT

(0 - +6.66V)

(0 - -16V )

(0 - +16V)

(0 - +3 V )

CCPIN

(0 - + 3 V)

IN0

(0 - + 3 V)

IN1

(0 - + 3 V)

IN2 IN3

(0 - + 3 V)

A A

(0 - + 3 V)

IN4 IN5

(0 - + 3 V)

(0 - +2.5V)

IN6

(0 - +2.5V)

IN7

(0 - +2.5V )

IN8

(0 - +2.5V )

IN9

D1-/NTESTIN

D1+

BANDGAP

TEMP. SEN SOR

GPIO

REGISTERS

FAN SPEED

COUNTER

INP UT

ATTEN UATO RS

AND

ANALOG

MULTIPLEXER

REFERENCE

Chassis Intrusion Detection Interrupt Output (SMBAlert)

Reset Input, Reset Outputs Thermal Interrupt (THERM) Output Shutdown Mode to Minimize Power Consumption Limit Comparison of all Monitored Values

APPLICATIONS Network Servers and Personal Computers Telecommunications Equipment Test Equipment and Measuring Instruments

ADD/

NTESTOUT

ADDRES S

POINTER

REGIST ER

8KBYTE S

E2PROM

TEMP E RA TUR E

CONFIGURATION

REGIST ER

SDA 3.3V M AIN

SERIAL B US

INTERFA C E

3.3VSTB Y

SCL

PWM REGISTER

AND CONTROLLER

VALUE AND

LIMIT

REGISTE RS

LIMIT

COMPA RA TOR S

INT E R R U P T

STATUS

REGISTE RS

INT M AS K

REGISTE RS

GENERATOR

3.3V M AIN RESET

3.3V STBY RESET

RESET IN

ADM1026

INTE RR U P T

MASKING

8-BIT ADC

CONFIGURATION

BANDGAP

REGISTE RS

ANALOG

OUTPUT REGISTE R

AND 8-BIT DAC

TO GPIO

REGISTERS

RESETM AIN

RESETST BY

PWM

INT

GPIO16/THERM

DAC

AGND

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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

DGND

(1.82V O R 2.5 V)

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2001

PRELIMINARY TECHNICAL DA T A

PRODUCT DESCRIPTION

The ADM1026 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. The ADM1026 has up to 19 analog measurement channels. Fifteen analog voltage inputs are provided, of which five are dedicated to monitoring +3.3V, +5V and ±12V power supplies and the processor core voltage. The ADM1026 can monitor two further power-supply voltages by measuring its own analog and digital V can be configured as general-purpose analog inputs to measure 0 to 2.5V, or as a second temperature sensing input.The 8 remaining inputs are general-purpose analog inputs with a range of 0 to 2.5V or 0 to 3V. Finally, the ADM1026 has on on-chip temperature sensor.

The ADM1026 has eight pins that can be configured for fan-speed measurement or as general purpose logic I/O pins. A further 8 pins are dedicated to general-purpose logic I/O. An additional pin can be configured as a general purpose I/O or as the bidirectional THERM pin.

Measured values can be read out via a 2-wire serial System Management Bus, and values for limit comparisons can be programmed in over the same serial bus. The high-speed successive-approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any out-of-limit measurement.

The ADM1026’s 3V to 5.5V supply voltage range, low supply current, and serial interface make it ideal for a wide range of applications. These include hardware monitoring and protection applications in personal computers, telecommunications equipment, and office electronics.

. One input (two pins) is dedicated to a remote temperature-sensing diode. Two further pins

ADM1026–SPECIFICA TIONS

(TA = T

MIN

to T

, VCC = V

MAX

MIN

to V

, unless otherwise noted)

MAX

Parameter Min Typ Max Units Test Conditions/Comments POWER SUPPLY

Supply Voltage, 3.3V STBY, 3.3V MAIN 3.135 3.3 5.5 V Supply Current, I

1.4 3.0 mA Interface Inactive, ADC Active

1.0 mA ADC Inactive, DAC Active 250 µA Shutdown Mode

TEMP. -TO-DIGITAL CONVERTER

Internal Sensor Accuracy ±3 Resolution ±1

External Diode Sensor Accuracy ±3 Resolution ±1

C 60 oC ≤ TD ≤ +100oC

Remote Sensor Source Current 90 µA High Level

5.5 µΑ Low Level

ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS)

Total Unadjusted Error, TUE ±2 % See Note 3 Differential Non-Linearity, DNL ±1 L SB Power Supply Sensitivity ±1 %/V Conversion Time (Analog Input or Int.Temp) 11.38 12.06 m s See Note 4 Conversion Time (External Temperature) 34.13 36.18 m s See Note 4 Input Resistance (+12V, +5V, V

, AIN0 - AIN5) 100 140 200 k⍀

CCP

Input Resistance of -12V pin 10 k⍀ Input Resistance (AIN6 - AIN9) 10 0 140 200 k⍀ Input Resistance of V

Current Drain (when measuring) 105 500 nA Gives CR2032 Battery life > 10 years

BAT

Current Drain (when not measuring) 16 nA

BAT

pin 97 k⍀ See Note 3

BAT

ANALOG OUTPUT

Output Voltage Range 0 2.5 V Total Unadjusted Error, TUE ±3 % I

= 2mA

Full-Scale Error ±1 ± 3 % Zero Error 2 LS B No Load Differential Non-Linearity, DNL ±1 L SB Monotonic by Design Integral Non-Linearity ±1 LS B Output Source Current 2 mA Output Sink Current 1 m A

REFERENCE OUTPUT

Output Voltage 1.8 1.82 1.84 V Bit 2 of Register 07h = 0 Output Voltage 2.47 2.50 2.53 V Bit 2 of Register 07h = 1 Line Regulation TB D %/V Load Regulation TB D µV/mA Short-Circuit Current TB D mA Output Current Source 2 mA Output Current Sink 2 m A

–2–

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PRELIMINARY TECHNICAL DA T A

ADM1026

Specifications (Continued)

Parameter Min Ty p Max Units Test Conditions/Comments FAN RPM-TO-DIGITAL CONVERTER See Note 5

Accuracy ±6 % Full-Scale Count 255 FAN0 TO FAN7 Nominal Input RPM 8800 RPM Divisor = 1, Fan Count = 153 (Note 5) 4400 RPM Divisor = 2, Fan Count = 153

2200 RPM Divisor = 4, Fan Count = 153 1100 RPM Divisor = 8, Fan Count = 153

Internal Clock Frequency 21.1 22.5 23.9 kHz

OPEN-DRAIN O/P'S, PWM, GPIO0-16

Output High Voltage, V Output Low Voltage, V

2.4 V I

0.4 V I

PWM Output Frequency 75 Hz

OPEN-DRAIN DIGITAL OUTPUTS

 INT

, RESETMAIN

Output Low Voltage, V High Level Output Leakage Current, I

, RESETSTBY

))

)

))

0.4 V I

0.1 1 µA V

RESET Pulse Width 140 180 240 ms

OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)

Output Low Voltage, V High Level Output Leakage Current, I

0.1 1 µA V

0.4 V I

SERIAL BUS DIGITAL INPUTS (SCL, SDA)

Input High Voltage, V Input Low Voltage, V

2.2 V

0.8 V

Hysteresis 500 mV

DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN0-7, GPIO0-16) See Notes 6 and 7

Input High Voltage, V Input Low Voltage, V

2.4 V VCC = 3.3V

0.8 V VCC = 3.3V

Hysteresis (Fan 0 - 7) 250 mV VCC = 3.3V

RESETMAIN, RESETSTBY

RESETMAIN Threshold 2.94 V RESETMAIN triggered from AV RESETSTBY Threshold 3.08 RESETSTBY triggered from DV RESETMAIN Hysteresis 60 mV RESETSTBY Hysteresis 50 mV

DIGITAL INPUT CURRENT

Input High Current, I Input Low Current, I Input Capacitance, C

IL IN

-1 µA VIN = V 1µAV

20 pF

EEPROM RELIABILITY

Endurance 100 700 K cycles See Note 9

Data Retention 10 0 Years See Note 10

SERIAL BUS TIMING

Clock Frequency, f Glitch Immunity, t Bus Free Time, t Start Setup Time, t Start Hold Time, t SCL Low Time, t SCL High Time, t

SCLK SW

BUF

SU;STA

HD;STA

LOW

HIGH

SCL, SDA Rise Time, t SCL, SDA Fall Time, t

4.7 µ s See Figure 1

4.7 µ s See Figure 1 4 µ s See Figure 1

400 kHz See Figure 1

50 n s See Figure 1

1000 ns See Figure 1

300 µ s See Figure 1

= 3.0mA, VCC = 3.3V

OUT

= -3.0mA, VCC = 3.3V

OUT

= -3.0mA, VCC = 3.3V

OUT

= V

OUT

= -3.0mA, VCC = 3.3V

= V

= 0

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PRELIMINARY TECHNICAL DA T A

ADM1026 Specifications (Continued)

Parameter Min Ty p Max Units Test Conditions/Comments

Data Setup Time, t Data Hold Time, t

NOTES

All voltages are measured with respect to GND, unless otherwise specified

Typicals are at TA=25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3V

TUE (Total Unadjusted Error) includes Offset, Gain and Linearity errors of the ADC, multiplexer and on-chip input attenuators. VBAT input is only linear for VBAT voltages greater than 1.5V.

Total analog monitoring cycle time is nominally 273ms, made up of 18 ⫻ 11.38ms measurements on analog input and internal temperature channels, and 2 ⫻ 34.13ms measurements on external temperature channels.

The total fan count is based on 2 pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and the fan speed. See section on Fan Speed Monitoring for more details.

ADD is a three-state input that may be pulled high, low or left open-circuit.

Logic inputs will accept input high voltages up to 5V even when device is operating at supply voltages below 5V.

Timing specifications are tested at logic levels of V

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117 and measured at -40°C, 25°C and 85°C. Typical Endurance at 25°C is 700,000 cycles.

Retention lifetime equivalent at junction temperature (Tj) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6eV will

SU;DAT

HD;DAT

= 0.8V for a falling edge and V

derate with junction temperature as shown in Figure 2.

250 n s See Figure 1 300 n s See Figure 1

= 2.1V for a rising edge.

ABSOLUTE MAXIMUM RATINGS*

Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . 6.5 V

Voltage on 12V V Voltage on -12V V

Voltage on Analog Pins . . . . . . . . . .-0.3V to (V

Pin . . . . . . . . . . . . . . . . . . . . . . . . +20V

Pin . . . . . . . . . . . . . . . . . . . . . . . -20V

+0.3V)

Voltage on Open Drain Digital Pins . . . . . . -0.3V to 6.5V

Input Current at any pin . . . . . . . . . . . . . . . . . . . . . . ±5mA

Package Input Current . . . . . . . . . . . . . . . . . . . . . . ±20mA

Maximum Junction Temperature (T

max) . . . . . . .150 °C

Storage Temperature Range . . . . . . . . .–65°C to +150°C

Lead Temperature, Soldering

Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . .+215°C

Infra-Red 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . +200°C

ESD Rating -12V

pin . . . . . . . . . . . . . . . . . . . . . 1000 V

ESD Rating all other pins . . . . . . . . . . . . . . . . . . . 2000 V

*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent

damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

48-Pin LQFP Package:

= 50°C/Watt, θ

= 10°C/Watt

ORDERING GUIDE

GPIO9

GPIO8 FAN0/GPIO0 FAN1/GPIO1 FAN2/GPIO2 FAN3/GPIO3

3.3V MAIN DGND

FAN4/GPIO4 FAN5/GPIO5 FAN6/GPIO6 FAN7/GPIO7

PIN CONFIGURATION

GPIO12

GPIO13

GPIO14

ADM10 26

(Not to Scale)

16 CI

GPIO15 43

TOP VIEW

INT

PWM

PIN 1 IDE NT IF IER

1 2 3 4 5 6 7 8

9 10 11 12

GPIO11

GPIO10

SCL

SDA

ADD/NTESTOUT

THERM

GPIO16/ 42

RESETST

)

- 3V

IN0

RESETMAIN

- 3V

IN1

IN2

IN3

A 40

AGN

IN4

A 37

(0 - 3V )

IN5

(0 - 2.5V)

IN6

(0 - 2.5V)

IN7

(0 - 3V)

CCP

(0 - 16V)

+12V

(0 - 16V)

-12V

+5V

(0 - 6.66 V )

(0 - 4.4V)

BAT

(0 - 2.5 V )

D2+/A

IN8

(0 - 2.5V )

D2-/A

IN9

D1+

D1-/NTESTIN

EF R

3.3V STBY

Temperature Package Package

Model Range Description Option

ADM1026JST 0°C to +100°C 48-Pin LQFP ST48

SCL

SDA

LOW

HD;STA

BUF

HD;DAT

HIGH

SU;DAT

Figure 1. Diagram for Serial Bus Timing

–4–

HD;STA

SU;STA

SU;STO

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PRELIMINARY TECHNICAL DA T A

ADM1026

PIN FUNCTION DESCRIPTION

PIN NO. MNEMONIC TYPE DESCRIPTION

1 GPIO9 Digital I/O 2 GPIO8 Digital I/O 3 FAN0/GPIO0 Digital I/O Fan tachometer input, or can be re-configured as a general purpose

4 FAN1/GPIO1 Digital I/O Fan tachometer input, or can be re-configured as a general purpose

5 FAN2/GPIO2 Digital I/O Fan tachometer input, or can be re-configured as a general purpose

6 FAN3/GPIO3 Digital I/O Fan tachometer input, or can be re-configured as a general purpose

7 3.3V MAIN Analog Input Monitors the main 3.3V system supply. Does NOT power device. 8 DGND Ground Ground pin for digital circuits. 9 FAN4/GPIO4 Digital I/O Fan tachometer input, or can be re-configured as a general purpose

General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output.

digital I/O pin. This has an internal 10k⍀ pullup resistor to 3.3VSTBY

10 FAN5/GPIO5 Digital I/O Fan tachometer input, or can be re-configured as a general purpose

digital I/O pin. This has an internal 10k⍀ pullup resistor to 3.3VSTBY

11 FAN6/GPIO6 Digital I/O Fan tachometer input, or can be re-configured as a general purpose

digital I/O pin. This has an internal 10k⍀ pullup resistor to 3.3VSTBY

12 FAN7/GPIO7 Digital I/O Fan tachometer input, or can be re-configured as a general purpose

digital I/O pin. This has an internal 10k⍀ pullup resistor to 3.3VSTBY 13 SCL Digital Input Open-drain Serial Bus Clock. Requires 2.2k⍀ pullup resistor. 14 SDA Digital I/O Serial Bus Data. Open-drain output. Requires 2.2k⍀ pullup resistor. 15 ADD/ Digital Input This is a three-state input that controls the two LSBs of the Serial Bus

NTESTOUT Address. It also functions as the output for NAND tree testing.

16 CI Digital Input An active high input which captures a Chassis Intrusion event in Bit 6

of Status Register 4. This bit will remain set until cleared, so long as

battery voltage is applied to the V

is powered off. 17 INT Digital Output Interrupt Request (open drain). The output is enabled when Bit 1 of

the Configuration Register is set to 1. The default state is disabled.

It has an on-chip 100k⍀ pullup resistor. 18 PWM Digital Output Open drain Pulse-width modulated output for control of fan speed.

This pin defaults to being high for 100% duty cycle for use with n-

MOS drive circuitry. If a p-MOS device is used to drive the fan the

PWM output may be inverted by setting bit 1 of Test Register 1 = 1.

input, even when the ADM1026

BAT

19 RESETSTBY Digital Output Power-on Reset. 5 mA driver (open drain), active low output with a

180 ms typical pulse width. RESETSTBY is asserted whenever

3.3VSTBY is below the reset threshold. It remains asserted for approx.

180ms after 3.3VSTBY rises above the reset threshold. 20 RESETMAIN Digital I/O Power-on Reset. 5 mA driver (open drain), active low output with a

180 ms typical pulse width. RESETMAIN is asserted whenever

3.3V MAIN is below the reset threshold. It remains asserted for

approx. 180ms after 3.3V MAIN rises above the reset threshold. If,

however, 3.3V STBY rises with or before 3.3V MAIN, then

RESETMAIN remains asserted for 180ms after RESETSTBY is de-

asserted. Pin 20 also functions as an active low RESET input.

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PRELIMINARY TECHNICAL DA T A

ADM1026

PIN FUNCTION DESCRIPTION (CONTINUED)

PIN NO. MNEMONIC TYPE DESCRIPTION

21 AGND Ground Ground pin for analog circuits 22 3.3V STBY Power Supply Supplies 3.3V power for the ADM1026. Also monitors 3.3V standby

power rail. 23 DAC Analog Output 0 to 2.5V output for analog control of fan speed. 24 VREF Analog Output Reference voltage output. Can be selected as 1.8V (default) or 2.5V. 25 D1-/NTESTIN Analog Input Connected to cathode of 1st remote temperature sensing diode. If held

high at power up it activates NAND tree test mode. 26 D1+ Analog Input Connected to anode of 1st remote temperature sensing diode. 27 D2-/AIN9 Programmable Connected to cathode of 2nd remote temperature sensing diode, or

Analog Input may be re-configured as a 0 - 2.5V analog input

28 D2+/AIN8 Programmable Connected to anode of 2nd remote temperature sensing diode, or

Analog Input may be re-configured as a 0 - 2.5V analog input

29 V

BAT

30 +5V 31 -12V 32 +12V 33 +V

CCP

Analog Input Monitors battery voltage, nominally +3V. Analog Input Monitors +5 V supply. Analog Input Monitors -12 V supply. Analog Input Monitors +12 V supply.

Analog Input Monitors processor core voltage (0 to 3.0V). 34 AIN7 Analog Input General-purpose 0 to 2.5V analog input. 35 AIN6 Analog Input General-purpose 0 to 2.5V analog input. 36 AIN5 Analog Input General-purpose 0 to 3V analog input. 37 AIN4 Analog Input General-purpose 0 to 3V analog input. 38 AIN3 Analog Input General-purpose 0 to 3V analog input. 39 AIN2 Analog Input General-purpose 0 to 3V analog input. 40 AIN1 Analog Input General-purpose 0 to 3V analog input. 41 AIN0 Analog Input General-purpose 0 to 3V analog input. 42 GPIO16/ Digital I/O

General purpose I/O pin can be configured as a digital input or output.

THERM Can also be configured as a bidirectional THERM pin (open drain). 43 GPIO15 Digital I/O 44 GPIO14 Digital I/O 45 GPIO13 Digital I/O 46 GPIO12 Digital I/O 47 GPIO11 Digital I/O 48 GPIO10 Digital I/O

NOTES

GPIO pins are open-drain and require external pullup resistors.

General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output. General purpose I/O pin can be configured as a digital input or output.

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PRELIMINARY TECHNICAL DA T A

ADM1026

FUNCTIONAL DESCRIPTION GENERAL DESCRIPTION

The ADM1026 is a complete system hardware monitor for microprocessor-based systems. The device communicates with the system via a serial System Management Bus. The serial bus controller has a hardwired address line for device selection (ADD, pin 15), a serial data line for reading and writing addresses and data (SDA, pin 14), and an input line for the serial clock (SCL, pin 13). All control and programming functions of the ADM1026 are performed over the serial bus.

MEASUREMENT INPUTS

Programmability of the analog and digital measurement inputs makes the ADM1026 extremely flexible and versatile. The device has an 8 bit A-to-D converter, and 17 analog measurement input pins that can be configured in different ways.

Pins 25 and 26 are dedicated temperature inputs and may be connected to the cathode and anode of a remote temperature-sensing diode.

Pins 27 and 28 may be configured as a temperature input and connected to a second temperature-sensing diode, or they may be re-configured as analog inputs with a range of 0 to +2.5V.

Pins 29 to 33 are dedicated analog inputs with on-chip attenuators, configured to monitor V and the processor core voltage V

Pins 34 to 41 are general-purpose analog inputs with a range of 0 to +2.5V or 0 to +3V. These are mainly intended for monitoring SCSI termination voltages, but may be used for other purposes.

The ADC also accepts input from an on-chip bandgap temperature sensor that monitors system ambient temperature.

Finally, the ADM1026 monitors the supply from which it is powered, 3.3VSTBY, so there is no need for a separate pin to monitor this power supply voltage.

The ADM1026 has 8 pins that are general-purpose logic I/O pins (pins 1,2 and 43 to 48), a pin that can be configured as GPIO or as a bidirectional thermal interrupt (THERM) pin (pin 42) and 8 pins that can be configured for fan speed measurement or as general-purpose logic pins (pins 3 to 6 and 9 to 12).

SEQUENTIAL MEASUREMENT

When the ADM1026 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in Value Registers. These can be read out over the serial bus, or can be compared with programmed limits stored in the Limit Registers. The results of out of limit comparisons are stored in the Interrupt Status Registers, and will generate an interrupt on the INT line (pin 17).

Any or all of the Interrupt Status Bits can be masked by appropriate programming of the Interrupt Mask Registers.

, +5V, -12V, +12V,

BAT

, respectively.

CCP

CHASSIS INTRUSION

A chassis intrusion input (pin 16) is provided to detect unauthorised tampering with the equipment. This event is latched in a battery-backed register bit.

RESETS

The ADM1026 has two power on reset outputs, RESETMAIN and RESETSTBY, that are asserted when

3.3VMAIN or 3.3VSTBY fall below the reset threshold. These give a 180ms reset pulse at power up. RESETMAIN also functions as an active-low RESET input.

FAN SPEED CONTROL OUTPUTS

The ADM1026 has two outputs intended to control fan speed, though they can also be used for other purposes.

Pin 18 is an open-drain pulse-width modulated (PWM) output with a programmable duty-cycle and an output frequency of 75Hz.

Pin 23 is connected to the output of an on-chip, 8-bit digital-to-analog converter with an output range of zero to

2.5V. Either or both of these outputs may be used to implement

a temperature-controlled fan by controlling the speed of a fan dependent upon the temperature measured by the onchip temperature sensor or remote temperature sensors.

INTERNAL REGISTERS OF THE ADM1026

The ADM1026 contains a large number of data registers. A brief description of the principal registers is given below. More detailed descriptions are given in the relevant sections and in the tables at the end of the data sheet.

Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1026, the first byte of data is always a register address, which is written to the Address Pointer Register.

Configuration Registers: Provide control and configuration for various operating parameters of the ADM1026.

Fan Divisor Registers: Contain counter pre-scaler values for fan speed measurement.

DAC/PWM Control Registers: Contain speed values for PWM and DAC fan drive outputs.

GPIO Configuration Registers: These configure the GPIO pins as input or output and for signal polarity.

Value and Limit Registers: The results of analog voltage inputs, temperature and fan speed measurements are stored in these registers, along with their limit values.

Status Registers: These registers store events from the various interrupt sources.

Mask Registers: Allow masking of individual interrupt sources.

EEPROM

The ADM1026 has 8K bytes of non-volatile, ElectricallyErasable Programmable Read-Only Memory (EEPROM), from register addresses 8000h to 9FFFh. This may be used for permanent storage of data that will not be lost when the ADM1026 is powered down, unlike the data in

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ADM1026

PRELIMINARY TECHNICAL DA T A

the volatile registers. Although referred to as Read Only Memory, the EEPROM can be written to (as well as read from) via the serial bus in exactly the same way as the other registers. The only major differences between the E2PROM and other registers are:

1. An EEPROM location must be blank before it can be written to. If it contains data, it must first be erased.

2. Writing to EEPROM is slower than writing to RAM.

3. Writing to the EEPROM should be restricted because it has a limited write/cycle life of 100,000 write operations, due to the usual EEPROM wear-out mechanisms.

The E two key E

PROM in the ADM1026 has been qualified for

PROM memory characteristics:- memory

cycling endurance and memory data retention. Endurance qualifies the ability of the E

PROM to be cycled through many Program, Read and Erase cycles. In real terms, a single endurance cycle is composed of four independent, sequential events. These events are defined as follows:

(a) initial page erase sequence (b) read/verify sequence (c) program sequence (d) second read/verify sequence In reliability qualification, every byte is cycled from 00h

to FFh until a first fail is recorded signifying the endurance limit of the E

Retention quantifies the ability of the memory to retain its programmed data over time. The E

PROM memory.

PROM in the ADM1026 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (Tj = 55°C). As part of this qualification procedure, the E

PROM memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the

PROM memory is guaranteed to retain its data for its

E full specified retention lifetime every time the E

PROM is

reprogrammed. It should be noted that retention lifetime

based on an activation energy of 0.6eV will derate with Tj as shown in Figure 2.

Figure 2. E2PROM Memory Retention

SERIAL BUS INTERFACE

Control of the ADM1026 is carried out via the serial System Management Bus (SMBus). The ADM1026 is connected to this bus as a slave device, under the control of a master device.

The ADM1026 has a 7-bit serial bus slave address. When the device is powered up, it will do so with a default serial bus address. The five MSB's of the address are set to 01011, the two LSB's are determined by the logical states of pin 15 (ADD/NTESTOUT). This is a three-state input that can be grounded, connected to V

or left open-

circuit to give three different addresses.

TABLE 1. ADDRESS PIN TRUTH TABLE

ADD Pin A1 A0

GND 0 0

No Connect 1 0

SCL

SDA

STAR T BY

MASTER

SCL

(CON T IN UED)

SDA

(CON T I N U E D)

1 91

1 0 1 1 A1 A0 D7

FRAME 1

SLAVE ADDRESS

FRAME 3

DATA BYTE

R/W

ACK. BY

SLAVE

ACK. BY

SLAVE

Figure 3a. General SMBus Write Timing Diagram

–8–

1 99

D5 D4 D3

FRAME 2

COMMAND CODE

ACK. BY

SLAVE

D4 D3 D2 D1

FRAME N

DATA BYTE

ACK. BY

SLAVE

STOP BY

MASTER

REV. PrP

PRELIMINARY TECHNICAL DA T A

ADM1026

1 91

SCL

SDA

STAR T BY

MASTER

SCL

(CON T IN UED)

SDA

(CON T I N U E D)

1011

FRAME 1

SLAVE ADDRESS

DATA BYTE

FRAME 3

R/W

ACK. BY

SLAVE

ACK. BY

MASTER

Figure 3b. General SMBus Read Timing Diagram

If ADD is left open-circuit the default address will be

0101110. ADD is sampled only at power-up, so any changes made while power is on will have no immediate effect.

The facility to make hardwired changes to device address allows the user to avoid conflicts with other devices sharing the same serial bus, for example if more than one ADM1026 is used in a system.

GENERAL SMBUS TIMING

Figures 3a and 3b show timing diagrams for general read and write operations using the SMBus. The SMBus specification defines specific conditions for different types of read and write operation, which are discussed later.

The general SMBus protocol operates as follows:

1. The master initiates data transfer by establishing a START condition, defined as a high to low transition on the serial data line SDA whilst the serial clock line SCL remains high. This indicates that a data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next 8 bits, consisting of a 7-bit slave address (MSB first) plus a R/W bit, which determines the direction of the data transfer, i.e. whether data will be written to or read from the slave device (0 = write, 1 = read).

The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowledge Bit, and holding it low during the high period of this clock pulse. All other devices on the bus now remain idle whilst the selected device waits for data to be read from or written to it. If the R/W bit is a 0 then the master will write to the slave device. If the R/W bit is a 1 the master will read from the slave device.

2. Data is sent over the serial bus in sequences of 9 clock pulses, 8 bits of data followed by an Acknowledge Bit from the slave device. Data transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low to high transition when the clock is high may be interpreted as a STOP signal.

If the operation is a write operation, the first data byte

D4 D3 D2 D1

FRAME 2

DATA BYTE

1 99

D4 D3 D2 D1

FRAME N

DATA BYTE

ACK. BY

MASTER

NO ACK.

STOP BY MASTER

after the slave address is a command byte. This tells the slave device what to expect next. It may be an instruction such as telling the slave device to expect a block write, or it may simply be a register address that tells the slave where subsequent data is to be written.

Since data can flow in only one direction as defined by the R/W bit, it is not possible to send a command to a slave device during a read operation. Before doing a read operation, it may first be necessary to do a write operation to tell the slave what sort of read operation to expect and/or the address from which data is to be read.

3. When all data bytes have been read or written, stop conditions are established. In WRITE mode, the master will pull the data line high during the 10th clock pulse to assert a STOP condition. In READ mode, the master device will release the SDA line during the low period before the 9th clock pulse, but the slave device will not pull it low. This is known as No Acknowledge. The master will then take the data line low during the low period before the 10th clock pulse, then high during the 10th clock pulse to assert a STOP condition.

Note: If it is required to perform several read or write operations

in succession, the master can send a repeat start condition instead of a stop condition to begin a new operation.

SMBUS PROTOCOLS FOR RAM AND EEPROM

The ADM1026 contains volatile registers (RAM) and non-volatile EEPROM. RAM occupies address locations from 00h to 6Fh, whilst EEPROM occupies addresses from 8000h to 9FFFh.

Data can be written to and read from both RAM and EEPROM as single data bytes and as block (sequential) read or write operations of 32 data bytes, which is the maximum block size allowed by the SMBus specification.

Data can only be written to unprogrammed EEPROM locations. To write new data to a programmed location it is first necessary to erase it. EEPROM erasure cannot be done at the byte level; the EEPROM is arranged as 128 pages* of 64 bytes, and an entire page must be erased.

The EEPROM has three RAM registers associated with it,

REV. PrP

–9–

ADM1026

PRELIMINARY TECHNICAL DA T A

EEPROM Registers 1, 2 and 3 at addresses 06h, 0Ch and 13h. EEPROM Registers 1 and 2 are for factory use only. EEPROM Register 3 is used to set up the EEPROM operating mode.

Setting bit 0 of EEPROM Register 3 puts the EEPROM into Read Mode. Setting bit 1 puts it into Programming Mode. Setting Bit 2 puts it into Erase Mode.

One, and only one of these bits must be set before the EEPROM may be accessed, setting no bits or more than one of them will cause the device to respond with No Acknowledge if an EEPROM read, program or erase operation is attempted.

It is important to distinguish between SMBus write operations such as sending an address or command, and EEPROM programming operations. It is possible to write an EEPROM address over the SMBus whatever the state of EEPROM register 3. However, EEPROM Register 3 must be correctly set before a subsequent EEPROM operation can be performed. For example, when reading from the EEPROM, bit 0 of EEPROM Register 3 can be set, even though SMBus write operations are required to set up the EEPROM address for reading.

Bit 3 of EEPROM Register 3 is used for EEPROM write protection. Setting this bit will prevent accidental programming or erasure of the EEPROM. If a an EEPROM write or erase operation is attempted with this bit set, the ADM1026 will respond with No Acknowledge. This bit is write once and can only be cleared by power-on reset.

EEPROM Register bit 7 is used for clock extend. Programming an EEPROM byte takes approximately 250µs, which would limit the SMBus clock for repeated or block write operations. Since EEPROM block read/write access is slow, it is recommended that this Clock Extend bit normally be set to 1. This allows the ADM1026 to pull SCL low and extend the clock pulse when it cannot accept any more data.

*Although the EEPROM is arranged into 128 pages, only 124 pages are available to the user. The last 4 pages are reserved for manufacturing purposes and cannot be erased/ rewritten.

ADM1026 WRITE OPERATIONS

The SMBus specification defines several protocols for different types of read and write operations. The ones used in the ADM1026 are discussed below. The following abbreviations are used in the diagrams:

S - START P - STOP R - READ W - WRITE A - ACKNOWLEDGE A - NO ACKNOWLEDGE The ADM1026 uses the following SMBus write protocols:

Send Byte

In this operation the master device sends a single command byte to a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master asserts a STOP condition on SDA and the transaction ends.

In the ADM1026, the send byte protocol is used to write a register address to RAM for a subsequent single byte read from the same address or block read or write starting at that address. This is illustrated in Figure 4a.

12 3 4 56

SLAVE

ADDRESS

RAM

ADDRESS

(00h TO 6Fh)

Figure 4a. Setting A RAM Address For Subsequent Read

If it is required to read data from the RAM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read, block read or block write operation, without asserting an intermediate stop condition.

Write Byte/Word

In this operation the master device sends a command byte and one or two data bytes to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

7. The slave asserts ACK on SDA.

8. The master sends a data byte (or may assert STOP at this point).

9. The slave asserts ACK on SDA.

10.The master asserts a STOP condition on SDA to end the transaction.

In the ADM1026, the write byte/word protocol is used for four purposes. The ADM1026 knows how to respond by the value of the command byte and EEPROM register 3.

1. Write a single byte of data to RAM. In this case the command byte is the RAM address from 00h to 6Fh and the (only) data byte is the actual data. This is illustrated in Figure 4b.

12 345678

SLAVE

ADDRESS

RAM

ADDRESS

(00h TO 6Fh)

ADATA A P

Figure 4b. Single Byte Write To RAM

2. Set up a two byte EEPROM address for a subsequent read or block read. In this case the command byte is

–10–

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PRELIMINARY TECHNICAL DA T A

ADM1026

the high byte of the EEPROM address from 80h to 9Fh. The (only) data byte is the low byte of the EEPROM address. This is illustrated in Figure 4c.

12 3 4 5 6 78

SLAVE

ADDRESS

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

EEPROM

ADDRESS

LOW BYTE

(00h TO FFh)

Figure 4c. Setting An EEPROM Address

If it is required to read data from the EEPROM immediately after setting up the address, the master can assert a repeat start condition immediately after the final ACK and carry out a single byte read, block read or block write operation, without asserting an intermediate stop condition. In this case bit 0 of EEPROM Register 3 should be set.

3. Erase a page of EEPROM memory. EEPROM memory can be written to only if it is unprogrammed. Before writing to one or more EEPROM memory locations that are already programmed, the page or pages containing those locations must first be erased. EEPROM memory is erased by writing an EEPROM page address plus an arbitrary byte of data with bit 2 of EEPROM Register 3 set to 1.

As the EEPROM consists of 128 pages of 64 bytes, the EEPROM page address consists of the EEPROM address high byte (from 80h to 9Fh) and the two MSB's of the low byte. The lower 6 bits of the EEPROM address low byte only specify addresses within a page and are ignored during an erase operation.

12 3 4 5 6 7 8 910

SLAVE

ADDRESS

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

EEPROM

ADDRESS

LOW BYTE

(00h TO FFh)

ARBITRARY

DATA

Figure 4d. EEPROM Page Erasure

Page erasure takes approximately 20ms. If the EEPROM is accessed before erasure is complete, it will respond with No Acknowledge.

4. Write a single byte of data to EEPROM. In this case the command byte is the high byte of the EEPROM address from 80h to 9Fh. The first data byte is the low byte of the EEPROM address and the second data byte is the actual data. Bit 1 of EEPROM Register 3 must be set. This is illustrated in Figure 4e.

12 3 4 5 6 78910

SLAVE

ADDRESS

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

EEPROM

ADDRESS

LOW BYTE

(00h TO FFh)

ADATAAP

Figure 4e. Single Byte Write To EEPROM

Block Write

In this operation the master device writes a block of data to a slave device. The start address for a block write must previously have been set. In the case of the ADM1026 this is done by a Send Byte operation to set a RAM address or a Write Byte/Word operation to set an EEPROM address.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the write bit (low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code that tells the slave device to expect a block write. The ADM1026 command code for a block write is A0h (10100000).

5. The slave asserts ACK on SDA.

6. The master sends a data byte (20h) that tells the slave device 32 data bytes will be sent to it. The master should always send 32 data bytes to the ADM1026.

7. The slave asserts ACK on SDA.

8. The master sends 32 data bytes.

9.The slave asserts ACK on SDA after each data byte.

10. The master sends a PEC (Packet Error Checking)

byte.

11. The ADM1026 checks the PEC byte and issues an

ACK if correct. If incorrect (NACK), the master should resend the data bytes.

12. The master asserts a STOP condition on SDA to end

the transaction.

12 3 4 56789 10

SLAVE

ADDRESS

COMMAND A0h

(BLOCK W RITE)

BYTE

AADATA 1 A

A DATA 2

COUNT

DATA

PEC

Figure 4f. Block Write To EEPROM Or RAM

When performing a block write to EEPROM, bit 1 of EEPROM Register 3 must be set.

Unlike some EEPROM devices which limit block writes to within a page boundary, there is no limitation on the start address when performing a block write to EEPROM, except:

1. There must be at least 32 locations from the start ad-

dress to the highest EEPROM address (9FFF), to avoiding writing to invalid addresses.

2. If the addresses cross a page boundary, both pages must

be erased before programming.

ADM1026 READ OPERATIONS

The ADM1026 uses the following SMBus read protocols:

RECEIVE BYTE

In this operation the master device receives a single byte from a slave device, as follows:

1.The master device asserts a START condition on SDA.

2.The master sends the 7-bit slave address followed by the

read bit (high).

3.The addressed slave device asserts ACK on SDA.

4.The master receives a data byte.

5.The master asserts NO ACK on SDA.

6.The master asserts a STOP condition on SDA and the

transaction ends. In the ADM1026, the receive byte protocol is used to read

a single byte of data from a RAM or EEPROM location whose address has previously been set by a send byte or

REV. PrP

–11–

ADM1026

PRELIMINARY TECHNICAL DA T A

write byte/word operation. This is illustrated in Figure 4g. When reading from EEPROM, Bit 0 of EEPROM register 3 must be set.

12 3456

SLAVE

ADDRESS

DATA

A P

Figure 4g. Single Byte Read From EEPROM Or RAM

BLOCK READ

In this operation the master device reads a block of data from a slave device. The start address for a block read must previously have been set. In the case of the ADM1026 this is done by a Send Byte operation to set a RAM address, or a Write Byte/Word operation to set an EEPROM address. The block read operation itself consists of a Send Byte operation that sends a block read command to the slave, immediately followed by a repeated start and a read operation that reads out multiple data bytes, as follows:

1.The master device asserts a START condition on SDA.

2.The master sends the 7-bit slave address followed by the write bit (low).

3.The addressed slave device asserts ACK on SDA.

4.The master sends a command code that tells the slave device to expect a block read. The ADM1026 command code for a block read is A1h (10100001).

5.The slave asserts ACK on SDA.

6.The master asserts a repeat start condition on SDA.

7.The master sends the 7-bit slave address followed by the read bit (high).

8.The slave asserts ACK on SDA.

9.The ADM1026 sends a byte count data byte that tells the master how many data bytes to expect. The ADM1026 will always return 32 data bytes (20h), which is the maximum allowed by the SMBus 1.1 specification.

10. The master asserts ACK on SDA.

11. The master receives 32 data bytes.

12. The master asserts ACK on SDA after each data byte.

13. The ADM1026 issues a PEC byte to the master. The master should check the PEC byte and issue another block read if the PEC byte is incorrect.

14. A NACK is generated after the PEC byte to signal the end of the read.

15. The master asserts a STOP condition on SDA to end the transaction.

12 3 4 567 89101112

SLAVE

ADDRESS

COMMAND A1h

(BLOCK READ)

SLAVE

ADDRESS

BYTE

COUNT

DATA

ADATA 1

AA S

13 14

PEC

A P

Figure 4h. Block Read From EEPROM or RAM

When block reading from EEPROM, bit 0 of EEPROM register 3 must be set.

–12–

Note: Although the ADM1026 supports Packet Error Checking (PEC), its use is optional. The PEC byte is calculated using CRC-8. The Frame Check Sequence (FCS) conforms to CRC-8 by the polynomial:-

C(x) = x

+ x2 + x1 + 1

Consult SMBus 1.1 specification for more information.

MEASUREMENT INPUTS

The ADM1026 has 17 external analog measurement pins, which can be configured to perform various functions. It also measures two supply voltages, 3.3V MAIN and 3.3V STBY, and the internal chip temperature.

Pins 25 and 26 are dedicated to remote temperature measurement, whilst pins 27 and 28 can be configured as analog inputs with a range of 0 to +2.5V or as inputs for a second remote temperature sensor.

Pins 29 to 33 are dedicated to measuring V

-12V, +12V supplies and the processor core voltage V

BAT

, +5V,

CCP

. The remaining analog inputs, pins 34 to 41 are generalpurpose analog inputs with a range of 0 to +2.5V (pins 34 and 35) or 0 to +3V (pins 36 to 41).

A TO D CONVERTER

These inputs are multiplexed into the on-chip, successive approximation, analog-to-digital converter. This has a resolution of 8 bits. The basic input range is zero to +2.5V, which is the input range of A

IN6

to A

, but five of

IN9

the inputs have built-in attenuators to allow measurement of V V

, +5V, -12V, +12V and the processor core voltage

BAT

, without any external components. To allow for the

CCP

tolerance of these supply voltages, the A to D converter produces an output of 3/4 full-scale (decimal 192) for the nominal input voltage, and so has adequate headroom to cope with overvoltages. Table 2 shows the input ranges of the analog inputs and output codes of the A to D converter.

When the ADC is running, it samples and converts an analog or local temperature input every 711µs (typical value). Each input is measured 16 times and the measurements averaged to reduce noise, so the total conversion time for each input is 11.38ms.

Measurements on the remote temperature (D1 and D2) inputs take 2.13ms. These are also measured 16 times and averaged, so the total conversion time for a remote temperature input is 34.13ms.

INPUT CIRCUITS

The internal structure for the analog inputs are shown in Figure 5. Each input circuit consists of an input protection diode, an attenuator, plus a capacitor to form a firstorder lowpass filter which gives the input immunity to high frequency noise. The -12V input also has a resistor connected to the on-chip reference to offset the negative voltage range so that it is always positive and can be handled by the ADC. The V

input allows the condition

BAT

of a battery such as a CMOS backup battery to be monitored. To reduce current drain from the battery, the lower resistor of the V when a V

BAT

attenuator is not connected, except

BAT

measurement is being made. The total

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PRELIMINARY TECHNICAL DA T A

ADM1026

TABLE 2. A/D OUTPUT CODE VS. V

Input Voltage A/D Output

+12V

-12V

+5VIN3.3VMAIN V

BAT

CCP

AIN (0-5) AIN(6-9) Decimal Binary

3.3VSTBY

<0.0625 <-15.928 <0.026 <0.0172 <0.016 <0.012 <0.012 <0.010 0 00000000

0.062 - 0.125 -15.928 ➝ -15.855 0.026 - 0.052 0.017 - 0.034 0.016 - 0.031 0.012 - 0.023 0.012 - 0.023 0.010 - 0.019 1 00000001

0.125 - 0.187 -15.855 ➝ -15.783 0.052 - 0.078 0.034 - 0.052 0.031 - 0.047 0.023 - 0.035 0.023 - 0.035 0.019 - 0.029 2 00000010

0.188 - 0.250 -15.783 ➝ -15.711 0.078 - 0.104 0.052 - 0.069 0.047 - 0.063 0.035 - 0.047 0.035 - 0.047 0.029 - 0.039 3 00000011

0.250 - 0.313 -15.711 ➝ -15.639 0.104 - 0.130 0.069 - 0.086 0.063 - 0.077 0.047 - 0.058 0.047 - 0.058 0.039 - 0.049 4 00000100

0.313 - 0.375 -15.639 ➝ -15.566 0.130 - 0.156 0.086 - 0.103 0.077 - 0.093 0.058 - 0.070 0.058 - 0.070 0.049 - 0.058 5 00000101

0.375 - 0.438 -15.566 ➝ -15.494 0.156 - 0.182 0.103 - 0.120 0.093 - 0.109 0.070 - 0.082 0.070 - 0.082 0.058 - 0.068 6 00000110

0.438 - 0.500 -15.494 ➝ 15.422 0.182 - 0.208 0.120 - 0.138 0.109 - 0.125 0.082 - 0.094 0.082 - 0.094 0.068 - 0.078 7 00000111

0.500 - 0563 -15.422 ➝ -15.349 0.208 - 0.234 0.138 - 0.155 0.125 - 0.140 0.094 - 0.105 0.094 - 0.105 0.078 - 0.087 8 00001000

4.000 - 4.063 -11.375 ➝ -11.303 1.665 - 1.691 1.110 - 1.127 1.000 - 1.040 0.750 - 0.780 0.750 - 0.780 0.625 - 0.635 64 (1/4-scale) 01000000

8.000 - 8.063 -6.750 ➝ -6.678 3.330 - 3.560 2.220 - 2.237 2.000 - 2.016 1.500 - 1.512 1.500 - 1.512 1.250 - 1.260 128 (1/2-scale) 10000000

12.000 - 12.063 -2.125 ➝ -2.053 4.995 - 5.021 3.330 - 3.347 3.000 - 3.016 2.250 - 2.262 2.250 - 2.262 1.875 - 1.885 192 (3/4 scale) 11000000

15.313 - 15.375 1.705 ➝ 1.777 6.374 - 6.400 4.249 - 4.267 3.828 - 3.844 2.871 - 2.883 2.871 - 2.883 2.392 - 2.402 245 11110101

15.375 - 15.437 1.777 ➝ 1.850 6.400 - 6.426 4.267 - 4.284 3.844 - 3.860 2.883 - 2.895 2.883 - 2.895 2.402 - 2.412 246 11110110

15.437 - 15.500 1.850 ➝ 1.922 6.426 - 6.452 4.284 - 4.301 3.860 - 3.875 2.895 - 2.906 2.895 - 2.906 2.412 - 2.422 247 11110111

15.500 - 15.563 1.922 ➝ 1.994 6.452 - 6.478 4.301 - 4.319 3.875 - 3.890 2.906 - 2.918 2.906 - 2.918 2.422 - 2.431 248 11111000

15.562 - 15.625 1.994 ➝ 2.066 6.478 - 6.504 4.319 - 4.336 3.890 - 3.906 2.918 - 2.930 2.918 - 2.930 2.431 - 2.441 249 11111001

15.625 - 15.688 2.066 ➝ 2.139 6.504 - 6.530 4.336 - 4.353 3.906 - 3.921 2.930 - 2.941 2.930 - 2.941 2.441 - 2.451 250 11111010

15.688 - 15.750 2.139 ➝ 2.211 6.530 - 6.556 4.353 - 4.371 3.921 - 3.937 2.941 - 2.953 2.941 - 2.953 2.451 - 2.460 251 11111011

15.750 - 15.812 2.211 ➝ 2.283 6.556 - 6.582 4.371 - 4.388 3.937 - 3.953 2.953 - 2.965 2.953 - 2.965 2.460 - 2.470 252 11111100

15.812 - 15.875 2.283 ➝ 2.355 6.582 - 6.608 4.388 - 4.405 3.953 - 3.969 2.965 - 2.977 2.965 - 2.977 2.470 - 2.480 253 11111101

15.875 - 15.938 2.355 ➝ 2.428 6.608 - 6.634 4.405 - 4.423 3.969 - 3.984 2.977 - 2.988 2.977 - 2.988 2.480 - 2.490 254 11111110 >15.938 >2.428 >6.634 >4.423 >3.984 >2.988 >2.988 >2.490 255 11111111

REV. PrP

–13–

ADM1026

PRELIMINARY TECHNICAL DA T A

current drain on the V maximum V

voltage = 4V) so a CR2032 CMOS

BAT

pin is 105nA typical (for a

BAT

battery will function in a system in excess of the expected 10 years. Note that when a measurement is not being made of V

the current drain is reduced to 16nA typical.

BAT

Under normal operating conditions, all measurements are made in a round-robin format, and each measurement result is actually 16 digitally averaged measurements. Averaging is not carried out on the V

measurement to

BAT

reduce measurement time and hence reduce the current drain from the battery. The V

current drain when a

BAT

measurement is being made is calculated by: I = (V For V

/100k) *(T

BAT

= 3V;

BAT

PULSE/TPERIOD

)

I = (3/100k) * (711µs/273ms) = 78nA

PULSE

PERIOD

= V

measurement time = 711µs typical

BAT

= Time to measure all analog inputs = 273ms

typical

23.3k

80k

122.2k

116.7k

22.7k

25pF

10pF

35pF

AIN0 - AIN5

(0 - 3V)

AIN6 - AIN9

(0 - 2.5V )

+12V

SETTING OTHER INPUT RANGES

IN0

to A

can easily be scaled to voltages other than

IN9

2.5V or 3V. If the input voltage range is zero to some positive voltage, then all that is required is an input attenuator, as shown in Figure 6.

However, when scaling A

IN0

to A

, it should be noted that

IN5

these inputs already have an on-chip attenuator, as their primary function is to monitor SCSI termination voltages. This attenuator will load any external attenuator. The input resistance of the on-chip attenuator can be between 100k⍀ and 200k⍀. For this tolerance not to affect the accuracy, the output resistance of the external attenuator should be very much lower than this, e.g. 1k⍀ in order to add not more than 1% to the TUE. Alternatively, the input can be buffered using an op-amp.

AIN(0 -9)

Figure 6. Scaling AIN(0 - 9)

R1/R2 = (Vfs-3.0)/3.0 (for A R1/R2 = (V

-2.5)/2.5 (for A

IN0 IN6

to A to A

IN5 IN9

) )

Negative and bipolar input ranges can be accommodated by using a positive reference voltage to offset the input voltage range so that it is always positive.

To monitor a negative input voltage, an attenuator can be used as shown in Figure 7.

REF

18.9k

121.1

-12V

10pF

91.6k

+5V

BAT

CCP

55.2k

61.1k

78.8k

*SEE TEXT

23.3k

116.7k

25pF

50pF

Figure 5. Structure of Analog Inputs

MUX

AIN(0 - 9)

Figure 7. Scaling and Offsetting AIN(0 - 9) for Negative In-

puts

This offsets the negative voltage so that the ADC always sees a positive voltage. R1 and R2 are chosen, so that the ADC input voltage is zero when the negative input voltage is at its maximum (most negative) value, i.e.

R1/R2 = |V

FS-

|/V

This is a simple and cheap solution, but the following point should be noted.

1. Since the input signal is offset but not inverted, the input range is transposed. An increase in the magnitude of the negative voltage (going more negative), will cause the input voltage to fall and give a lower output code from the ADC. Conversely, a decrease in the

–14–

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PRELIMINARY TECHNICAL DA T A

ADM1026

magnitude of the negative voltage will cause the ADC code to increase. The maximum negative voltage corresponds to zero output from the ADC. This means that the upper and lower limits will be transposed.

2. For the ADC output to be full-scale when the negative voltage is zero, V voltage of the ADC, because V and R2. If V

must be greater than the full-scale

is equal to or less than the full-scale

is attenuated by R1

voltage of the ADC the input range is bipolar, but not necessarily symmetrical.

This is only a problem if the ADC output must be fullscale when the negative voltage is zero.

Symmetrical bipolar input ranges can easily be accommodated by making V

equal to the full-scale voltage of the

analog input and adding a third resistor to set the positive full-scale.

AIN(0 - 9)

REFERENCE OUTPUT

The on-chip reference voltage is scaled and buffered at pin 24 to provide a 1.82V or 2.5V reference. This output can source or sink a load current of 2mA. The reference voltage is set to 1.82V if bit 2 of Configuration Register 3 (address 07h) is 0, 2.5V if it is 1. The voltage reference output can be used to provide a stable reference voltage to external circuitry such as LDO's.

TEMPERATURE MEASUREMENT SYSTEM

LOCAL TEMPERATURE MEASUREMENT

The ADM1026 contains an on-chip bandgap temperature sensor, whose output is digitized by the on-chip ADC. The temperature data is stored in the Local Temperature Value Register (address 1Fh). As both positive and negative temperatures can be measured, the temperature data is stored in two's complement format, as shown in Table 3. Theoretically, the temperature sensor and ADC can measure temperatures from -128 tion of 1 T

MAX

C. However, temperatures below T

are outside the operating temperature range of the

C to +127oC with a resolu-

and above

MIN

device, so local temperature measurements outside this range are not possible. Temperature measurement from

C to +127oC is possible using a remote sensor.

-128

Figure 8. Scaling and Offsetting AIN(0 - 9) for Bipolar Inputs

R1/R2 = |V

FS-

|/V

(R3 has no effect as the input voltage at the device pin is zero when V

= minus full-scale)

R1/R3 = (V

FS+

-3.0)/3.0 (for A

-2.5)/2.5 (for A

IN0

IN6

to A to

AIN9

IN5

)

(R2 has no effect as the input voltage at the device pin is equal to V

when VIN = plus full-scale).

REMO TE SENSING

TRANS IST OR

D+

D-

DIODE

N x I

BIAS

REMOTE TEMPERATURE MEASUREMENT

The ADM1026 can measure the temperature of two remote diode sensors or diode-connected transistors, connected to pins 25 and 26 or 27 and 28.

Pins 25 and 26 are a dedicated temperature input channel. Pins 27 and 28 can be configured to measure a diode sensor by clearing bit 3 of Configuration Register 1 (address 00h) to 0. If this bit is 1 then pins 27 and 28 are A

IN9

IN8

and

The forward voltage of a diode or diode-connected transistor, operated at a constant current, exhibits a negative temperature coefficient of about -2mV/ the absolute value of V

, varies from device to device, and

C.Unfortunately,

individual calibration is required to null this out, so the technique is unsuitable for mass-production.

OUT+

TO ADC

OUT-

LOWPASS FILTER

= 65kHz

REV. PrP

Figure 9. Signal Conditioning for Remote Diode temperature Sensors

–15–

ADM1026

PRELIMINARY TECHNICAL DA T A

The technique used in the ADM1026 is to measure the change in V

when the device is operated at two different

currents. This is given by: ∆V

= KT/q x ln(N)

where: K is Boltzmann’s constant q is charge on the carrier T is absolute temperature in Kelvins N is ratio of the two currents Figure 9 shows the input signal conditioning used to mea-

sure the output of a remote temperature sensor. This figure shows the external sensor as a substrate transistor, provided for temperature monitoring on some microprocessors, but it could equally well be a discrete transistor such as a 2N3904.

If a discrete transistor is used, the collector will not be grounded, and should be linked to the base. If a PNP transistor is used the base is connected to the D- input and the emitter to the D+ input. If an NPN transistor is used, the emitter is connected to the D- input and the base to the D+ input.

TABLE 3. TEMPERATURE DATA FORMAT

Temperature Digital Output

-128 °C 1000 0000

and to a chopper-stabilized amplifier that performs the functions of amplification and rectification of the waveform to produce a DC voltage proportional to ∆V

. This

voltage is measured by the ADC to give a temperature output in 8-bit two’s complement format. To further reduce the effects of noise, digital filtering is performed by averaging the results of 16 measurement cycles. A remote temperature measurement takes nominally 2.14ms.

The results of external temperature measurements are stored in 8 bit, twos-complement format, as illustrated in Table 3.

LAYOUT CONSIDERATIONS

Digital boards can be electrically noisy environments, and care must be taken to protect the analog inputs from noise, particularly when measuring the very small voltages from a remote diode sensor. The following precautions should be taken:

1. Place the ADM1026 as close as possible to the remote sensing diode. Provided that the worst noise sources such as clock generators, data/address buses and CRTs are avoided, this distance can be 4 to 8 inches.

2. Route the D+ and D- tracks close together, in parallel, with grounded guard tracks on each side. Provide a ground plane under the tracks if possible.

3. Use wide tracks to minimize inductance and reduce noise pickup. 10 mil track minimum width and spacing is recommended.

-125 °C 1000 0011

-100 °C 1001 1100

-75 °C 1011 0101

-50 °C 1100 1110

-25 °C 1110 0111

-10 oC 11110110 0 °C 0000 0000

+10 °C 0000 1010 +25 °C 0001 1001 +50 °C 0011 0010

+75 °C 0100 1011 +100 °C 0110 0100 +125 °C 0111 1101 +127 °C 0111 1111

To prevent ground noise interfering with the measurement, the more negative terminal of the sensor is not referenced to ground, but is biased above ground by an internal diode at the D- input.

To measure ∆V

, the sensor is switched between operat-

ing currents of I and N x I. The resulting waveform is passed through a 65kHz lowpass filter to remove noise,

GND

D+

D-

GND

Figure 10. Arrangement of Signal Tracks

10 mil. 10 mil.

10 mil. 10 mil. 10 mil. 10 mil.

10 mil.

4. Try to minimize the number of copper/solder joints, which can cause thermocouple effects. Where copper/ solder joints are used, make sure that they are in both the D+ and D- path and at the same temperature.

Thermocouple effects should not be a major problem as

C corresponds to about 240µV, and thermocouple

voltages are about 3µV/

C of temperature difference. Unless there are two thermocouples with a big temperature differential between them, thermocouple voltages should be much less than 200µV.

5. Place a 0.1µF bypass capacitor close to the ADM1026.

6. If the distance to the remote sensor is more than 8 inches, the use of twisted pair cable is recommended. This will work up to about 6 to 12 feet.

7. For really long distances (up to 100 feet) use shielded twisted pair such as Belden #8451 microphone cable. Connect the twisted pair to D+ and D- and the shield to GND close to the ADM1026. Leave the remote end

–16–

REV. PrP

PRELIMINARY TECHNICAL DA T A

ADM1026

of the shield unconnected to avoid ground loops.

Because the measurement technique uses switched current sources, excessive cable and/or filter capacitance can affect the measurement. When using long cables, the filter capacitor may be reduced or removed.

Cable resistance can also introduce errors. 1⍀ series resistance introduces about 0.5

LIMIT VALUES

Limit values for analog measurements are stored in the appropriate limit registers. In the case of voltage measurements, high and low limits can be stored so that an interrupt request will be generated if the measured value goes above or below acceptable values. In the case of temperature, a Hot Temperature or High Limit can be programmed, and a Hot Temperature Hysteresis or Low Limit, which will usually be some degrees lower. This can be useful as it allows the system to be shut down when the hot limit is exceeded, and re-started automatically when it has cooled down to a safe temperature.

ANALOG MONITORING CYCLE TIME

The analog monitoring cycle begins when a one is written to the Start Bit (bit 0), and a zero to the INT_Clear Bit (bit 2) of the Configuration Register. INT_Enable (Bit 1) should be set to one to enable the INT output. The ADC measures each analog input in turn, starting with remote temperature channel 1 and ending with local temperature. As each measurement is completed the result is automatically stored in the appropriate value register. This "round-robin" monitoring cycle continues until it is disabled by writing a 0 to bit 0 of the Configuration Register.

As the ADC will normally be left to free-run in this manner, the time taken to monitor all the analog inputs will normally not be of interest, as the most recently measured value of any input can be read out at any time.

For applications where the monitoring cycle time is important, it can easily be calculated.

The total number of channels measured is: 5 dedicated supply voltage inputs 10 general purpose analog inputs

3.3V

MAIN

3.3V

STBY

Local temperature 2 remote temperature Pins 28 and 27 are measured both as analog inputs AIN8/

AIN9 and as remote temperature input D2+/D2-, irrespective of which configuration is selected for these pins.

If pins 28 and 27 are configured as AIN8/AIN9, the measurements for these channels are stored in registers 27h and 29h and the invalid temperature measurement is discarded. On the other hand, if pins 28 and 27 are configured as D2+/D2-, the temperature measurement is stored in register 29h and there will be no valid result in register 27h.

As mentioned previously, the ADC performs a conversion every 711µs on the analog and local temperature inputs and every 2.13ms on the remote temperature inputs. Each input

REV. PrP

C error.

–17–

is measured 16 times and averaged to reduce noise. The total monitoring cycle time for voltage and tempera-

ture inputs is therefore nominally: (18 ⫻ 16 ⫻ 0.711) + (2 ⫻ 16 ⫻ 2.13) = 273ms The ADC uses the internal 22.5kHz clock, which has a

tolerance of ±6%, so the worst case monitoring cycle time is 290ms.

The fan speed measurement uses a completely separate monitoring loop, as described later.

INPUT SAFETY

Scaling of the analog inputs is performed on chip, so external attenuators are normally not required. However, since the power supply voltages will appear directly at the pins, its is advisable to add small external resistors (e.g. 500Ω) in series with the supply traces to the chip to prevent damaging the traces or power supplies should an accidental short such as a probe connect two power supplies together.

As the resistors will form part of the input attenuators, they will affect the accuracy of the analog measurement if their value is too high.

The worst such accident would be connecting -12V to +12V - a total of 24V difference, with the series resistors this would draw a maximum current of approx. 24mA.

REFERENCE OUTPUT

The ADM1026 has a buffered reference voltage output (pin 24), which can be programmed to 1.82V or 2.5V by clearing or setting bit 2 of Configuration Register 3 (address 07h).

ANALOG OUTPUT

The ADM1026 has a single analog output from an unsigned 8 bit DAC which produces 0 - 2.5V (independent of the reference voltage setting). The input data for this DAC is contained in the DAC Control register (address 04h) The DAC Control Register defaults to FFh during power-on reset, which produces maximum fan speed. The analog output may be amplified and buffered with external circuitry such as an op-amp and transistor to provide fan speed control. During automatic fan speed control, described later, the four MSBs of this register set the minimum fan speed.

Suitable fan drive circuits are given in Figures 11a to 11e. When using any of these circuits, the following points should be noted:

1. All of these circuits will provide an output range from zero to almost +12V, apart from Figure 11a which loses the base-emitter voltage drop of Q1 due to the emitter-follower configuration.

2. To amplify the 2.5V range of the analog output up to 12V, the gain of these circuits needs to be around 4.8.

3. Care must be taken when choosing the op-amp to en-

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