Analog Devices ADM1026 a Datasheet

Complete Thermal System

A

FEATURES

Up to 19 analog measurement channels (including internal

measurements)
Up to 8 fan speed measurement channels
Up to 17 general-purpose logic I/O pins
Remote temperature measurement with remote diode (two

channels)
On-chip temperature sensor
Analog and PWM fan speed control outputs
2-wire serial system management bus (SMBus)
8 kB on-chip EEPROM

GPIO15
GPIO14
GPIO13
GPIO12
GPIO11
GPIO10

GPIO9
GPIO8

FAN7/GPIO7
FAN6/GPIO6
FAN5/GPIO5
FAN4/GPIO4
FAN3/GPIO3
FAN2/GPIO2
FAN1/GPIO1
FAN0/GPIO0

V

BAT

+5 V

IN

–12 V

IN

+12 V

IN

+V
A
A
A
A
A
A

A

IN6

A

IN7

D2+/

IN8

D2–/A

IN9

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

CCP

(0V – +3V)

IN0

(0V – +3V)

IN1

(0V – +3V)

IN2

(0V – +3V)

IN3

(0V – +3V)

IN4

(0V – +3V)

IN5

(0V – +2.5V)
(0V – +2.5V)
(0V – +2.5V)
(0V – +2.5V)

D1+

D1–/NTESTIN

BAND GAP

TEMPERATURE

SENSOR

GPIO

REGISTERS

FAN

SPEED

COUNTER

INPUT

ATTENUATORS

AND

ANALOG

MULTIPLEXER

Figure 1. Functional Block Diagram

AGND V

ADDRESS

POINTER

REGISTER

8k BYTES

EEPROM

AUTOMATIC

FAN SPEED

CONTROL

ADM1026

8-BIT

ADC

BAND GAP

REFERENCE

DGND

Management Controller

ADM1026

Full SMBus 1.1 support includes packet error checking (PEC)
Chassis intrusion detection
Interrupt output (SMBAlert)
Reset input, reset outputs
Thermal interrupt (

Limit comparison of all monitored values

APPLICATIONS

Network servers and personal computers
Telecommunications equipment
Test equipment and measuring instruments

ADD/

NTESTOUT

SERIAL BUS

INTERFACE

(1.82V OR 2.5V)

REF

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

3.3V STBY

SCLSDA

V

PWM REGISTER

AND CONTROLLER

VALUE AND

LIMIT

REGISTERS

LIMIT

COMPARATORS

INTERRUPT

STATUS

REGISTERS

INT MASK

REGISTERS

INTERRUPT

MASKING

CONFIGURATION

REGISTERS

ANALOG

OUTPUT REGISTER

AND 8-BIT DAC

THERM

GENERATOR

CC

GENERATOR

) output

3.3V MAIN

3.3V MAIN
RESET

3.3V STBY
RESET

REGISTERS

RESET IN

100kΩ

V

100kΩ

TO GPIO

V

CC

V

100kΩ

CC

V

CC

CC

RESETMAIN

RESETSTBY

PWM

CI

INT

GPIO16/THERM

DAC

02657-A-001

ADM1026

TABLE OF CONTENTS

Specifications..................................................................................... 3

Measurement Inputs .................................................................. 16

Absolute Maximum Ratings............................................................ 5

Thermal Characteristics .............................................................. 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 8

Product Description....................................................................... 10

Functional Description.............................................................. 10

Internal Registers........................................................................ 11

EEPROM .....................................................................................11

SMBus Protocols for RAM and EEPROM.............................. 13

REVISION HISTORY

3/04—Data Sheet Changed from Rev. 0 to Rev. A

Updated Format..................................................................Universal

Change to Footnote 4, Table 1..........................................................4

Added Figure 15.................................................................................9

Changes to Table 6.......................................................................... 17

Changes to Figure 27...................................................................... 18

Change to Figure 31 ....................................................................... 19

Change to Battery Measurement Input Section ......................... 19

Changes to Table 7.......................................................................... 21

Changes to Equations in Fan Speed Measurement Section...... 26

Change to Chassis Intrusion Input Section ................................ 27

Changes to Reset Input and Outputs Section ............................. 31

Changes to Software Reset Function Section ............................. 34

Changes to Ordering Guide.......................................................... 55

Temperature Measurement System.......................................... 20

Analog Output............................................................................ 22

Fan Speed Measurement ........................................................... 25

Enabling and Clearing Interrupts ............................................ 29

NAND Tree Tests........................................................................ 31

Using the ADM1026 .................................................................. 33

Registers........................................................................................... 36

Detailed Register Descriptions................................................. 38

Outline Dimensions....................................................................... 54

Ordering Guide .......................................................................... 55

5/02—Revision 0: Initial Version

Rev. A | Page 2 of 56

ADM1026

SPECIFICATIONS1, 2, 3

Table 1. TA = T

MIN

to T

, VCC = V

MAX

MIN

to V

, unless otherwise noted.

MAX

Parameter Min Typ Max Test Conditions/Comments Unit

POWER SUPPLY

Supply Voltage, 3.3 V STBY, 3.3 V MAIN 3.0 3.3 5.5 V
Supply Current, I

2.5 4.0 Interface inactive, ADC active mA

CC

TEMPERATURE-TO-DIGITAL CONVERTER

Internal Sensor Accuracy ±3 °C
Resolution ±1 °C
External Diode Sensor Accuracy ±3 0°C < TD < 100°C °C
Resolution ±1 °C
Remote Sensor Source Current 90 High level µA

5.5 Low level µA
ANALOG-TO-DIGITAL CONVERTER (including MUX and attenuators)

Total Unadjusted Error (TUE)4 ±2 %
Differential Nonlinearity (DNL) ±1 LSB
Power Supply Sensitivity ±0.1 %/V
Conversion Time (Analog Input or Internal Temperature)5 11.38 12.06 ms
Conversion Time (External Temperature)5 34.13 36.18 ms
Input Resistance (+5 VIN, V

CCP

, A

− A

IN0

) 80 100 120 kΩ

IN5

Input Resistance of +12 VIN pin 70 100 115 kΩ
Input Resistance of −12 VIN pin 8 10 12 kΩ
Input Resistance (A
Input Resistance of V
V

Current Drain (when measured) 80 100 CR2032 battery life >10 years nA

BAT

V

Current Drain (when not measured) 6 nA

BAT

− A

) 5 MΩ

IN6

IN9

pin4 80 100 120 kΩ

BAT

ANALOG OUTPUT (DAC)

Output Voltage Range 0–2.5 V
Total Unadjusted Error (TUE) ±5 IL = 2 mA %
Zero Error 1 No load LSB
Differential Nonlinearity (DNL) ±1 Monotonic by design LSB
Integral Nonlinearity ±0.5 LSB
Output Source Current 2 mA
Output Sink Current 1 mA

REFERENCE OUTPUT

Output Voltage 1.8 1.82 1.84 Bit 2 of Register 07h = 0 V
Output Voltage 2.47 2.50 2.53 Bit 2 of Register 07h = 1 V
Load Regulation (I
Load Regulation (I

= 2 mA) 0.15 %

SINK

= 2 mA) 0.15 %

SOURCE

Short Circuit Current 25 VCC = 3.3 V mA
Output Current Source 2 mA
Output Current Sink 2 mA

FAN RPM-TO-DIGITAL CONVERTER6

Accuracy ±12 %
Full-Scale Count 255
FAN0 to FAN7 Nominal Input RPM5 8800 Divisor = 1, fan count = 153 RPM
4400 Divisor = 2, fan count = 153 RPM
2200 Divisor = 4, fan count = 153 RPM
1100 Divisor = 8, fan count = 153 RPM
Internal Clock Frequency 20 22.5 25 kHz

OPEN DRAIN O/Ps, PWM, GPIO0 to 16

Output High Voltage, VOH 2.4 I

= 3.0 mA, VCC = 3.3 V V

OUT

Rev. A | Page 3 of 56

ADM1026

Parameter Min Typ Max Test Conditions/Comments Unit

High Level Output Leakage Current, IOH 0.1 1 V

Output Low Voltage, VOL 0.4 I

PWM Output Frequency 75 Hz
DIGITAL OUTPUTS (INT, RESETMAIN, RESETBY)

Output Low Voltage, VOL 0.4 I

RESET Pulse Width

140 180 240 ms

OPEN DRAIN SERIAL DATABUS OUTPUT (SDA)

Output Low Voltage, VOL 0.4 I

High Level Output Leakage Current, IOH 0.1 1 V
SERIAL BUS DIGITAL INPUTS (SCL, SDA)

Input High Voltage, VIH 2.2 V

Input Low Voltage, VIL 0.8 V

Hysteresis 500 mV
DIGITAL INPUT LOGIC LEVELS (ADD, CI, FAN 0 to 7, GPIO 0 to 16)7, 8

Input High Voltage, VIH 2.4 VCC = 3.3 V V

Input Low Voltage, VIL 0.8 VCC = 3.3 V V

Hysteresis (Fan 0 to 7) 250 VCC = 3.3 V mV
RESETMAIN, RESETSTBY

RESETMAIN Threshold

RESETSBY Threshold

RESETMAIN Hysteresis

RESETSTBY Hysteresis

2.89 2.94 2.97 Falling voltage V

3.01 3.05 3.10 Falling voltage V
60 mV
70 mV

DIGITAL INPUT CURRENT

Input High Current, IIH –1 VIN = VCC µA

Input Low Current, IIL 1 V

Input Capacitance, CIN 20 pF
EEPROM RELIABILITY

Endurance9 100 700 kcycles

Data Retention10 10 Years
SERIAL BUS TIMING See Figure 2 for all parameters.

Clock Frequency, f

400 kHz

SCLK

Glitch Immunity, tSW 50 ns

Bus Free Time, t

Start Setup Time, t

Start Hold Time, t

SCL Low Time, t

SCL High Time, t

4.7 µs

BUF

4.7 µs

SU; STA

4 µs

HD; STA

4.7 µs

LOW

4 µs

HIGH

SCL, SDA Rise Time, tr 1000 ns

SCL, SDA Fall Time, tf 300 ns

Data Setup Time, t

Data Hold Time, t

250 ns

SU; DAT

300 ns

HD; DAT

1

All voltages are measured with respect to GND, unless otherwise specified.

2

Typicals are at TA = 25°C and represent the most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.

3

Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.1 V for a rising edge.

4

Total unadjusted error (TUE) includes offset, gain, and linearity errors of the ADC, multiplexer, and on-chip input attenuators. V

greater than 1.5 V (see Figure 15).

5

Total analog monitoring cycle time is nominally 273 ms, made up of 18 ms × 11.38 ms measurements on analog input and internal temperature channels, and

2 ms × 34.13 ms measurements on external temperature channels.

6

The total fan count is based on two pulses per revolution of the fan tachometer output. The total fan monitoring time depends on the number of fans connected and

the fan speed. See the Fan Speed Measurement section for more details.

7

ADD is a three-state input that may be pulled high, low, or left open-circuit.

8

Logic inputs accept input high voltages up to 5 V even when device is operating at supply voltages below 5 V.

9

Endurance is qualified to 100,000 cycles as per JEDEC Std. 22 method A117, and measured at −40°C, +25°C, and +85°C. Typical endurance at +25°C is 700,000 cycles.

10

Retention lifetime equivalent at junction temperature (TJ ) = 55°C as per JEDEC Std. 22 method A117. Retention lifetime based on an activation energy of 0.6 V
derates with junction temperature as shown in Figure 16.

= VCC µA

OUT

= −3.0 mA, VCC = 3.3 V V

OUT

= −3.0 mA, VCC = 3.3 V V

OUT

= –3.0 mA, VCC = 3.3 V V

OUT

= VCC µA

OUT

= 0 µA

IN

is accurate only for V

BAT

voltages

BAT

Rev. A | Page 4 of 56

ADM1026

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Positive Supply Voltage (VCC) 6.5 V
Voltage on +12 V VIN Pin +20 V
Voltage on −12 V VIN Pin −20 V
Voltage on Analog Pins −0.3 V to (VCC + 0.3 V)
Voltage on Open Drain Digital Pins −0.3 V to +6.5 V
Input Current at any Pin ±5 mA
Package Input Current ±20 mA
Maximum Junction Temperature (T

) 150°C

J MAX

Storage Temperature Range −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 200°C
ESD Rating, −12 VIN Pin 1000 V
ESD Rating, All Other Pins 2000 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL CHARACTERISTICS

• 48-Lead LQFP package

• θ

= 50°C/W, θJC = 10°C/W

JA

t

F

t

HIGH

Figure 2. Serial Bus Timing Diagram

t

SU; DAT

S

t

SU; STA

t

HD; STA

SCL

SDA

t

BUF

PS

t

LOW

t

HD; STA

t

R

t

HD; DAT

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

t

SU; STO

P

02657-A-002

Rev. A | Page 5 of 56

ADM1026

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

(0V – 3V)

(0V – 3V)

(0V – 3V)

(0V – 3V)

GPIO10

GPIO11

GPIO12

GPIO13

4847464544434241403938

GPIO14

GPIO15

A

GPIO16/THERM

IN0

(0V – 3V)

IN1

IN2

IN3

A

A

A

A

37

IN4

GPIO9

GPIO8
FAN0/GPIO0
FAN1/GPIO1
FAN2/GPIO2
FAN3/GPIO3

3.3V MAIN
DGND

FAN4/GPIO4
FAN5/GPIO5
FAN6/GPIO6
FAN7/GPIO7

1

PIN 1 IDENTIFIER

2
3
4
5
6
7
8

9
10
11
12

1314151617181920212223

SCL

SDA

ADM1026

TOP VIEW

(Not to Scale)

CI

ADD/NTESTOUT

INT

PWM

RESETSTBY

DAC

AGND

3.3V STBY

RESETMAIN

24

REF

V

A

36

IN5

A

35

IN6

A

34

IN7

+V

33

CCP

+12 V

32

–12 V

31

+5 V

30

V

BAT

29

D2+/A

28

D2–/A

27

D1+

26

D1–/NTESTIN

25

(0V – 3V)
(0V – 2.5V)
(0V – 2.5V)

IN
IN

IN

(0V – 2.5V)

IN8

(0V – 2.5V)

IN9

02657-A-003

Figure 3. Pin Configuration

Table 3.

Pin No. Mnemonic Type Description

1 GPIO9 Digital I/O1 General-purpose I/O pin that can be configured as digital inputs or outputs.
2 GPIO8 Digital I/O1 General-purpose I/O pin that can be configured as digital inputs or outputs.
3 FAN0/GPIO0 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.

4 FAN1/GPIO1 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.

5 FAN2/GPIO2 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be
reconfigured as a general-purpose, open drain, digital I/O pin.

6 FAN3/GPIO3 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin.
7 3.3 V MAIN Analog Input Monitors the main 3.3 V system supply. Does not power the device.
8 DGND Ground Ground pin for digital circuits.
9 FAN4/GPIO4 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin.
10 FAN5/GPIO5 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin.
11 FAN6/GPIO6 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin.
12 FAN7/GPIO7 Digital I/O

Fan tachometer input with internal 10 kΩ pull-up resistor to 3.3 V STBY. Can be

reconfigured as a general-purpose, open drain, digital I/O pin.
13 SCL Digital Input Open Drain Serial Bus Clock. Requires a 2.2 kΩ pull-up resistor.
14 SDA Digital I/O Serial Bus Data. Open drain I/O. Requires a 2.2 kΩ pull-up resistor.
15 ADD/NTESTOUT Digital Input

This is a three-state input that controls the two LSBs of the serial bus address. It also

functions as the output for NAND tree testing.
16 CI Digital Input

An active high input that captures a chassis intrusion event in Bit 6 of Status Register 4.

This bit remains set until cleared, as long as battery voltage is applied to the V

even when the ADM1026 is powered off.
17

INT

Digital Output

Interrupt Request (Open Drain). The output is enabled when Bit 1 of the configuration

register is set to 1. The default state is disabled. It has an on-chip 100 kΩ pull-up resistor.

BAT

input,

Rev. A | Page 6 of 56

ADM1026

Pin No. Mnemonic Type Description

18 PWM Digital Output

19

20

RESETSTBY

RESETMAIN

Digital Output

Digital I/O

21 AGND Ground Ground pin for analog circuits.
22 3.3 V STBY Power Supply Supplies 3.3 V power. Also monitors the 3.3 V standby power rail.
23 DAC Analog Output 0 V to 2.5 V output for analog control of the fan speed.
24 V

Analog Output Reference Voltage Output. Can be selected as 1.8 V (default) or 2.5 V.

REF

25 D1–/NTESTIN Analog Input

26 D1+ Analog Input Connected to the anode of the first remote temperature sensing diode.
27 D2–/A

28 D2+/A

29 V

Programmable

IN9

Programmable

IN8

Analog Input Monitors battery voltage, nominally +3 V.

BAT

30 +5 VIN Analog Input Monitors the +5 V supply.
31

−12 V

IN

Analog Input
32 +12 VIN Analog Input Monitors the +12 V supply.
33 +V
34 A
35 A
36 A
37 A
38 A
39 A
40 A
41 A
42

Analog Input Monitors the processor core voltage (0 V to 3.0 V).

CCP

Analog Input General-purpose 0 V to 2.5 V analog inputs.

IN7

Analog Input General-purpose 0 V to 2.5 V analog inputs.

IN6

Analog Input General-purpose 0 V to 3 V analog inputs.

IN5

Analog Input General-purpose 0 V to 3 V analog inputs.

IN4

Analog Input General-purpose 0 V to 3 V analog inputs.

IN3

Analog Input General-purpose 0 V to 3 V analog inputs.

IN2

Analog Input General-purpose 0 V to 3 V analog inputs.

IN1

Analog Input General-purpose 0 V to 3 V analog inputs.

IN0

GPIO16/THERM

Digital I/O

1

43 GPIO15 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output.
44 GPIO14 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output.
45 GPIO13 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output.
46 GPIO12 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output.
47 GPIO11 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output.
48 GPIO10 Digital I/O1 General-purpose I/O pin that can be configured as a digital input or output.

Open drain pulse width modulated output for control of the fan speed. This pin defaults
to high for the 100% duty cycle for use with NMOS drive circuitry. If a PMOS device is used
to drive the fan, the PWM output may be inverted by setting Bit 1 of Test Register 1 = 1.

Power-On Reset. 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up)
with a 180 ms typical pulse width. RESETSTBY

is asserted whenever 3.3 V STBY is below

the reset threshold. It remains asserted for approximately 180 ms after 3.3 V STBY rises
above the reset threshold.

Power-On Reset. 5 mA driver (weak 100 kΩ pull-up), active low output (100 kΩ pull-up)
with a 180 ms typical pulse width. RESETMAIN

is asserted whenever 3.3 V MAIN is below
the reset threshold. It remains asserted for approximately 180 ms after 3.3 V MAIN rises
above the reset threshold. If, however, 3.3 V STBY rises with or before 3.3 V MAIN, then
RESETMAIN

remains asserted for 180 ms after RESETSTBY is deasserted. Pin 20 also

functions as an active low RESET input.

Connected to a cathode of the first remote temperature sensing diode. If it is held high at
power-on, it activates the NAND tree test mode.

Connected to the cathode of the second remote temperature sensing diode, or the
analog input may be reconfigured as a 0 V− 2.5 V analog input.

Connected to the anode of the second remote temperature sensing diode, or the analog
input may be reconfigured as a 0 V − 2.5 V analog input.

Monitors the −12 V supply.

General-purpose I/O pin that can be configured as a digital input or output. Can also be
configured as a bidirectional THERM

pin (100 kΩ pull-up).

1

GPIO pins are open drain and require external pull-up resistors. Fan inputs have integrated 10 kΩ pull-ups, but these pins become open drain when reconfigured as

GPIOs.

Rev. A | Page 7 of 56

ADM1026

TYPICAL PERFORMANCE CHARACTERISTICS

25
20

15

10

D+ TO GND

5

0

–5

D+ TO V

–10

TEMPERATURE ERROR (°C)

–15
–20

–25

CC

30 60 1200

LEAKAGE RESISTANCE (MΩ)

90

02657-A-004

110
100

90
80
70
60
50

READING (°C)

40
30
20
10

0

0 10 20 30 40 50 60 70 80 90 100 110

PIII TEMPERATURE (°C)

02657-A-007

Figure 4. Temperature Error vs. PCB Track Resistance

14

12

10

8

250mV

6

4

TEMPERATURE ERROR (°C)

100mV

2

0

100 200 300 400 500

0

FREQUENCY (MHz)

Figure 5. Temperature Error vs. Power Supply Noise Frequency

12

10

8

100mV
60mV
40mV

600

Figure 7. Pentium® III Temperature vs. ADM1026 Reading

5

0

–5

–10

–15

TEMPERATURE ERROR (°C)

–20

–25

02657-A-005

01020304050

CAPACITANCE (nF)

02657-A-008

Figure 8. Temperature Error vs. Capacitance Between D+ and D–

80

70

60

50

6

4

TEMPERATURE ERROR (°C)

2

0

100

0 200 300 400 500 600

FREQUENCY (MHz)

Figure 6. Temperature Error vs. Common-Mode Noise Frequency

02657-A-006

Rev. A | Page 8 of 56

40

30

20

TEMPERATURE ERROR (°C)

10

0

100

100mV

60mV

40mV

200 300 400 500

FREQUENCY (MHz)

600

Figure 9. Temperature Error vs. Differential-Mode Noise Frequency

02657-A-009

ADM1026

450

400

350

300

250

200

150

RESET TIMEOUT (ms)

100

50

0

0204060–40 100 120

–20

TEMPERATURE (°C)

Figure 10. Power-up Reset Timeout vs. Temperature

3.0

80

140

02657-A-010

1.0

0.5

0

–0.5

–1.0

TEMPERATURE ERROR (°C)

–1.5

–2.0

0

10 20 30 40 50 60 70 80 90 100 110 120

TEMPERATURE (°C)

Figure 13. Remote Sensor Temperature Error

120

02657-A-013

2.5

2.0

1.5

(mA)

DD

I

1.0

0.5

0

3.00 4.003.25 3.50 3.75 4.25 4.50 4.75 5.255.00
VCC(V)

Figure 11. Supply Current vs. Supply Voltage

1.8

1.6

1.4

1.2

1.0

0.8

0.6

TEMPERATURE ERROR (°C)

0.4

0.2

0

10 20 30 40 50 60 70 80 90 100 110 120

0

TEMPERATURE (°C)

Figure 12. Local Sensor Temperature Error

5.50

100

80

60

40

TEMPERATURE (°C)

20

0

02657-A-011

42

068101214161820222426

TIME (s)

02657-A-014

Figure 14. Response to Thermal Shock

3.5

3.0

2.5

2.0

1.5

MEASUREMENT

BAT

V

1.0

0.5

0

01234

02657-A-012

Figure 15. V

V

VOLTAGE

BAT

Measurement vs. Voltage

BAT

02657-A-015

Rev. A | Page 9 of 56

ADM1026

PRODUCT DESCRIPTION

The ADM1026 is a complete system hardware monitor for
microprocessor-based systems, providing measurement and
limit comparison of various system parameters. The ADM1026
has up to 19 analog measurement channels. Fifteen analog
voltage inputs are provided, five of which are dedicated to
monitoring +3.3 V, +5 V, and ±12 V power supplies, and the
processor core voltage. The ADM1026 can monitor two other
power supply voltages by measuring its own V
system supply. One input (two pins) is dedicated to a remote
temperature-sensing diode. Two additional pins can be
configured as general-purpose analog inputs to measure
0 V to 2.5 V, or as a second temperature sensing input. The eight
remaining inputs are general-purpose analog inputs with a
range of 0 V to 2.5 V or 0 V to 3 V. The ADM1026 also has an
on-chip temperature sensor.

The ADM1026 has eight pins that can be configured for fan
speed measurement or as general-purpose logic I/O pins.
Another eight pins are dedicated to general-purpose logic I/O.
An additional pin can be configured as a general-purpose I/O
or as the bidirectional

Measured values can be read out via a 2-wire serial system
management bus, and values for limit comparisons can be
programmed over the same serial bus. The high speed,
successive approximation ADC allows frequent sampling of all
analog channels to ensure a fast interrupt response to any out­of-limit measurement.

THERM

pin.

FUNCTIONAL DESCRIPTION

The ADM1026 is a complete system hardware monitor for
microprocessor-based systems. The device communicates with
the system via a serial system management bus. The serial bus
controller has a hardwired address line for device selection
(ADD, Pin 15), a s erial data line for reading and writing
addresses and data (SDA, Pin 14), and an input line for the
serial clock (SCL, Pin 13). All control and programming
functions of the ADM1026 are performed over the serial bus.

Measurement Inputs

Programmability of the analog and digital measurement inputs
makes the ADM1026 extremely flexible and versatile. The
device has an 8-bit A/D converter, and 17 analog measurement
input pins that can be configured in different ways.

Pins 25 and 26 are dedicated temperature inputs and may be
connected to the cathode and anode of a remote temperature­sensing diode.

and the main

CC

Pins 29 to 33 are dedicated analog inputs with on-chip
attenuators configured to monitor V
and the processor core voltage V

Pins 34 to 41 are general-purpose analog inputs with a range
of 0 V to 2.5 V or 0 V to 3 V. These are mainly intended for
monitoring SCSI termination voltages, but may be used for
other purposes.

The ADC also accepts input from an on-chip band gap
temperature sensor that monitors system ambient temperature.

In addition, the ADM1026 monitors the supply from which it is
powered, 3.3 V STBY, so there is no need for a separate pin to
monitor the power supply voltage.

The ADM1026 has eight pins that are general-purpose logic
I/O pins (Pins 1, 2, and 43 to 48), a pin that can be configured
as GPIO or as a bidirectional thermal interrupt (

(Pin 42), and eight pins that can be configured for fan speed
measurement or as general-purpose logic pins (Pins 3 to 6 and
Pins 9 to 12).

, +5 V, −12 V, +12 V,

BAT

, respectively.

CCP

THERM

) pin

Sequential Measurement

When the ADM1026 monitoring sequence is started, it cycles
sequentially through the measurement of analog inputs and the
temperature sensor, while at the same time the fan speed inputs
are independently monitored. Measured values from these
inputs are stored in value registers. These can be read over the
serial bus, or can be compared with programmed limits stored
in the limit registers. The results of out-of-limit comparisons are
stored in the interrupt status registers. An out-of-limit event
generates an interrupt on the

Any or all of the interrupt status bits can be masked by
appropriate programming of the interrupt mask registers.

line (Pin 17).

INT

Chassis Intrusion

A chassis intrusion input (Pin 16) is provided to detect
unauthorized tampering with the equipment. This event is
latched in a battery-backed register bit.

Resets

The ADM1026 has two power-on reset outputs,
and

RESETSTBY
STBY fall below the reset threshold. These give a 180 ms reset
pulse at power-up.
RESET input.

, that are asserted when 3.3 V MAIN or 3.3 V

RESETMAIN

also functions as an active-low

RESETMAIN

Pins 27 and 28 may be configured as temperature inputs and
connected to a second temperature-sensing diode, or may be
reconfigured as analog inputs with a range of 0 V to 2.5 V.

Rev. A | Page 10 of 56

ADM1026

Fan Speed Control Outputs

The ADM1026 has two outputs intended to control fan speed,
though they can also be used for other purposes. Pin 18 is an
open drain, pulse width modulated (PWM) output with a
programmable duty cycle and an output frequency of 75 Hz.
Pin 23 is connected to the output of an on-chip, 8-bit, digital-to­analog converter with an output range of 0 V to 2.5 V.

Either or both of these outputs may be used to implement a
temperature-controlled fan by controlling the speed of a fan
using the temperature measured by the on-chip temperature
sensor or remote temperature sensors.

INTERNAL REGISTERS

Table 4 describes the principal registers of the ADM1026. For
more detailed information, see Table 11 to Table 124.

Tabl e 4 . Prin c ip a l Re g ist e r s

Type Description

Address Pointer

Configuration
Registers

Fan Divisor
Registers

DAC/PWM
Control Registers

GPIO Configuration
Registers

Value and Limit
Registers

Status Registers

Mask Registers

Contains the address that selects one of
the other internal registers. When writing
to the ADM1026, the first byte of data is
always a register address, and is written
to the address pointer register.

Provide control and configuration for
various operating parameters.

Contain counter prescaler values for fan
speed measurement.

Contain speed values for PWM and DAC
fan drive outputs.

Configure the GPIO pins as input or
output and for signal polarity.

Store the results of analog voltage inputs,
temperature, and fan speed
measurements, along with their limit
values.

Store events from the various interrupt
sources.

Allow masking of individual interrupt
sources.

• Writing to the EEPROM should be restricted because its

typical cycle life is 100,000 write operations, due to the
usual EEPROM wear-out mechanisms.

The EEPROM in the ADM1026 has been qualified for two key
EEPROM memory characteristics: memory cycling endurance
and memory data retention.

Endurance qualifies the ability of the EEPROM to be cycled
through many program, read, and erase cycles. In real terms,
a single endurance cycle is composed of four independent,
sequential events, as follows:

1. Initial page erase sequence

2. Read/verify sequence

3. Program sequence

4. Second read/verify sequence

In reliability qualification, every byte is cycled from 00h to FFh
until a first fail is recorded, signifying the endurance limit of the
EEPROM memory.

Retention quantifies the ability of the memory to retain its
programmed data over time. The EEPROM in the ADM1026
has been qualified in accordance with the formal JEDEC
Retention Lifetime Specification (A117) at a specific junction
temperature (T

= 55°C) to guarantee a minimum of 10 years

J

retention time. As part of this qualification procedure, the
EEPROM memory is cycled to its specified endurance limit
described above before data retention is characterized. This
means that the EEPROM memory is guaranteed to retain its
data for its full specified retention lifetime every time the
EEPROM is reprogrammed. Note that retention lifetime based
on an activation energy of 0.6 V derates with T

, as shown in

J

Figure 16.

300

250

200

EEPROM

The ADM1026 has 8 kB of nonvolatile, electrically erasable,
programmable read-only memory (EEPROM) from register
Addresses 8000h to 9FFFh. This may be used for permanent
storage of data that is not lost when the ADM1026 is powered
down, unlike the data in the volatile registers. Although referred
to as read-only memory, the EEPROM can be written to (as well
as read from) via the serial bus in exactly the same way as the
other registers. The main differences between the EEPROM and
other registers are

• An EEPROM location must be blank before it can be

written to. If it contains data, it must first be erased.

• Writing to EEPROM is slower than writing to RAM.

Rev. A | Page 11 of 56

150

100

RETENTION (Years)

50

0

50

60 70 80 90 10040

JUNCTION TEMPERATURE (°C)

Figure 16. Typical EEPROM Memory Retention

110

120

02657-A-016

ADM1026

Serial Bus Interface

Control of the ADM1026 is carried out via the serial system
management bus (SMBus). The ADM1026 is connected to this
bus as a slave device, under the control of a master device.

The ADM1026 has a 7-bit serial bus slave address. When the
device is powered on, it does so with a default serial bus address.
The 5 MSBs of the address are set to 01011, and the 2 LSBs are
determined by the logical states of Pin 15 ADD/NTESTOUT.
This pin is a three-state input that can be grounded, connected

, or left open-circuit to give three different addresses.

to V

CC

Table 5. Address Pin Truth Table

ADD Pin A1 A0

GND 0 0
No Connect 1 0
V

0 1

CC

If ADD is left open-circuit, the default address is 0101110
(5Ch). ADD is sampled only at power-up on the first valid
SMBus transaction, so any changes made while the power is on
(and the address is locked) have no effect.

The facility to make hardwired changes to device addresses
allows the user to avoid conflicts with other devices sharing the
same serial bus, for example if more than one ADM1026 is used
in a system.

General SMBus Timing

Figure 17 and Figure 18 show timing diagrams for general read
and write operations using the SMBus. The SMBus specification
defines specific conditions for different types of read and write
operations, which are discussed later in this section.

1

The general SMBus protocol

1. The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial
data line (SDA) while the serial clock line SCL remains
high. This indicates that a data stream follows. All slave
peripherals connected to the serial bus respond to the start
condition and shift in the next 8 bits, consisting of a 7-bit
slave address (MSB first) and an R/

the direction of the data transfer, that is, whether data is
written to or read from the slave device
(0 = write, 1 = read).

operates as follows:

bit, which determine

W

The peripheral whose address corresponds to the trans­mitted address responds by pulling the data line low during
the low period before the ninth clock pulse, known as the
acknowledge bit, and holding it low during the high period
of this clock pulse. All other devices on the bus remain idle
while the selected device waits for data to be read from or
written to it. If the R/

slave device. If the R/

bit is 0, the master writes to the

W

bit is 1, the master reads from the

W

slave device.

2. Data is sent over the serial bus in sequences of nine clock

pulses, 8 bits of data followed by an acknowledge bit from
the slave device. Data transitions on the data line must
occur during the low period of the clock signal and re­main stable during the high period, because a low-to-high
transition when the clock is high may be interpreted as
a stop signal.

If the operation is a write operation, the first data byte after
the slave address is a command byte. This tells the slave
device what to expect next. It may be an instruction telling
the slave device to expect a block write, or it may simply be
a register address that tells the slave where subsequent data
is to be written.

Because data can flow in only one direction as defined by
the R/

bit, it is not possible to send a command to a slave

W
device during a read operation. Before doing a read oper­ation, it may first be necessary to do a write operation to
tell the slave what type of read operation to expect and/or

the address from which data is to be read.

3. When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls
the data line high during the 10th clock pulse to assert a
stop condition. In read mode, the master
device releases the SDA line during the low period before
the ninth clock pulse, but the slave device does not pull
it low (called No Acknowledge). The master takes the data
line low during the low period before the 10th clock pulse,
then high during the 10th clock pulse to assert a stop
condition.

1

If it is required to perform several read or write operations in succession, the

master can send a repeat start condition instead of a stop condition to begin
a new operation.

Rev. A | Page 12 of 56

ADM1026

191

SCL

9

SDA

START BY

MASTER

SCL

(CONTINUED)

SDA

(CONTINUED)

SCL

SDA

START BY

MASTER

SCL

(CONTINUED)

0

1011

FRAME 1

SLAVE ADDRESS

1

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

A0

A1

R/W

ACK. BY

SLAVE

D7

ACK. BY

SLAVE

D6

D4

D5

FRAME 2

COMMAND CODE

199

D7 D6 D5 D4 D3 D2 D1 D0

D2

D3

D1

FRAME N

DATA BYTE

D0

ACK. BY

Figure 17. General SMBus Write Timing Diagram

191

0

10

1

1

1

FRAME 1

SLAVE ADDRESS

A0

A1

R/W

ACK. BY

SLAVE

D6

D7

D4

D5

FRAME 2

DATA BYTE

199

D2

D3

D1

D0

ACK. BY
MASTER

SLAVE

9

ACK. BY

SLAVE

STOP BY
MASTER

02657-A-017

SDA

(CONTINUED)

D7 D6 D5 D4 D3 D2 D1 D0

FRAME 3

DATA BYTE

ACK. BY

MASTER

Figure 18. General SMBus Read Timing Diagram

SMBus PROTOCOLS FOR RAM AND EEPROM

The ADM1026 contains volatile registers (RAM) and non­volatile EEPROM. RAM occupies Addresses 00h to 6Fh, while
EEPROM occupies Addresses 8000h to 9FFFh.

Data can be written to and read from both RAM and EEPROM
as single data bytes and as block (sequential) read or write
operations of 32 data bytes, the maximum block size allowed by
the SMBus specification.

Data can only be written to unprogrammed EEPROM locations.
To write new data to a programmed location, it is first necessary
to erase it. EEPROM erasure cannot be done at the byte level;
the EEPROM is arranged as 128 pages of 64 bytes, and an entire
page must be erased. Note that of these 128 pages, only 124
pages are available to the user. The last four pages are reserved
for manufacturing purposes and cannot be erased/rewritten.

The EEPROM has three RAM registers associated with it,
EEPROM Registers 1, 2, and 3 at Addresses 06h, 0Ch, and 13h.

D7 D6 D5 D4 D3 D2 D1 D0

STOP BY

MASTER

02657-A-018

FRAME N

DATA BYTE

NO ACK.

EEPROM Registers 1 and 2 are for factory use only. EEPROM
Register 3 sets up the EEPROM operating mode. Setting Bit 0 of
EEPROM Register 3 puts the EEPROM into read mode. Setting
Bit 1 puts it into programming mode. Setting Bit 2 puts it into
erase mode.

Only one of these bits must be set before the EEPROM may be
accessed. Setting no bits or more than one of them causes the
device to respond with No Acknowledge if an EEPROM read,
program, or erase operation is attempted.

It is important to distinguish between SMBus write opera­tions, such as sending an address or command, and EEPROM
programming operations. It is possible to write an EEPROM
address over the SMBus, whatever the state of EEPROM
Register 3. However, EEPROM Register 3 must be correctly set
before a subsequent EEPROM operation can be performed. For
example, when reading from the EEPROM, Bit 0 of EEPROM
Register 3 can be set, even though SMBus write operations are
required to set up the EEPROM address for reading.

Rev. A | Page 13 of 56

ADM1026

Bit 3 of EEPROM Register 3 is used for EEPROM write protec­tion. Setting this bit prevents accidental programming or era­sure of the EEPROM. If an EEPROM write or erase operation
is attempted when this bit is set, the ADM1026 responds with
No Acknowledge. This bit is write-once and can only be cleared
by a power-on reset.

EEPROM Register 3 Bit 7 is used for clock extend. Program­ming an EEPROM byte takes approximately 250 µs, which
would limit the SMBus clock for repeated or block write opera­tions. Because EEPROM block read/write access is slow, it is
recommended that this clock extend bit typically be set to 1.
This allows the ADM1026 to pull SCL low and extend the
clock pulse when it cannot accept any more data.

ADM1026 SMBus Operations

The SMBus specification defines several protocols for different
types of read and write operations. The ones used in the
ADM1026 are discussed below. The following abbreviations are
used in the diagrams:

S Start
W Write
P Stop
A Acknowledge
R Read
A

No Acknowledge

ADM1026 Write Operations

Send Byte

In this operation, the master device sends a single command
byte to a slave device, as follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code.

5. The slave asserts ACK on the SDA.

6. The master asserts a stop condition on the SDA and the

transaction ends.

In the ADM1026, the send byte protocol is used to write a
register address to RAM for a subsequent single-byte read from
the same address or block read or write starting at that address.
This is illustrated in Figure 19.

12 3 4 56

SLAVE

S

ADDRESS

Figure 19. Setting a RAM Address for Subsequent Read

W

If it is required to read data from the RAM immediately after
setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single byte read, block read, or block write operation without
asserting an intermediate stop condition.

RAM

ADDRESS

(00h TO 6Fh)

AAP

02657-A-019

Writ e B yte / Word

In this operation, the master device sends a command byte and
one or two data bytes to the slave device as follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code.

5. The slave asserts an ACK on the SDA.

6. The master sends a data byte.

7. The slave asserts an ACK on the SDA.

8. The master sends a data byte (or may assert stop here.)

9. The slave asserts an ACK on the SDA.

10. The master asserts a stop condition on the SDA to end the

transaction.

In the ADM1026, the write byte/word protocol is used for four
purposes. The ADM1026 knows how to respond by the value of
the command byte and EEPROM Register 3.

The first purpose is to write a single byte of data to RAM. In
this case, the command byte is the RAM address from 00h to
6Fh and the (only) data byte is the actual data. This is illustrated
in Figure 20.

12 3 4 56

SLAVE

S

ADDRESS

WA

Figure 20. Single Byte Write to RAM

RAM

ADDRESS

(00h TO 6Fh)

A

DATA

78

AP

02657-A-020

The protocol is also used to set up a 2-byte EEPROM address
for a subsequent read or block read. In this case, the command
byte is the high byte of the EEPROM address from 80h to 9Fh.
The (only) data byte is the low byte of the EEPROM address.
This is illustrated in Figure 21.

13456

2

EEPROM

W

ADDRESS

A

HIGH BYTE

(80h TO 9Fh)

SLAVE

S

ADDRESS

Figure 21. Setting an EEPROM Address

EEPROM

ADDRESS

A

LOW BYTE

(00h TO FFh)

7

8

A

P

02657-A-021

If it is required to read data from the EEPROM immediately
after setting up the address, the master can assert a repeat start
condition immediately after the final ACK and carry out a
single-byte read or block read operation without asserting an
intermediate stop condition. In this case, Bit 0 of EEPROM
Register 3 should be set.

The third use is to erase a page of EEPROM memory. EEPROM
memory can be written to only if it is previously erased. Before
writing to one or more EEPROM memory locations that are
already programmed, the page or pages containing those
locations must first be erased. EEPROM memory is erased by
writing an EEPROM page address plus an arbitrary byte of data
with Bit 2 of EEPROM Register 3 set to 1.

Rev. A | Page 14 of 56

ADM1026

Because the EEPROM consists of 128 pages of 64 bytes, the
EEPROM page address consists of the EEPROM address high
byte (from 80h to 9Fh) and the two MSBs of the low byte. The
lower six bits of the EEPROM address (low byte only) specify
addresses within a page and are ignored during an erase
operation.

12 3 4 5 6

SLAVE

S

ADDRESS

WA

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

EEPROM

ADDRESS

A

LOW BYTE

(00h TO FFh)

Figure 22. EEPROM Page Erasure

78

ARBITRARY

A

DATA

9

10

AY

02657-A-022

Page erasure takes approximately 20 ms. If the EEPROM is
accessed before erasure is complete, the ADM1026 responds
with No Acknowledge.

Last, this protocol is used to write a single byte of data to
EEPROM. In this case, the command byte is the high byte of the
EEPROM address from 80h to 9Fh. The first data byte is the low
byte of the EEPROM address, and the second data byte is the
actual data. Bit 1 of EEPROM Register 3 must be set. This is
illustrated in Figure 23.

9. The slave asserts an ACK on the SDA after each data byte.

10. The master sends a packet error checking (PEC ) byte.

11. The ADM1026 checks the PEC byte and issues an ACK if

correct. If incorrect (NACK), the master resends the data
bytes.

12. The master asserts a stop condition on the SDA to end the

transaction.

WA

COMMAND
A0h BLOCK

WRITE

BYTE

A A DATA 1

COUNT

Figure 24. Block Write to EEPROM or RAM

AA

DATA

32

PEC

APDATA 2 A

SLAVE

S

ADDRESS

When performing a block write to EEPROM, Bit 1 of EEPROM
Register 3 must be set.

Unlike some EEPROM devices that limit block writes to within
a page boundary, there is no limitation on the start address
when performing a block write to EEPROM, except:

• There must be at least 32 locations from the start address

to the highest EEPROM address (9FFF) to avoid writing to
invalid addresses.

02857-A-024

12 3 4 5 6

SLAVE

S

ADDRESS

WA

EEPROM

ADDRESS

HIGH BYTE

(80h TO 9Fh)

EEPROM

ADDRESS

A

LOW BYTE

(00h TO FFh)

78

DATA

A

910

AY

02657-A-023

Figure 23. Single-Byte Write to EEPROM

Block Write

In this operation, the master device writes a block of data to a
slave device. The start address for a block write must have been
set previously. In the case of the ADM1026, this is done by a
Send Byte operation to set a RAM address or by a write
byte/word operation to set an EEPROM address.

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code that tells the slave

device to expect a block write. The ADM1026 command
code for a block write is A0h (10100000).

5. The slave asserts an ACK on the SDA.

6. The master sends a data byte (20h) that tells the slave

device that 32 data bytes are being sent to it. The master
should always send 32 data bytes to the ADM1026.

7. The slave asserts an ACK on the SDA.

8. The master sends 32 data bytes.

• If the addresses cross a page boundary, both pages must be

erased before programming.

ADM1026 Read Operations

The ADM1026 uses the SMBus read protocols described here.

Receive Byte

In this operation, the master device receives a single byte from a
slave device as follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an ACK on the SDA.

4. The master receives a data byte.

5. The master asserts a NO ACK on the SDA.

6. The master asserts a stop condition on the SDA to end the

transaction.

In the ADM1026, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
byte/word operation. Figure 25 shows this. When reading from
EEPROM, Bit 0 of EEPROM Register 3 must be set.

12 3456

SLAVE

S

ADDRESS

RA

Figure 25. Single-Byte Read from EEPROM or RAM

DATA

A

P

02657-A-025

Rev. A | Page 15 of 56

ADM1026

Block Read

In this operation, the master device reads a block of data from a
slave device. The start address for a block read must have been
set previously. In the case of the ADM1026 this is done by a
send byte operation to set a RAM address, or by a write
byte/word operation to set an EEPROM address. The block read
operation consists of a send byte operation that sends a block
read command to the slave, immediately followed by a repeated
start and a read operation that reads out multiple data bytes as
follows:

1. The master device asserts a start condition on the SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an ACK on the SDA.

4. The master sends a command code that tells the slave

device to expect a block read. The ADM1026 command
code for a block read is A1h (10100001).

5. The slave asserts an ACK on the SDA.

6. The master asserts a repeat start condition on the SDA.

7. The master sends the 7-bit slave address followed by the

read bit (high).

8. The slave asserts an ACK on the SDA.

9. The ADM1026 sends a byte count data byte that tells the

master how many data bytes to expect. The ADM1026
always returns 32 data bytes (20h), the maximum allowed
by the SMBus 1.1 specification.

10. The master asserts an ACK on the SDA.

11. The master receives 32 data bytes.

12. The master asserts an ACK on the SDA after each data byte.

13. The ADM1026 issues a PEC byte to the master. The master

should check the PEC byte and issue another block read if
the PEC byte is incorrect.

14. A NACK is generated after the PEC byte to signal the end

of the read.

15. The master asserts a stop condition on the SDA to end the

transaction.

WA

A DATA 1

COMMAND

A1h BLOCK

READ

A

SLAVE

A S R

ADDRESS

DATA

A

32

PEC

P

A

02657-A-026

SLAVE

S

ADDRESS

BYTE

A

COUNT

Figure 26. Block Read from EEPROM or RAM

When block reading from EEPROM, Bit 0 of EEPROM
Register 3 must be set.

Note that although the ADM1026 supports packet error
checking (PEC), its use is optional. The PEC byte is calculated
using CRC-8. The frame check sequence (FCS) conforms to
CRC-8 by the polynomial:

8

C(x) = x

+ x2 + x1 + 1

Consult the SMBus 1.1 Specification for more information.

MEASUREMENT INPUTS

The ADM1026 has 17 external analog measurement pins that
can be configured to perform various functions. It also meas­ures two supply voltages, 3.3 V MAIN and 3.3 V STBY, and the
internal chip temperature.

Pins 25 and 26 are dedicated to remote temperature measure­ment, while Pins 27 and 28 can be configured as analog inputs
with a range of 0 V to 2.5 V, or as inputs for a second remote
temperature sensor.

Pins 29 to 33 are dedicated to measuring V
+12 V supplies, and the processor core voltage V
remaining analog inputs, Pins 34 to 41, are general-purpose
analog inputs with a range of 0 V to 2.5 V (Pins 34 and 35) or
0 V to 3 V (Pins 36 to 41).

A-to-D Converter (ADC)

These inputs are multiplexed into the on-chip, successive
approximation, analog-to-digital converter. The ADC has a
resolution of 8 bits. The basic input range is 0 V to 2.5 V, which

to A

is the input range of A

IN6

, but five of the inputs have

IN9

built-in attenuators to allow measurement of V
+12 V, and the processor core voltage V
components. To allow the tolerance of these supply voltages, the
ADC produces an output of 3/4 full scale (decimal 192) for the
nominal input voltage, and so has adequate headroom to cope
with over voltages. Table 6 shows the input ranges of the analog
inputs and output codes of the ADC.

When the ADC is running, it samples and converts an analog
or local temperature input every 711 µs (typical value). Each
input is measured 16 times and the measurements are averaged
to reduce noise, so the total conversion time for each input is

11.38 ms.

Measurements on the remote temperature (D1 and D2) inputs
take 2.13 ms. These are also measured 16 times and are
averaged, so the total conversion time for a remote temperature
input is 34.13 ms.

, + 5 V, − 1 2 V,

BAT

The

CCP.

, +5 V, −12 V,

BAT

, without any exter nal

CCP

Rev. A | Page 16 of 56

ADM1026

Table 6. A-to-D Output Code vs. V

+12 VIN –12 VIN +5 VIN

< 0.0625 < -15.928 < 0.026 < 0.0172 NA < 0.012 < 0.012 < 0.010 0 00000000

0.062-0.125

0.125-0.187

0.188-0.250

0.250-0.313

0.313-0.375

0.375-0.438

0.438-0.500

0.500-0.563

4.000-4.063

8.000-8.063

12.000-12.063

15.313-15.375 1.705-1.777 6.38-6.406 4.249-4.267 3.828-3.844 2.871-2.883 2.871-2.883 2.392-2.402 245 11110101

15.375-15.437 1.777-1.850 6.406-6.432 4.267-4.284 3.844-3.860 2.883-2.895 2.883-2.895 2.402-2.412 246 11110110

15.437-15.500 1.850-1.922 6.432-6.458 4.284-4.301 3.860-3.875 2.895-2.906 2.895-2.906 2.412-2.422 247 11110111

15.500-15.563 1.922-1.994 6.458-6.484 4.301-4.319 3.875-3.890 2.906-2.918 2.906-2.918 2.422-2.431 248 11111000

15.562-15.625 1.994-2.066 6.484-6.51 4.319-4.336 3.890-3.906 2.918-2.930 2.918-2.930 2.431-2.441 249 11111001

15.625-15.688 2.066-2.139 6.51-6.536 4.336-4.353 3.906-3.921 2.930-2.941 2.930-2.941 2.441-2.451 250 11111010

15.688-15.750 2.139-2.211 6.536-6.563 4.353-4.371 3.921-3.937 2.941-2.953 2.941-2.953 2.451-2.460 251 11111011

15.750-15.812 2.211-2.283 6.563-6.589 4.371-4.388 3.937-3.953 2.953-2.965 2.953-2.965 2.460-2.470 252 11111100

15.812-15.875 2.283-2.355 6.589-6.615 4.388-4.405 3.953-3.969 2.965-2.977 2.965-2.977 2.470-2.480 253 11111101

15.875-15.938 2.355-2.428 6.615-6.641 4.405-4.423 3.969-3.984 2.977-2.988 2.977-2.988 2.480-2.490 254 11111110
>15.938 >2.428 >6.634 >4.423 >3.984 >2.988 >2.988 >2.490 255 11111111

−15.928-15.855

−15.855-15.783

−15.783-15.711

−15.711-15.639

−15.639-15.566

−15.566-15.494

−15.494-15.422

−15.422-15.349

•

•

•

−11.375-11.303

•

•

•

−6.750−6.678

•

•

•

−2.125-2.053

•

•

•

IN

Input Voltage A-to-D Output

3.3 V MAIN

3.3 V STBY

0.026-0.052 0.017-0.034 NA 0.012-0.023 0.012-0.023 0.010-0.019 1 00000001

0.052-0.078 0.034-0.052 NA 0.023-0.035 0.023-0.035 0.019-0.029 2 00000010

0.078-0.104 0.052-0.069 NA 0.035-0.047 0.035-0.047 0.029-0.039 3 00000011

0.104-0.130 0.069-0.086 NA 0.047-0.058 0.047-0.058 0.039-0.049 4 00000100

0.130-0.156 0.086-0.103 NA 0.058-0.070 0.058-0.070 0.049-0.058 5 00000101

0.156-0.182 0.103-0.120 NA 0.070-0.082 0.070-0.082 0.058-0.068 6 00000110

0.182-0.208 0.120-0.138 NA 0.082-0.094 0.082-0.094 0.068-0.078 7 00000111

0.208-0.234 0.138-0.155 NA 0.094-0.105 0.094-0.105 0.078-0.087 8 00001000

1.667-1.693 1.110-1.127 NA 0.750-0.780 0.750-0.780 0.625-0.635 64

3.333-3.359 2.000-2.016 2.000-2.016 1.500-1.512 1.500-1.512 1.250-1.260 128

5-5.026 3.330-3.347 3.000-3.016 2.250-2.262 2.250-2.262 1.875-1.885 192

1

V

V

BAT

A

CCP

IN (0–5)

A

Decimal Binary

IN (6–9)

(1⁄4 scale)

(1⁄2 scale)

(3⁄4 scale)

01000000

10000000

11000000

1

V

is not accurate for voltages under 1.5 V (see Figure 15).

BAT

Rev. A | Page 17 of 56