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ADM1024 c
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Analog Devices ADM1024 c Datasheet

System Hardware Monitor with
Remote Diode Thermal Sensing
ADM1024
FEATURES Up to 9 Measurement Channels Inputs Programmable to Measure Analog Voltage, Fan
Speed, or External Temperature
External Temperature Measurement with Remote
Diode (2 Channels) On-Chip Temperature Sensor 5 Digital Inputs for VID Bits LDCM Support System Management Bus (SMBus) Chassis Intrusion Detect Interrupt and Overtemperature Outputs Programmable RESET Input Pin Shutdown Mode to Minimize Power Consumption Limit Comparison of All Monitored Values

FUNCTIONAL BLOCK DIAGRAM

V
VID0/IRQ0
VID1/IRQ1
VID2/IRQ2
VID3/IRQ3
VID4/IRQ4
FAN1/AIN1
FAN2/AIN2
+V
CCP1
+2.5VIN/D2+
+5V
+12V
/D2–
V
CCP2
D1+
D1–
V
IN
IN
CC
POWER TO CHIP
BAND GAP
TEMPERATURE
SENSOR
CC
100k⍀
PULL-UPS
VID0–3 AND
FAN DIVISOR
REGISTER
VID4 AND DEVICE ID REGISTER
FAN SPEED
COUNTER
INPUT
ATTENUATORS
AND
ANALOG
MULTIPLEXER
ADM1024
ADDRESS
POINTER
REGISTER
TEMPERATURE
CONFIGURATION
REGISTER
10-BIT ADC
2.5V
BAND GAP
REFERENCE
APPLICATIONS Network Servers and Personal Computers Microprocessor-Based Office Equipment Test Equipment and Measuring Instruments

GENERAL DESCRIPTION

The ADM1024 is a complete system hardware monitor for microprocessor-based systems, providing measurement and limit comparison of various system parameters. Eight measurement inputs are provided; three are dedicated to monitoring 5 V and 12 V power supplies and the processor core voltage. The ADM1024 can monitor a fourth power supply voltage by mea­suring its own V
. One input (two pins) is dedicated to a
CC
remote temperature-sensing diode. Two more pins can be
(continued on Page 7)
V
CC
V
CC
V
CC
NTEST OUT/ADD
SDA
SCL
CI
THERM
INT
IN/AOUT
NTEST
RESET
SERIAL BUS INTERFACE
CHANNEL
MODE
REGISTER
VALUE AND
LIMIT
REGISTERS
LIMIT
COMPARATORS
INTERRUPT
STATUS
REGISTERS
INT MASK
REGISTERS
INTERRUPT
MASKING
CONFIGURATION
REGISTERS
ANALOG
OUTPUT
REGISTER AND
8-BIT DAC
CHASSIS
INTRUSION
CLEAR
REGISTER
100k⍀
100k⍀
100k⍀
GND
REV. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
1, 2
ADM1024–SPECIFICATIONS
(TA = T
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY
Supply Voltage, V Supply Current, I
CC
CC
2.8 3.30 5.5 V
TEMPERATURE-TO-DIGITAL CONVERTER
Internal Sensor Accuracy ± 3 °C0°C ≤ TA ≤ 100°C
Resolution ± 1 °C External Diode Sensor Accuracy ± 5 °C0°C ≤ T
Resolution ± 1 °C Remote Sensor Source Current 80 110 150 µAHigh Level
4 6.5 9 µA Low Level
ANALOG-TO-DIGITAL CONVERTER (INCLUDING MUX AND ATTENUATORS)
Total Unadjusted Error, TUE (12 V TUE (AIN, V
, 2.5 VIN, 5 VIN) ± 3%
CCP
3
)
IN
Differential Nonlinearity, DNL ± 1 LSB Power Supply Sensitivity ± 1 %/V Conversion Time (Analog Input or Int. Temp.) 754.8 856.8 µs0°C ≤ T Conversion Time (External Temperature) Input Resistance (2.5 V, 5 V, 12 V, V
CCP1
4
, V
)80140 200 kΩ
CCP2
Input Resistance (AIN1, AIN2) 5 MΩ
ANALOG OUTPUT
Output Voltage Range 0 2.5 V Total Unadjusted Error, TUE ± 3%I Full-Scale Error ± 1 ±5% Zero-Scale Error 2 LSB No Load Differential Nonlinearity, DNL ± 1 LSB Monotonic by Design Integral Nonlinearity ± 1 LSB Output Source Current 2 mA Output Sink Current 1 mA
FAN RPM-TO-DIGITAL CONVERTER
Accuracy ± 12 % 0°C ≤ TA ≤ 100°C Full-Scale Count 255 FAN1 and FAN2 Nominal Input RPM
5
Internal Clock Frequency 19.8 22.5 25.2 kHz 0°C ≤ TA ≤ 100°C
DIGITAL OUTPUTS NTEST_OUT
Output High Voltage, V Output Low Voltage, V
OPEN-DRAIN DIGITAL OUTPUTS
OH
OL
6
2.4 V I
(INT, THERM, RESET)
Output Low Voltage, V High Level Output Current, I
OL
OH
RESET and CI Pulse Width 20 45 ms
OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)
Output Low Voltage, V High Level Output Current, I
OL
OH
to T
MIN
, VCC = V
MAX
MIN
to V
, unless otherwise noted.)
MAX
1.4 3.5 mA Interface Inactive, ADC Active
1.0 mA ADC Inactive, DAC Active 45 145 µA Shutdown Mode
± 2 °CT
= 25°C
A
≤ 100°C
A
± 3 °C25°C
± 4%
≤ 100°C
A
4
9.6 ms
= 2 mA
L
8800 rpm Divisor = 1, Fan Count = 153 4400 rpm Divisor = 2, Fan Count = 153 2200 rpm Divisor = 3, Fan Count = 153 1100 rpm Divisor = 4, Fan Count = 153
= +3.0 mA, VCC = 2.85 V – 3.60 V
0.4 V I
0.4 V I
0.1 100 µAV
0.4 V I
0.1 100 µAV
OUT
= –3.0 mA, VCC = 2.85 V – 3.60 V
OUT
= –3.0 mA, VCC = 3.60 V
OUT
= V
OUT
OUT
OUT
CC
= –3.0 mA, VCC = 2.85 V – 3.60 V
= V
CC
REV. C–2–
ADM1024
Parameter Min Typ Max Unit Test Conditions/Comments
SERIAL BUS DIGITAL INPUTS (SCL, SDA)
Input High Voltage, V Input Low Voltage, V
IH
IL
Hysteresis 500 mV Glitch Immunity 100 ns
DIGITAL INPUT LOGIC LEVELS
7
(ADD, CI, RESET, VID0–VID4, FAN1, FAN2)
Input High Voltage, V Input Low Voltage, V
IH
IL
NTEST_IN
Input High Voltage, V
IH
DIGITAL INPUT CURRENT
Input High Current, I Input Low Current, I Input Capacitance, C
SERIAL BUS TIMING
Clock Frequency, f Glitch Immunity, t Bus Free Time, t Start Setup Time, t Start Hold Time, t SCL Low Time, t SCL High Time, t SCL, SDA Rise Time, t SCL, SDA Fall Time, t Data Setup Time, t Data Hold Time, t
NOTES
1
All voltages are measured with respect to GND, unless otherwise specified.
2
Typicals are at TA = 25°C and represent most likely parametric norm. Shutdown current typ is measured with VCC = 3.3 V.
3
TUE (Total Unadjusted Error) includes Offset, Gain, and Linearity errors of the ADC, multiplexer, and on-chip input attenuators, including an external series input protection resistor value between 0 kΩ and 1 kΩ.
4
Total monitoring cycle time is nominally m × 755 µs + n × 33244 µs, where m is the number of channels configured as analog inputs, plus 2 for the internal V measurement and internal temperature sensor, and n is the number of channels configured as external temperature channels (D1 and D2).
5
The total fan count is based on two pulses per revolution of the fan tachometer output.
6
Open-drain digital outputs may have an external pull-up resistor connected to a voltage lower or higher than VCC (up to 6.5 V absolute maximum).
7
All logic inputs except ADD are tolerant of 5 V logic levels, even if VCC is less than 5 V. ADD is a three-state input that may be connected to VCC, GND, or left open-circuit.
8
Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.2 V for a rising edge.
Specifications subject to change without notice.
IH
IL
IN
8
SCLK
SW
BUF
SU; STA
HD; STA
LOW
HIGH
r
f
SU; DAT
HD; DAT
2.2 V
0.8 V
2.2 V VCC = 2.85 V – 5.5 V
0.8 V VCC = 2.85 V – 5.5 V
2.2 V VCC = 2.85 V – 5.5 V
–1 µAVIN = V
CC
1 µAVIN = 0
20 pF
400 kHz See Figure 1 50 ns See Figure 1
1.3 µsSee Figure 1 600 ns See Figure 1 600 ns See Figure 1
1.3 µsSee Figure 1
0.6 µsSee Figure 1 300 ns See Figure 1 300 ns See Figure 1
100 ns See Figure 1
900 ns See Figure 1
CC
REV. C
SCL
SDA
t
HIGH
t
F
t
SU:DAT
t
SU:STA
t
HD:STA
t
SU:STO
PSP
t
R
t
LOW
t
t
HD:STA
t
BUF
S
HD:DAT
Figure 1. Diagram for Serial Bus Timing
–3–
ADM1024

ABSOLUTE MAXIMUM RATINGS*

Positive Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . . . 6.5 V
Voltage on 12 V V
Pin . . . . . . . . . . . . . . . . . . . . . . . . . 20 V
IN
Voltage on AOUT, N TEST_OUT ADD,
/D2+ . . . . . . . . . . . . . . . . . . –0.3 V to (VCC + 0.3 V)
2.5 V
IN
Voltage on Any Other Input or Output Pin . . –0.3 V to +6.5 V
Input Current at Any Pin . . . . . . . . . . . . . . . . . . . . . . . ± 5 mA
Package Input Current . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
Maximum Junction Temperature (T
max) . . . . . . . . . . 150°C
J
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature, Soldering
Vapor Phase 60 sec . . . . . . . . . . . . . . . . . . . . . . . . . . 235°C
Infrared 15 sec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200°C
ESD Rating All Pins . . . . . . . . . . . . . . . . . . . . . . . . . . 2000 V
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

THERMAL CHARACTERISTICS

24-Lead, Small Outline Package: ␪JA = 50°C/W, ␪JC = 10°C/W

ORDERING GUIDE

PIN CONFIGURATION

NTEST OUT/ADD VID0/IRQ0
FAN1/AIN1 VID4/IRQ4
FAN2/AIN2 +V
NTEST IN/AOUT D1+
1
2
THERM
SDA VID2/IRQ2
3
4
SCL VID3/IRQ3
5
ADM1024
6
TOP VIEW
(Not to Scale)
7
CI +2.5VIN/D2+
8
GND V
9
V
CC
10
INT
11
12
RESET
24
23
VID1/IRQ1
22
21
20
19
18
17
16
+5V
15
+12V
14
13
D1–
CCP1
CCP2
/D2–
IN
IN
Temperature Package Package
Model Range Description Option
ADM1024ARU 0°C to 100°C 24-Lead TSSOP RU-24 ADM1024ARU-REEL 0°C to 100°C 24-Lead TSSOP RU-24 ADM1024ARU-REEL7 0°C to 100°C 24-Lead TSSOP RU-24 ADM1024ARUZ* 0°C to 100°C 24-Lead TSSOP RU-24 ADM1024ARUZ-REEL* 0°C to 100°C 24-Lead TSSOP RU-24 ADM1024ARUZ-REEL7* 0°C to 100°C 24-Lead TSSOP RU-24 EVAL-ADM1024EB Evaluation Board
*Z = Pb-free part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADM1024 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV. C–4–
ADM1024

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description
1 NTEST_OUT/ADD Digital I/O. Dual function pin. This is a three-state input that controls the two LSBs of the Serial
Bus Address. This pin functions as an output when doing a NAND test.
2 THERM Digital I/O. Dual function pin. This pin functions as an interrupt output for temperature interrupts
only, or as an interrupt input for fan control. It has an on-chip 100 kΩ pull-up resistor. 3 SDA Digital I/O. Serial bus bidirectional data. Open-drain output. 4 SCL Digital Input. Serial bus clock. 5 FAN1/AIN1 Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to V
tachometer input. 6 FAN2/AIN2 Programmable Analog/Digital Input. 0 V to 2.5 V analog input or digital (0 to V
tachometer input. 7CIDigital I/O. An active high input from an external latch that captures a Chassis Intrusion event.
This line can go high without any clamping action, regardless of the powered state of the ADM1024.
The ADM1024 provides an internal open drain on this line, controlled by Bit 6 of Register 40h or
Bit 7 of Register 46h, to provide a minimum 20 ms pulse on this line to reset the external Chassis
Intrusion Latch. 8GND System Ground 9V
CC
Power (2.8 V to 5.5 V). Typically powered from 3.3 V power rail. Bypass with the parallel combi-
nation of 10 µF (electrolytic or tantalum) and 0.1 µF (ceramic) bypass capacitors. 10 INT Digital Output. Interrupt request (open-drain). The output is enabled when Bit 1 of Register 40h is
set to 1. The default state is disabled. It has an on-chip 100 kΩ pull-up resistor. 11 NTEST_IN/AOUT Digital Input/Analog Output. An active-high input that enables NAND Test mode board-level
connectivity testing. Refer to the section on NAND testing. Also functions as a programmable
analog output when NAND Test is not selected. 12 RESET Digital I/O. Master Reset, 5 mA driver (open drain), active low output with a 45 ms minimum
pulse width. Set using Bit 4 in Register 40h. Also acts as reset input when pulled low (e.g., power-
on reset). It has an on-chip 100 kΩ pull-up resistor. 13 D1– Analog Input. Connected to cathode of first external temperature-sensing diode. 14 D1+ Analog Input. Connected to anode of first external temperature-sensing diode. 15 +12 V 16 +5 V 17 V
CCP2
IN
IN
/D2– Programmable Analog Input. Monitors second processor core voltage or cathode of second external
Programmable Analog Input. Monitors 12 V supply.
Analog Input. Monitors 5 V supply.
temperature-sensing diode. 18 +2.5 V
/D2+ Programmable Analog Input. Monitors 2.5 V supply or anode of second external temperature-
IN
sensing diode. 19 +V
CCP1
Analog Input. Monitors first processor core voltage (0 V to 3.6 V). 20 VID4/IRQ4 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID4
Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up
resistor. 21 VID3/IRQ3 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3
Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up
resistor. 22 VID2/IRQ2 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3
Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up
resistor. 23 VID1/IRQ1 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3
Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up
resistor. 24 VID0/IRQ0 Digital Input. Core Voltage ID readouts from the processor. This value is read into the VID0–VID3
Status Register. Can also be reconfigured as an interrupt input. It has an on-chip 100 kΩ pull-up
resistor.
) amplitude fan
CC
) amplitude fan
CC
REV. C
–5–
ADM1024–Typical Performance Characteristics
30
20
–10
–20
–30
TEMPERATURE ERROR – ⴗC
–40
–50
–60
10
0
1 1003.3
LEAKAGE RESISTANCE – M⍀
DXP TO GND
DXP TO VCC (5V)
10 30
TPC 1. Temperature Error vs. PC Board Track Resistance
6
5
4
250mV p-p REMOTE
3
120
100
90
80
70
60
50
READING
40
30
20
10
0
0 11010
20 30 40 50
MEASURED TEMPERATURE
60 70 80 90 100
TPC 4. ADM1024 Reading vs. Pentium® III Tem­perature Measurement
25
20
15
2
1
TEMPERATURE ERROR – ⴗC
0
–1
50 50M500
5k
FREQUENCY – Hz
100mV p-p REMOTE
500k 5M
50k
TPC 2. Temperature Error vs. Power Supply Noise Frequency
25
20
15
10
5
TEMPERATURE ERROR – ⴗC
0
–5
50 50M500
5k 50k 500k 5M
FREQUENCY – Hz
100mV p-p
50mV p-p
25mV p-p
TPC 3. Temperature Error vs. Common-Mode Noise Frequency
10
5
TEMPERATURE ERROR – ⴗC
0
–5
1102.2
3.2 4.7 7
DXP-DXN CAPACITANCE – nF
TPC 5. Temperature Error vs. Capacitance Between D+ and D–
10
9
8
TEMPERATURE ERROR – ⴗC
7
6
5
4
3
2
1
0
50 50M500
5k 50k 500k 5M
10mV SQ. WAVE
100k 25M
FREQUENCY – Hz
TPC 6. Temperature Error vs. Differential-Mode Noise Frequency
REV. C–6–
ADM1024
26.5
26.0
25.5
25.0
24.5
24.0
STANDBY CURRENT – ␮A
23.5
23.0
22.5 –40 –20
VDD = 3.3V
020406080100 120
TEMPERATURE – C
TPC 7. Standby Current vs. Temperature
(continued from Page 1)
configured as inputs to monitor a 2.5 V supply and a second processor core voltage, or as a second temperature-sensing input. The remaining two inputs can be programmed as general­purpose analog inputs or as digital fan-speed measuring inputs. Measured values can be read out via an SMBus serial System Management Bus, and values for limit comparisons can be programmed in over the same serial bus. The high speed succes­sive approximation ADC allows frequent sampling of all analog channels to ensure a fast interrupt response to any out-of-limit measurement.
The ADM1024’s 2.8 V to 5.5 V supply voltage range, low sup­ply current, and SMBus interface make it ideal for a wide range of applications. These include hardware monitoring and protection applications in personal computers, electronic test equipment, and office electronics.

MEASUREMENT INPUTS

Programmability of the measurement inputs makes the ADM1024 extremely flexible and versatile. The device has a 10-bit ADC and nine measurement input pins that can be configured in differ­ent ways.
Pins 5 and 6 can be programmed as general-purpose analog inputs with a range of 0 V to 2.5 V, or as digital inputs to moni­tor the speed of fans with digital tachometer outputs. The fan inputs can be programmed to accommodate fans with different speeds and different numbers of pulses per revolution from their tachometer outputs.
Pins 13 and 14 are dedicated temperature inputs and may be connected to the cathode and anode of an external temperature­sensing diode.
Pins 15, 16, and 19 are dedicated analog inputs with on-chip attenuators, configured to monitor 12 V, 5 V, and the processor core voltage, respectively.
Pins 17 and 18 may be configured as analog inputs with on-chip attenuators to monitor a second processor core voltage and a
2.5 V supply, or they may be configured as a temperature input and connected to a second temperature-sensing diode.
The ADC also accepts input from an on-chip band gap tempera­ture sensor that monitors system-ambient temperature.
Finally, the ADM1024 monitors the supply from which it is powered, so there is no need for a separate 3.3 V analog input if the chip V can be configured for either a 3.3 V or 5 V V
is 3.3 V. The range of this VCC measurement
CC
by Bit 3 of the
CC
Channel Mode Register.

SEQUENTIAL MEASUREMENT

When the ADM1024 monitoring sequence is started, it cycles sequentially through the measurement of analog inputs and the temperature sensor, while at the same time the fan speed inputs are independently monitored. Measured values from these inputs are stored in Value Registers. These can be read out over the serial bus, or can be compared with programmed limits stored in the Limit Registers. The results of out-of-limit comparisons are stored in the Interrupt Status Registers, and will generate an interrupt on the INT line (Pin 10).
Any or all of the Interrupt Status Bits can be masked by appro­priate programming of the Interrupt Mask Register.

PROCESSOR VOLTAGE ID

Five digital inputs (VID4 to VID0—Pins 20 to 24) read the processor voltage ID code. These inputs can also be reconfigured as interrupt inputs.
The VID pins have internal 100 kΩ pull-up resistors.

CHASSIS INTRUSION

A chassis intrusion input (Pin 7) is provided to detect unautho­rized tampering with the equipment.

RESET

A RESET input/output (Pin 12) is provided. Pulling this pin low will reset all ADM1024 internal registers to default values. The ADM1024 can also be programmed to give a low going 45 ms reset pulse at this pin.
The RESET pin has an internal, 100 kΩ pull-up resistor.

ANALOG OUTPUT

The ADM1024 contains an on-chip, 8-bit DAC with an out­put range of 0 V to 2.5 V (Pin 11). This is typically used to implement a temperature-controlled fan by controlling the speed of a fan dependent upon the temperature measured by the on-chip temperature sensor.
Testing of board level connectivity is simplified by providing a NAND tree test function. The AOUT (Pin 11) also doubles as a NAND test input, while Pin 1 doubles as a NAND tree output.

INTERNAL REGISTERS OF THE ADM1024

A brief description of the ADM1024’s principal internal regis­ters follows. More detailed information on the function of each register is given in Tables VI to XIX.
Configuration Registers: Provide control and configuration.

Channel Mode Register: Stores the data for the operating

modes of the input channels.

Address Pointer Register: This register contains the address that selects one of the other internal registers. When writing to the ADM1024, the first byte of data is always a register address, which is written to the Address Pointer Register.

REV. C
–7–
ADM1024
Interrupt (INT) Status Registers: Two registers to provide status of each interrupt event. These registers are also mirrored at addresses 4Ch and 4Dh.
Interrupt (INT) Mask Registers: Allow masking of individual interrupt sources.
Temperature Configuration Register: The configuration of the temperature interrupt is controlled by the lower three bits of this register.

VID/Fan Divisor Register: The status of the VID0 to VID4 pins of the processor can be written to and read from these registers. Divisor values for fan speed measurement are also stored in this register.

Value and Limit Registers: The results of analog voltage inputs, temperature, and fan speed measurements are stored in these registers, along with their limit values.

Analog Output Register: The code controlling the analog output DAC is stored in this register.

Chassis Intrusion Clear Register: A signal latched on the chassis intrusion pin can be cleared by writing to this register.

SERIAL BUS INTERFACE

Control of the ADM1024 is carried out via the serial bus. The ADM1024 is connected to this bus as a slave device, under the control of a master device, e.g., ICH.
The ADM1024 has a 7-bit serial bus address. When the device is powered up, it will do so with a default serial bus address. The 5 MSBs of the address are set to 01011, and the 2 LSBs are determined by the logical states of Pin 1 (NTEST OUT/ADD). This is a three-state input that can be grounded, connected to V
, or left open-circuit to give three different addresses.
CC
Table I. ADD Pin Truth Table
ADD Pin A1 A0
GND 1 0 No Connect 0 0 V
CC
If ADD is left open-circuit, the default address will be 0101100. ADD is sampled only at power-up, so any changes made while power is on will have no immediate effect.
The facility to make hardwired changes to A1 and A0 allows the user to avoid conflicts with other devices sharing the same serial bus, for example, if more than one ADM1024 is used in a system.
01
The serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START condition, defined as a high-to-low transition on the serial data line SDA while the serial clock line, SCL, remains high. This indicates that an address/data stream will follow. All slave peripherals connected to the serial bus respond to the START condition, and shift in the next eight bits, consisting of a 7-bit address (MSB first) plus an R/W bit, which deter­mines the direction of the data transfer, i.e., whether data will be written to or read from the slave device.
The peripheral whose address corresponds to the transmitted address responds by pulling the data line low during the low period before the ninth clock pulse, known as the Acknowl­edge Bit. All other devices on the bus now remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is a 0, the master will write to the slave device. If the R/W bit is a 1, the master will read from the slave device.
2. Data is sent over the serial bus in sequences of nine clock pulses, eight bits of data followed by an Acknowledge Bit from the slave device. Transitions on the data line must occur during the low period of the clock signal and remain stable during the high period, as a low-to-high transition when the clock is high may be interpreted as a STOP signal. The number of data bytes that can be transmitted over the serial bus in a single Read or Write operation is limited only by what the master and slave devices can handle.
3. When all data bytes have been read or written, stop condi­tions are established. In Write mode, the master will pull the data line high during the tenth clock pulse to assert a STOP condition. In Read mode, the master device will override the Acknowledge Bit by pulling the data line high during the low period before the ninth clock pulse. This is known as No Acknowledge. The master will then take the data line low during the low period before the tenth clock pulse, then high during the tenth clock pulse to assert a STOP condition.
Any number of bytes of data may be transferred over the serial bus in one operation, but it is not possible to mix read and write in one operation because the type of operation is determined at the beginning and cannot subsequently be changed without starting a new operation.
In the case of the ADM1024, write operations contain either one or two bytes, and read operations contain one byte and perform the following functions.
To write data to one of the device data registers or read data from it, the Address Pointer Register must be set so that the correct data register is addressed, then data can be written into that register or read from it. The first byte of a write operation always contains an address that is stored in the Address Pointer Register. If data is to be written to the device, the write opera­tion contains a second data byte that is written to the register
REV. C–8–
ADM1024
selected by the Address Pointer Register. This is illustrated in Figure 2a. The device address is sent over the bus followed by R/W set to 0. This is followed by two data bytes. The first data byte is the address of the internal data register to be written to, which is stored in the Address Pointer Register. The second data byte is the data to be written to the internal data register.
When reading data from a register, there are two possibilities:
1. If the ADM1024’s Address Pointer Register value is unknown or not the desired value, it is first necessary to set it to the correct value before data can be read from the desired data register. This is done by performing a write to the ADM1024 as before, but only the data byte containing the register ad­dress is sent, as data is not to be written to the register. This is shown in Figure 2b.
A read operation is then performed consisting of the serial bus address, R/W bit set to 1, followed by the data byte read from the data register. This is shown in Figure 2c.
2. If the Address Pointer Register is known to be already at the desired address, data can be read from the corresponding data register without first writing to the Address Pointer Register, so Figure 2b can be omitted.
NOTES
1. Although it is possible to read a data byte from a data regis­ter without first writing to the Address Pointer Register, if the Address Pointer Register is already at the correct value, it is not possible to write data to a register without writing to the Address Pointer Register because the first data byte of a write is always written to the Address Pointer Register.
2. In Figures 2a to 2c, the serial bus address is shown as the default value 01011(A1)(A0), where A1 and A0 are set by the three-state ADD pin.

MEASUREMENT INPUTS

The ADM1024 has nine external measurement pins that can be configured to perform various functions by programming the Channel Mode Register.
Pins 13 and 14 are dedicated to temperature measurement, while Pins 15, 16, and 19 are dedicated analog input channels. Their function is unaffected by the Channel Mode Register.
Pins 5 and 6 can be individually programmed as analog inputs, or as digital fan speed measurement inputs, by programming Bits 0 and 1 of the Channel Mode Register.
Pins 17 and 18 can be configured as analog inputs or as inputs for external temperature-sensing diodes by programming Bit 2 of the Channel Mode Register.
Bit 3 of the Channel Mode Register configures the internal V measurement range for either 3.3 V or 5 V.
Bits 4 to 6 of the Channel Mode Register enable or disable Pins 22 to 24 when they are configured as interrupt inputs by setting Bit 7 of the Channel Mode Register. This function is controlled for Pins 20 and 21 by Bits 6 and 7 of Configuration Register 2.
Bit 7 of the Channel Mode Register allows the processor core voltage ID bits (VID0 to VID4, Pins 24 to 20) to be reconfigured as interrupt inputs.
A truth table for the Channel Mode Register is given in Table II.
CC
REV. C
–9–
ADM1024
SCL
SDA
START BY
MASTER
191
0
1011
SERIAL BUS ADDRESS BYTE
FRAME 1
SCL (CONTINUED)
SDA (CONTINUED)
A0
A1
R/W
ACK. BY
ADM1024
1
D7 D6 D5
D6
D7
ADDRESS POINTER REGISTER BYTE
D4 D3 D2 D1
D5
FRAME 2
D4 D3 D2 D1
FRAME 3
DATA BYTE
D0
ACK. BY
ADM1024
D0
9
9
ACK. BY
ADM1024
STOP BY
MASTER
Figure 2a. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register
SCL
SDA
START BY
MASTER
191
0
1011A1A0 D7
FRAME 1
SERIAL BUS ADDRESS BYTE
R/W
ACK. BY
ADM1024
D6
D5 D4 D3 D2 D1
ADDRESS POINTER REGISTER BYTE
FRAME 2
D0
9
ACK. BY
ADM1024
STOP BY MASTER
Figure 2b. Writing to the Address Pointer Register Only
SCL
SDA
START BY
MASTER
191
0
0
1
SERIAL BUS ADDRESS BYTE
1
FRAME 1
1
A0
A1
R/W
ACK. BY
ADM1024
D6
D7
D4 D3 D2 D1
D5
FRAME 2
DATA BYTE FROM ADM1024
D0
NO ACK.
BY MASTER
Figure 2c. Reading Data from a Previously Selected Register
9
STOP BY MASTER
REV. C–10–
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