Broadband upconverter/downconverter
Power conversion gain of 1.8 dB
Broadband RF, LO, and IF ports
SSB noise figure (NF) of 9.75 dB
Input IP3: 28.5 dBm
Input P1dB: 13.3 dBm
Typical LO drive: 0 dBm
Single-supply operation: 5 V at 130 mA
Adjustable bias for low power operation
Exposed paddle, 4 mm × 4 mm, 24-lead LFCSP package
APPLICATIONS
Cellular base station receivers
Radio link downconverters
Broadband block conversion
Instrumentation
GENERAL DESCRIPTION
The ADL5801 uses a high linearity, doubly balanced, active
mixer core with integrated LO buffer amplifier to provide high
dynamic range frequency conversion from 10 MHz to 6 GHz.
The mixer benefits from a proprietary linearization architecture
that provides enhanced input IP3 performance when subject to
high input levels. A bias adjust feature allows the input linearity,
SSB noise figure, and dc current to be optimized using a single
control pin. An optional input power detector is provided for
adaptive bias control. The high input linearity allows the device
to be used in demanding cellular applications where in-band
blocking signals may otherwise result in degradation in
dynamic performance. The adaptive bias feature allows the part
to provide high input IP3 performance when presented with
large blocking signals. When blockers are removed, the
ADL5801 can automatically bias down to provide low noise
figure and low power consumption.
10 MHz to 6 GHz, Active Mixer
ADL5801
FUNCTIONAL BLOCK DIAGRAM
GND
GND
LOIP
LOIN
GND
GND
1
ADL5801
2
3
4
5
6
PLO
24
78
NCGND
9101112
GNDVPLOENBL VSET
Figure 1.
The balanced active mixer arrangement provides superb LO-toRF and LO-to-IF leakage, typically better than −40 dBm. The IF
outputs are designed to provide a typical voltage conversion
gain of 7.8 dB when loaded into a 200 load. The broad
frequency range of the open-collector IF outputs allows the
ADL5801 to be applied as an upconverter for various transmit
applications.
The ADL5801 is fabricated using a SiGe high performance IC
process. The device is available in a compact 4 mm × 4 mm,
24-lead LFCSP package and operates over a −40°C to +85°C
temperature range. An evaluation board is also available.
212223
GNDIFON
IFOP
1920
V2I
DET
DETO GND
18
VPRF
17
GND
16
RFIP
RFIN
15
14
GND
VPDT
13
8079-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Changes to RF Detector Section................................................... 28
Changes to RF and LO Ports Section........................................... 30
2/10—Revision 0: Initial Version
Rev. A | Page 2 of 36
ADL5801
SPECIFICATIONS
VS = 5 V, TA = 25C, fRF = 900 MHz, fLO = (fRF − 153 MHz), LO power = 0 dBm, Z
Table 1.
Parameter Test Conditions Min Typ Max Unit
RF INPUT INTERFACE
Return Loss Tunable to >20 dB over a limited bandwidth 12 dB
Input Impedance 50 Ω
RF Frequency Range 10 6000 MHz
OUTPUT INTERFACE
Output Impedance Differential impedance, f = 200 MHz 230 Ω
IF Frequency Range Can be matched externally to 3000 MHz LF 600 MHz
DC Bias Voltage2 Externally generated 4.75 VS 5.25 V
LO INTERFACE
LO Power −10 0 +10 dBm
Return Loss 15 dB
Input Impedance 50 Ω
LO Frequency Range 10 6000 MHz
POWER INTERFACE
Supply Voltage 4.75 5 5.25 V
Quiescent Current Resistor programmable 130 200 mA
Disable Current ENBL pin high 50 mA
Enable Time Time from ENBL pin low to enable 182 ns
Disable Time Time from ENBL pin high to disable 28 ns
DYNAMIC PERFORMANCE at fRF = 900 MHz/1900 MHz3
Power Conversion Gain4 f
= 900 MHz 1.8 dB
RF
fRF = 1900 MHz 1.8 dB
Voltage Conversion Gain5 f
= 900 MHz 7.8 dB
RF
fRF = 1900 MHz 7.8 dB
SSB Noise Figure f
SSB Noise Figure Under Blocking
6
Input Third-Order Intercept7 f
Input Second-Order Intercept8 f
= 900 MHz, VSET = 2.0 V 9.75 dB
CENT
f
= 1900 MHz, VSET = 2.0 V 11.5 dB
CENT
f
= 900 MHz 19.5 dB
CENT
f
= 1900 MHz 20 dB
CENT
= 900 MHz 28.5 dBm
CENT
f
= 1900 MHz 26.4 dBm
CENT
= 900 MHz 63 dBm
CENT
f
= 1900 MHz 49.7 dBm
CENT
Input 1 dB Compression Point fRF = 900 MHz 13.3 dBm
f
Power Conversion Gain11 −0.1 dB
Voltage Conversion Gain5 −6.1 dB
SSB Noise Figure f
Input Third-Order Intercept12 f
Input Second-Order Intercept13 f
Input 1 dB Compression Point f
Power Conversion Gain15 −0.44 dB
Voltage Conversion Gain5 −6.44 dB
SSB Noise Figure f
Input Third-Order Intercept7 f
Input Second-Order Intercept8 f
Input 1 dB Compression Point 12.5 dBm
LO-to-IF Output Leakage Unfiltered IF output −30.2 dBm
LO-to-RF Input Leakage −29.4 dBm
RF-to-IF Output Isolation −29.7 dBc
IF/2 Spurious9 0 dBm input power, fRF = 3800 MHz −47.1 dBc
IF/3 Spurious9 0 dBm input power, fRF = 3800 MHz −57.8 dBc
DYNAMIC PERFORMANCE at fRF = 5500 MHz16
Power Conversion Gain17 0.8 dB
Voltage Conversion Gain5 −5.2 dB
SSB Noise Figure f
Input Third-Order Intercept7 f
Input Second-Order Intercept 8 f
Input 1 dB Compression Point 11.3 dBm
LO-to-IF Output Leakage Unfiltered IF output −42.6 dBm
LO-to-RF Input Leakage −28.9 dBm
RF-to-IF Output Isolation −46.7 dBc
IF/2 Spurious9 0 dBm input power, fRF = 5800 MHz −44 dBc
IF/3 Spurious9 0 dBm input power, fRF = 5800 MHz −47 dBc
DYNAMIC PERFORMANCE at fIF = 900 MHz18
Power Conversion Gain19 0 dB
Voltage Conversion Gain5 −6 dB
SSB Noise Figure fIF = 900 MHz, fRF = 250 MHz, VSET = 2.0 V 10.6 dB
Output Third-Order Intercept20 f
Output Second-Order Intercept 21 f
Output 1 dB Compression Point 11.1 dBm
LO-to-IF Output Leakage Unfiltered IF output −33.8 dBm
LO-to-RF Input Leakage −33.4 dBm
IF/2 Spurious9
IF/3 Spurious9
DYNAMIC PERFORMANCE at fIF = 2140 MHz22
Power Conversion Gain23 −1.25 dB
Voltage Conversion Gain5 −7.25 dB
SSB Noise Figure fIF = 2140 MHz, fRF = 190 MHz, VSET = 2.0 V 13.6 dB
Output Third-Order Intercept24 f
Output Second-Order Intercept25 f
Output 1 dB Compression Point 9.9 dBm
LO-to-IF Output Leakage Unfiltered IF output −23.8 dBm
LO-to-RF Input Leakage −33.2 dBm
IF/2 Spurious9
= 3500 MHz, VSET = 3.6 V 15.8 dB
CENT
= 3500 MHz, VSET = 3.6 V 26.5 dBm
CENT
= 3500 MHz, VSET = 3.6 V 42.3 dBm
CENT
= 5500 MHz, VSET = 3.6 V 16.2 dB
CENT
= 5500 MHz, VSET = 3.6 V 22.7 dBm
CENT
= 5500 MHz, VSET = 3.6 V 35.4 dBm
CENT
= 153 MHz, VSET = 3.6 V 30.6 dBm
CENT
= 153 MHz, VSET = 3.6 V 68.7 dBm
CENT
0 dBm input power, f
f
= 806 MHz
IF
0 dBm input power, f
= 806 MHz
f
IF
= 170 MHz, VSET = 3.6 V 24 dBm
CENT
= 170 MHz, VSET = 3.6 V 70 dBm
CENT
0 dBm input power, f
= 2210 MHz
f
IF
= 140 MHz,
RF
= 140 MHz,
RF
= 140 MHz,
RF
−62.6 dBc
−68.9 dBc
−51.5 dBc
Rev. A | Page 4 of 36
ADL5801
1
Z0 is the characteristic impedance assumed for all measurements and the PCB.
2
Supply voltage must be applied from an external circuit through choke inductors
3
VS = 5 V, TA = 25°C, fRF = 900 MHz/1900 MHz, fLO = (f
4
Excluding 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-13M+), and PCB loss.
5
Z
= 50 Ω, differential; Z
SOURCE
6
fRF = f
, f
BLOCKER
− 1) MHz, f
CENT
) MHz, f
CENT
− 1) MHz, f
CENT
) MHz, f
CENT
− 1) MHz, f
CENT
) MHz, f
CENT
− 1) MHz, f
CENT
) MHz, f
CENT
= (f
CENT
RF2
= (f
RF2
= (f
RF2
= (f
RF2
= (f
RF2
CENT
7
f
= (f
RF1
8
f
= (f
RF1
9
For details, see the Spur Per section. formance
10
VS = 5 V, TA = 25°C, fRF = 2500 MHz, fLO = (fRF – 211 MHz), LO power = 0 dBm, Z
11
Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (TC1-1-43M+ and TC1-1-13M+ respectively), and PCB loss.
12
f
= (f
RF1
13
f
= (f
RF1
14
VS = 5 V, TA = 25°C, fRF = 3500 MHz, fLO = (fRF – 153 MHz), LO power = 0 dBm, Z
15
Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (3600BL14M050), and PCB loss.
16
VS = 5 V, TA = 25°C, fRF = 5500 MHz, fLO = (fRF – 153 MHz), LO power = 0 dBm, Z
17
Including 4:1 IF port transformer (TC4-1W+), RF and LO port transformers (5400BL14B050), and PCB loss.
18
VS = 5 V, TA = 25°C, fRF = 153 MHz, fLO = (fRF + 900 MHz), LO power = 0 dBm, Z
19
Including 4:1 IF port transformer (TC4-14+), RF and LO transformers (TC1-1-13M+), and PCB loss.
20
f
= (f
RF1
21
f
= (f
RF1
22
VS = 5 V, TA = 25°C, fRF = 153MHz, fLO = (fRF + 2140 MHz), LO power = 0 dBm, Z
23
Including 4:1 IF port transformer (1850BL15B200), RF and LO port transformers (TC1-1-13M+), and PCB loss.
24
f
= (f
RF1
25
f
= (f
RF1
= 200 Ω differential; Z
LOAD
− 5) MHz, fLO = (f
= (f
) MHz, fLO = (f
CENT
+ 100) MHz, fLO = (f
CENT
= (f
) MHz, fLO = (f
RF2
CENT
+ 100) MHz, fLO = (f
CENT
= (f
) MHz, fLO = (f
RF2
CENT
+ 100) MHz, fLO = (f
CENT
= (f
) MHz, fLO = (f
RF2
CENT
+ 100) MHz, fLO = (f
CENT
CENT
– 153 MHz), LO power = 0 dBm, Z
RF
is the impedance of the source instrument; Z
− 153) MHz, blocker level = 0 dBm.
CENT
SOURCE
– 153) MHz, each RF tone at −10 dBm.
– 153) MHz, each RF tone at −10 dBm.
CENT
– 211) MHz, each RF tone at −10 dBm.
CENT
– 211) MHz, each RF tone at −10 dBm
CENT
0
+ 900 MHz), each RF tone at −10 dBm.
CENT
+ 900) MHz, each RF tone at −10 dBm.
CENT
+ 2140 MHz), each RF tone at −10 dBm.
CENT
+ 2140) MHz, each RF tone at −10 dBm.
CENT
1
0
1
= 50 Ω, VSET = 3.8 V, unless otherwise noted.
0
is the load impedance at the output.
LOAD
1
= 50 Ω, VSET = 3.8 V, unless otherwise noted.
0
1
= 50 Ω, VSET = 3.6 V, unless otherwise noted.
0
1
= 50 Ω, VSET = 3.6 V, unless otherwise noted.
0
= 50 Ω, VSET = 3.6 V, unless otherwise noted.
1
= 50 Ω, VSET = 4 V, unless otherwise noted.
Rev. A | Page 5 of 36
ADL5801
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage, VPOS 5.5 V
VSET, ENBL 5.5 V
IFOP, IFON 5.5 V
RFIN Power 20 dBm
Internal Power Dissipation 1.2 W
θJA (Exposed Paddle Soldered Down)1 26.5°C/W
θJC (at Exposed Paddle) 8.7°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
1
As measured on the evaluation board. For details, see the Evaluation Board
section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 36
ADL5801
O
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
IFOP
GND
NC
IFON
GND
VPL
20
19
22
21
23
24
PIN 1
INDICATOR
1GND
2GND
ADL5801
3LOIP
TOP VIEW
4LOIN
(Not to Scale)
5GND
6GND
9
7
8
L
GND
ENB
VPLO
NOTES
1. THERE IS AN EXPOSED PADDLE THAT
MUST BE SOLDERED TO GROUND.
2. NC = NO CONNECT.
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 5, 6, 8, 12,
GND Device Common (DC Ground).
14, 17, 19, 23
3, 4 LOIP, LOIN Differential LO Input Terminal. Internally matched to 50 Ω. Must be ac-coupled.
7, 24 VPLO Positive Supply Voltage for LO System.
9 ENBL Device Enable. Pull high to disable the device; pull low to enable.
10 VSET
Input IP3 Bias Adjustment. The voltage presented to the VSET pin sets the internal bias of the mixer core
and allows for adaptive control of the input IP3 and NF characteristics of the mixer core.
11 DETO
Detector Output. The DETO pin should be loaded with a capacitor to ground. The developed voltage is
proportional to the rms input level. When the DETO output voltage is connected to the VSET input pin,
the part auto biases and increases input IP3 performance when presented with large signal input levels.
13 VPDT Positive Supply Voltage for Detector.
15, 16 RFIN, RFIP
Differential RF Input Terminal. Internally matched to 50 Ω differential input impedance. Must be
ac-coupled.
18 VPRF Positive Supply Voltage for RF Input System.
20, 21 IFOP, IFON
Differential IF Output Terminal. Bias must be applied through pull-up choke inductors or the center tap
of the IF transformer.
22 NC Not Connected.
EPAD The exposed paddle must be soldered to ground.
18 VPRF
17 GND
16 RFIP
15 RFIN
14 G ND
13 VP DT
11
12
10
GND
VSET
DETO
8079-002
Rev. A | Page 7 of 36
ADL5801
C
TYPICAL PERFORMANCE CHARACTERISTICS
DOWNCOVERTER MODE WITH A BROADBAND BALUN
VS = 5 V, TA = 25°C, VSET = 3.8 V, IF = 153 MHz, as measured using a typical circuit schematic with low-side local oscillator (LO), unless
otherwise noted. Insertion loss of input and output baluns (TC1-1-13M+, TC4-1W+) is extracted from the gain measurement.
6
5
4
3
2
1
GAIN (dB)
0
–1
–2
–3
–4
50010001500200025003000
TA = –40°C
T
= +85°C
A
RF FREQUENCY (MHz)
TA = +25°C
Figure 3. Power Conversion Gain vs. RF Frequency
4.0
3.5
3.0
2.5
2.0
GAIN (dB)
1.5
1.0
0.5
0
050100150200250
900MHz
1900MHz
IF FREQUENCY (MHz)
Figure 4. Power Conversion Gain vs. IF Frequency
3.0
2.5
2.0
1.5
1.0
GAIN (dB)
0.5
0
–0.5
GAIN = 900MHz
GAIN = 1900M Hz
I
= 900MHz
POS
I
= 1900MHz
POS
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
8079-003
08079-004
SUPPLY CURRENT (A)
6
5
4
GAIN = 900MHz
GAIN = 1900MHz
3
INPUT IP 3 = 900MHz
GAIN (dB)
INPUT IP 3 = 1900MHz
2
1
0
–15–1 0–5051015
LO LEVEL (dBm)
Figure 6. Power Conversion Gain and Input IP3 vs. LO Power
100
90
1.700
MEAN = 1.87
SD = 0.03
1.740
1.780
1.820
POWER CONVERSION GAIN (dB)
1.860
1.900
1.940
1.980
80
70
60
Y (%)
50
40
FREQUEN
30
20
10
0
Figure 7. Power Conversion Gain Distribution
3.0
2.5
2.0
1.5
GAIN (dB)
1.0
0.5
TA = –40°C
TA = +25°C
= +85°C
T
A
35
30
25
20
INPUT IP3 (dBm)
15
10
5
2.020
2.060
2.100
08079-007
08079-006
–1.0
2.03.02.53.54.04.55.0
VSET (V)
Figure 5. Power Conversion Gain and Supply Current vs. VSET
0.02
0
4.74.84.95.05.15.25.3
8079-005
SUPPLY (V)
08079-008
Figure 8. Power Conversion Gain vs. Supply Voltage