Fixed gain of 20 dB
Operation up to 6 GHz
Input/output internally matched to 50 Ω
Integrated bias control circuit
Output IP3
46 dBm at 500 MHz
40 dBm at 900 MHz
Output 1 dB compression: 20.6 dB at 900 MHz
Noise figure of 3 dB at 900 MHz
Single 5 V power supply
Small footprint 8-lead LFCSP
Pin compatible with 15 dB gain ADL5541
1 kV ESD (Class 1C)
GENERAL DESCRIPTION
The ADL5542 is a broadband 20 dB linear amplifier that
operates at frequencies up to 6 GHz. The device can be used in
a wide variety of CATV, cellular, and instrumentation equipment.
The ADL5542 provides a gain of 20 dB that is stable over
frequency, temperature, power supply, and from device to
device. The device is internally matched to 50 Ω with an input
return loss of 10 dB or better, up to 6 GHz. Only input/output
ac coupling capacitors, power supply decoupling capacitors, and
an external inductor are required for operation.
RF/IF Gain Block
ADL5542
FUNCTIONAL BLOCK DIAGRAM
RFIN
GND
GND
CB
MATCH
2
3
4
BIAS CONTROL
ADL5542
INPUT
1
The ADL5542 is fabricated on an InGaP HBT process and has
an ESD rating of 1 kV (Class 1C). The device is packaged in a
3 mm × 3 mm LFCSP that uses an exposed paddle for excellent
thermal impedance.
The ADL5542 consumes 93 mA on a single 5 V supply and is
fully specified for operation from −40°C to +85°C.
A fully populated RoHS-compliant evaluation board is
available.
The ADL5541 is a companion part that offers a gain of 15 dB in
a pin-compatible package.
Figure 1.
OUTPUT
MATCH
8
7
6
5
RFOUT
GND
GND
VPOS
06879-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Input Return Loss (S11) Frequency 500 MHz to 5 GHz −15 dB
Output Return Loss (S22) Frequency 500 MHz to 5 GHz −10 dB
Reverse Isolation (S12) −22 dB
FREQUENCY = 100 MHz
Gain 20.2 dB
Output 1 dB Compression Point 19.6 dBm
Output Third-Order Intercept Δf = 1 MHz, output power (P
Noise Figure 2.7 dB
FREQUENCY = 500 MHz
Gain 18.4 19.5 20.8 dB
vs. Frequency ±50 MHz ±0.15 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.1 dB
vs. Supply 4.75 V to 5.25 V ±0.02 dB
Output 1 dB Compression Point 20.6 dBm
Output Third-Order Intercept Δf = 1 MHz, output power (P
Noise Figure 2.8 3.2 dB
FREQUENCY = 900 MHz
Gain 19.2 19.7 20.8 dB
vs. Frequency ±50 MHz ±0.03 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.14 dB
vs. Supply 4.75 V to 5.25 V ±0.02 dB
Output 1 dB Compression Point 20.6 dBm
Output Third-Order Intercept Δf = 1 MHz, output power (P
Noise Figure 3.0 3.3 dB
FREQUENCY = 2000 MHz
Gain 18 18.7 19.4 dB
vs. Frequency ±50 MHz ±0.05 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.23 dB
vs. Supply 4.75 V to 5.25 V ±0.04 dB
Output 1 dB Compression Point 18 dBm
Output Third-Order Intercept Δf = 1 MHz, output power (P
Noise Figure 3.2 3.6 dB
FREQUENCY = 2400 MHz
Gain 17.7 18.3 18.9 dB
vs. Frequency ±50 MHz ±0.05 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.24 dB
vs. Supply 4.75 V to 5.25 V ±0.04 dB
Output 1 dB Compression Point 16.8 dBm
Output Third-Order Intercept Δf = 1 MHz, output power (P
Noise Figure 3.5 3.8 dB
) = 0 dBm per tone 38 dBm
OUT
) = 3 dBm per tone 46 dBm
OUT
) = 0 dBm per tone 40 dBm
OUT
) = 0 dBm per tone 39 dBm
OUT
) = 0 dBm per tone 38 dBm
OUT
Rev. A | Page 3 of 12
ADL5542
Parameter Conditions Min Typ Max Unit
FREQUENCY = 3500 MHz
Gain 15.9 17.5 18.8 dB
vs. Frequency ±50 MHz ±0.04 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.31 dB
vs. Supply 4.75 V to 5.25 V ±0.04 dB
Output 1 dB Compression Point 13.7 dBm
Output Third-Order Intercept Δf = 1 MHz, output power (P
Noise Figure 3.7 4.3 dB
FREQUENCY = 5800 MHz
Gain 11.2 12.7 14.4 dB
vs. Frequency ±50 MHz ±0.03 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±1.2 dB
vs. Supply 4.75 V to 5.25 V ±0.04 dB
Output 1 dB Compression Point 6.8 dBm
Output Third-Order Intercept Δf = 1 MHz, output power (P
Noise Figure 5.7 6.3 dB
POWER INTERFACE Pin VPOS
Supply Voltage (VPOS) 4.5 5 5.5 V
Supply Current 93 115 mA
vs. Temperature −40°C ≤ TA ≤ +85°C ±15 mA
Power Dissipation VPOS = 5 V 0.5 W
) = 0 dBm per tone 33 dBm
OUT
) = 0 dBm per tone 24.2 dBm
OUT
Rev. A | Page 4 of 12
ADL5542
TYPICAL SCATTERING PARAMETERS
VPOS = 5 V and TA = 25°C, the effects of the test fixture have been de-embedded up to the pins of the device.
Supply Voltage, VPOS 6.5 V
Input Power (re: 50 Ω) 10 dBm
Internal Power Dissipation (Paddle Soldered) 650 mW
θ
(Junction to Paddle) 28.5°C/W
JC
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 6 of 12
ADL5542
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
1RFIN
INDICATOR
2GND
ADL5542
3GND
TOP VIEW
(Not to S cale)
4CB
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 RFIN RF Input. Requires a dc blocking capacitor.
2, 3, 6, 7 GND Ground. Connect these pins to a low impedance ground plane.
4 CB Low Frequency Bypass. A 1 μF capacitor should be connected between this pin and ground.
5 VPOS Power Supply for Bias Controller. Connect directly to external power supply.
8 RFOUT
RF Output and Supply Voltage. DC bias is provided to this pin through an inductor that is tied to the
external power supply. RF path requires a dc blocking capacitor.
Exposed Paddle Exposed Paddle. Internally connected to GND. Solder to a low impedance ground plane.
8RFOUT
7GND
6GND
5VPOS
06879-002
Rev. A | Page 7 of 12
ADL5542
TYPICAL PERFORMANCE CHARACTERISTICS
45
40
OIP3 (0dBm)
35
30
25
20
15
10
GAIN, P1dB, OIP3, NF (dB, dBm)
NF
5
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
P1dB
FREQUENCY (GHz )
Figure 3. Gain, P1dB, OIP3, and Noise Figure vs. Frequency
20
19
18
17
16
15
GAIN (dB)
14
13
12
11
10
FREQUENCY (GHz)
Figure 4. Gain vs. Frequency an d Te mperature
+85°C
GAIN
–40°C
+25°C
06879-003
06879-004
5.75.34.94.54.13.73.32.92.52.11.71.30.90.5
50
45
40
35
30
25
20
15
OIP3 AND P1dB (dBm)
10
OIP3 (+85°C)
5
0
OIP3 (+25° C)
OIP3 (–40°C)
P1dB (+85°C)
P1dB (+25°C)
P1dB (–40°C)
FREQUENCY (GHz )
Figure 6. OIP3 and P1dB vs. Frequency and Temperature
50
45
2.4GHz
900MHz
3.5GHz
P
OUT
40
35
30
OIP3 (dBm)
25
20
15
–318
03691215
Figure 7. OIP3 vs. Output Power (P
(dBm)
) and Frequency
OUT
500MHz
2GHz
06879-006
5.75.34.94.54.13.73.32.92.52.11.71.30.90.5
06879-007
0
–5
–10
–15
–20
–25
–30
S11, S22, S12 (d B)
–35
–40
–45
–50
06
12345
S12
FREQUENCY (GHz )
S22
S11
06879-005
Figure 5. Input Return Loss (S11), Output Return Loss (S22), and
8
7
6
5
4
NOISE FIGURE (dB)
3
2
06.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Figure 8. Noise Fi gure vs. Frequency and Temperatu re
Reverse Isolation (S12) vs. Frequency
Rev. A | Page 8 of 12
+85°C
+25°C
–40°C
06879-008
FREQUENCY (GHz )
ADL5542
50
40
30
20
PERCENTAGE (%)
10
0
38.0
39.240.441.6
OIP3 (dBm)
06879-009
Figure 9. OIP3 Distribution at 900 MHz
25
20
15
10
PERCENTAGE (%)
5
0
20.3
20.420.520.620.720.820.9
P1dB (dBm)
06879-010
Figure 10. P1dB Distribution at 900 MHz
40
30
20
PERCENTAGE (%)
10
0
19.5
19.619.719.819.9
GAIN (dB)
Figure 11. Gain Distribution at 900 MHz
40
35
30
25
20
15
PERCENTAGE (%)
10
5
0
2.40
2.52 2.64 2.76 2.88 3.00 3.12 3.24 3.36 3.48
NOISE FI G URE (dB)
Figure 12. Noise Figure Distribution at 900 MHz
06879-011
879-012
06
Rev. A | Page 9 of 12
ADL5542
T
BASIC CONNECTIONS
The basic connections for operating the ADL5542 are shown in
Figure 13. Recommended components are listed in Tabl e 5. The
input and output should be ac-coupled with appropriately sized
capacitors (device characterization was performed with 33 pF
capacitors). A 5 V dc bias is supplied to the amplifier via VPOS
(Pin 5) and through a biasing inductor connected to RFOUT
(Pin 8). The bias voltage should be decoupled using a 1 μF
capacitor, a 1.2 nF capacitor, and two 68 pF capacitors.
VCC
RFINRFOU
C1
33pF
C3
1µF
C6
1µF
C5
1.2nF
ADL5542
1RFIN8RFOUT
2GND7GND
3GND6GND
4CB5VPOS
Figure 13. Basic Connections
For operation between 50 MHz and 500 MHz, a larger biasing
choke and ac coupling capacitors are necessary (see Ta b le 5).
Figure 14 shows a plot of the input return loss, the output
return loss, and the gain with these components. At 100 MHz,
the ADL5542 achieves an OIP3 of 38 dBm (P
tone). The noise figure performance for operation from 50 MHz
to 500 MHz is shown in Figure 15. When operating below
50 MHz, the ADL5542 exhibits gain peaking, and the input
and output match degrade significantly.
21.0
C4
68pF
C7
68pF
L1
47nH
C2
33pF
GND
VCC
= 0 dBm per
OUT
10
4.0
3.5
3.0
2.5
NOISE FI GURE (dB)
2.0
1.5
50500
100 150200 250300 350400 450
FREQUENCY (MHz)
06879-015
Figure 15. Noise Figure vs. Frequency
SOLDERING INFORMATION AND RECOMMENDED
013
06879-
PCB LAND PATTERN
Figure 16 shows the recommended land pattern for the ADL5542.
To minimize thermal impedance, the exposed paddle on the
package underside should be soldered down to a ground plane
along with Pin 2, Pin 3, Pin 6, and Pin 7. If multiple ground
layers exist, they should be stitched together using vias (a
minimum of five vias is recommended). For more information
on land pattern design and layout, refer to Application Note
AN-772, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP).
2.03mm
PIN 1
PIN 8
20.5
S21
20.0
19.5
GAIN (dB)
19.0
18.5
18.0
100 150200 250300 350400 450
50500
S11
S22
FREQUENCY (MHz)
0
–10
–20
–30
–40
–50
1.85mm
PIN 4
RETURN LOSS ( dB)
0.71mm
1.53mm
PIN 5
1.78mm0.5mm
06879-016
Figure 16. Recommended Land Pattern
06879-014
Figure 14. Input Return Loss (S11), Output Return Loss (S22), and
Gain (S21) vs. Frequency
Table 5. Recommended Components for Basic Connections
Figure 19 shows the schematic for the ADL5542 evaluation
board. The board is powered by a single 5 V supply.
The components used on the board are listed in Tab le 6 . Power
can be applied to the board through clip-on leads (VCC and
GND) or through a 2-pin header (W1).
79-0
068 17
Figure 17. Evaluation Board Layout (Bottom)
W1
VCC
C1
RFINRFOUT
33pF
C3
1µF
C5
C6
1.2nFC468pF
1µF
ADL5542
1RFIN8RFOUT
2GND7GND
3GND6GND
4CB5VPOS
DUT1
L1
47nH
C2
33pF
GND
C7
68pFC8OPENC9OPEN
Figure 19. Evaluation Board Schematic
VCC
06879-019
06879-018
Figure 18. Evaluation Board Layout (Top)
Table 6. Evaluation Board Configuration Options
Component Function Default Value
DUT1 Gain block ADL5542
C1, C2 AC coupling capacitors 33 pF, 0402
C3 Low frequency bypass capacitor 1 μF, 0805
C4, C5, C6, C7, C8, C9 Power supply decoupling capacitors C4, C7 = 68 pF, 0603
C5 = 1.2 nF, 0603
C6 = 1 μF, 0805
C8, C9 = open
L1 DC bias inductor 47 nH, 0603 (Coilcraft 0603CS-47NXJL_ or equivalent)
VCC and GND Clip-on terminals for power supply
W1 2-pin header for connection of ground and supply via cable
Rev. A | Page 11 of 12
ADL5542
OUTLINE DIMENSIONS
3.25
3.00 SQ
INDICATOR
0.90 MAX
0.85 NOM
SEATING
PLANE
PIN 1
12° MAX
2.75
TOP
VIEW
0.70 MAX
0.65TYP
0.30
0.23
0.18
2.95
2.75 SQ
2.55
0.05 MAX
0.01 NOM
0.20 REF
0.60 MAX
Figure 20. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
3 mm × 3 mm Body, Very Thin, Dual Lead
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADL5542ACPZ-R7
ADL5542-EVALZ
1
Z = RoHS Compliant Part.
1
−40°C to +85°C 8-Lead LFCSP_VD, Tape and Reel CP-8-2 Q15