Operation from 400 MHz to 4000 MHz
Noise figure of 0.8 dB at 900 MHz
Requires few external components
Integrated active bias control circuit
Integrated dc blocking capacitors
Adjustable bias for low power applications
Single-supply operation from 3 V to 5 V
Gain of 20.8 dB at 900 MHz
OIP3 of 37.0 dBm at 900 MHz
P1dB of 21.8 dBm at 900 MHz
Small footprint LFCSP
Pin-compatible version with 21.5 dB gain available
GENERAL DESCRIPTION
The ADL5521 is a high performance GaAs pHEMT low noise
amplifier. It provides high gain and low noise figure for singledownconversion IF sampling receiver architectures as well as
direct-downconversion receivers.
The ADL5521 provides a high level of integration by incorporating
the active bias and dc blocking capacitors, making it very easy
to use while not sacrificing design flexibility.
Low Noise Amplifier
ADL5521
FUNCTIONAL BLOCK DIAGRAM
ACTIVE
1VBIAS
BIAS
2RFIN
3NC
ADL5521
4NC
NC = NO CONNECT
Figure 1.
The ADL5521 is easy to tune, requiring only a few external
components. The device can support operation from 3 V to 5 V,
and the current draw can be adjusted with the external bias
resistor for applications requiring low power consumption.
The ADL5521 comes in a compact, thermally enhanced, 3 mm ×
3 mm LFCSP and operates over the temperature range of
−40°C to +85°C.
A fully populated evaluation board is also available.
8 VPOS
7RFOUT
6NC
5NC
06828-001
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Updated Maximum Junction Temperature Unit (Table 4) ......... 5
10/08—Revision 0: Initial Version
Rev. A | Page 2 of 24
ADL5521
SPECIFICATIONS
AC SPECIFICATIONS
TA = 25°C, R1 = 1.3 kΩ; parameters include matching circuit, matched for optimal noise, unless otherwise noted.
Table 1.
3 V 5 V
Parameter Conditions Min Typ Max Min Typ Max Unit
FREQUENCY = 900 MHz
Gain (S21) 20.3 20.8 dB
vs. Frequency ±50 MHz ±0.28 ±0.33 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.53 ±0.46 dB
Noise Figure1 0.8 0.9 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.8 21.8 dBm
Input Return Loss (S11) −8.0 −9.0 dB
Output Return Loss (S22) −14.7 −15.3 dB
Isolation (S12) −23.8 −25.0 dB
FREQUENCY = 1950 MHz
Gain (S21) 15.4 14.7 15.8 17.0 dB
vs. Frequency ±30 MHz ±0.04 ±0.06 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.43 ±0.40 dB
Noise Figure1 1.0 1.0 dB
Output Third-Order Intercept (OIP3) Δf = MHz, P
Output 1 dB Compression Point (P1dB) 17.6 21.8 dBm
Input Return Loss (S11) −10.5 −12.5 dB
Output Return Loss (S22) −25.5 −25.5 dB
Isolation (S12) −20.2 −21.0 dB
FREQUENCY = 2600 MHz
Gain (S21) 12.4 12.8 dB
vs. Frequency ±100 MHz ±0.35 ±0.35 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.46 ±0.45 dB
Noise Figure1 0.9 1.0 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.1 21.5 dBm
Input Return Loss (S11) −7.1 −7.7 dB
Output Return Loss (S22) −14.1 −13.5 dB
Isolation (S12) −20.0 −20.5 dB
FREQUENCY = 3500 MHz
Gain (S21) 10.0 10.3 dB
vs. Frequency ±100 MHz ±0.56 ±0.59 dB
vs. Temperature −40°C ≤ TA ≤ +85°C ±0.66 ±0.63 dB
Noise Figure1 1.0 1.1 dB
Output Third-Order Intercept (OIP3) Δf = 1 MHz, P
Output 1 dB Compression Point (P1dB) 17.0 20.9 dBm
Input Return Loss (S11) −18.0 −18.3 dB
Output Return Loss (S22) −10.5 −11.0 dB
Isolation (S12) −17.8 −18.1 dB
1
Noise figure de-embedded to first matching component on input side.
= 0 dBm per tone 28.0 37.0 dBm
OUT
= 0 dBm per tone 29.0 35.0 dBm
OUT
= 0 dBm per tone 30.5 35.5 dBm
OUT
= 0 dBm per tone 31.0 36.0 dBm
OUT
Rev. A | Page 3 of 24
ADL5521
DC SPECIFICATIONS
Table 2.
3 V 5 V
Parameter Conditions
Supply Current 30 60 mA
vs. Temperature −40°C ≤ TA ≤ +85°C ±4 ±7 mA
DE-EMBEDDED S-PARAMETERS, VPOS = 3 V TO 5 V, RFIN = PORT 1, VPOS = PORT 2, RFOUT = PORT 3
Supply Voltage, VPOS 5.5 V
RF Input Level 7 dBm
RF Input Level (with 8 Ω Series Resistor on VPOS) 20 dBm
Internal Power Dissipation 500 mW
θJA (Junction to Air) 50°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. A | Page 5 of 24
ADL5521
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1VBIAS
ADL5521
2RFIN
3NC
4NC
NOTES
1. NC = NO CONNEC T.
2. CONNECT THE EXPOSED PAD TO A LOW
IMPEDANCE GROUND PL ANE .
TOP VIEW
(Not to S cale)
EXPOSED PAD
8 VPOS
7RFOUT
6NC
5NC
06828-002
Figure 2. Pin Configuration
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 VBIAS Internal DC Bias. This pin should be connected to VPOS through the R1 resistor.
2 RFIN RF Input. This is the input to the LNA.
3, 4, 5, 6 NC No Connection. No internal connection.
7 RFOUT RF Output.
8 VPOS
Supply Voltage. DC bias needs to be bypassed to ground using a low inductance capacitor. This pin is
also used for output matching. See the Basic Connections section.
9 (EPAD) Exposed Pad (EPAD) GND. Connect the exposed pad to a low impedance ground plane.
Rev. A | Page 6 of 24
ADL5521
TYPICAL PERFORMANCE CHARACTERISTICS
900 MHz, VPOS = 5 V
Matched for optimal noise figure, external matching circuit included.