Datasheet ADL5519 Datasheet (ANALOG DEVICES)

1 MHz to 10 GHz, 62 dB Dual Log

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FEATURES

Wide bandwidth: 1 MHz to 10 GHz Dual-channel and channel difference output ports Integrated accurate scaled temperature sensor 62 dB dynamic range (±3 dB) >50 dB with ±1 dB up to 8 GHz Stability over temperature: ±0.5 dB (−40 Low noise detector/controller outputs Pulse response time: 6 ns/8 ns (fall time/rise time) Supply operation: 3.3 V to 5.5 V @ 60 mA Fabricated using high speed SiGe process Small footprint, 5 mm × 5 mm, 32-lead LFCSP Operating temperature range: −40

APPLICATIONS

RF transmitter power amplifier linearization and

gain/power control Power monitoring in radio link transmitters Dual-channel wireless infrastructure radios Antenna VSWR monitor RSSI measurement in base stations, WLAN, WiMAX, radar

GENERAL DESCRIPTION

The ADL5519 is a dual-demodulating logarithmic amplifier that incorporates two AD8317s. It can accurately convert an RF input signa

l into a corresponding decibel-scaled output. The ADL5519 provides accurately scaled, independent, logarithmic output voltages for both RF measurement channels. The device has two additional output ports, OUTP and OUTN, that provide the measured differences between the OUTA and OUTB channels. The on-chip channel matching makes the log amp outputs insensitive to temperature and process variations.

The temperature sensor pin provides a scaled voltage that is

portional to the temperature over the operating temperature

pro range of the device.

The ADL5519 maintains accurate log conformance for signals

m 1 MHz to 8 GHz and provides useful operation to 10 GHz.

fro The ±3 dB dynamic range is typically 62 dB and has a ±1 dB dynamic range of >50 dB (re: 50 ). The ADL5519 has a response time of 6 ns/8 ns (fall time/rise time) that enables RF burst detection to a pulse rate of greater than 50 MHz. The device provides unprecedented logarithmic intercept stability vs. ambient

C to +85oC)

C to +125oC

Detector/Controller

ADL5519

FUNCTIONAL BLOCK DIAGRAM

INHA

INLA

COMR

PWDN

COMR

INLB

INHB

COM

24 23 22 21 20 19 18 17

ADL5519

CHANNEL A

LOG DETECTOR

OUTA OUTB

CHANNEL B

LOG DETECTOR

1 2 3 4 5 6 7 8

COMR

VPSA

VPSB

ADJA

TEMP

BIAS

ADJB

Figure 1.

VPSR

VREF

TEMP

VLVL

temperature conditions. A supply of 3.3 V to 5.5 V is required to power the device. Current consumption is typically 60 mA, and it decreases to less than 1 mA when the device is disabled.

The device is capable of supplying four log amp measurements sim

ultaneously. Linear-in-dB measurements are provided at OUTA and OUTB with conveniently scaled slopes of −22 mV/dB. The log amp difference between OUTA and OUTB is available as differential or single-ended signals at OUTP and OUTN. An optional voltage applied to VLVL provides a common-mode reference level to offset OUTP and OUTN above ground. The broadband output pins can support many system solutions.

Any of the ADL5519 output pins can be configured to provide

rol voltage to a variable gain amplifier (VGA). Special

a cont attention has been paid to minimize the broadband noise of the output pins so that they can be used for controller applications.

The ADL5519 is fabricated on a SiGe bipolar IC process and is ava

ilable in a 5 mm × 5 mm, 32-lead LFCSP with an operating temperature range of −40°C to +125°C.

VSTA

CLPA

OUTA

FBKA

OUTP

OUTN

FBKB

OUTB

VSTB

CLPB

06198-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

ADL5519

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Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

General Description......................................................................... 1

Revision History ...............................................................................2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics........................................... 11

Theory of Operation ......................................................................19

Using the ADL5519........................................................................ 20

Basic Connections...................................................................... 20

Input Signal Coupling................................................................ 20

Temperature Sensor Interface................................................... 22

VREF Interface ...........................................................................22

Power-Down Interface............................................................... 22

Setpoint Interface—VSTA, VSTB............................................. 22

Output Interface—OUTA, OUTB............................................22

Difference Output—OUTP, OUTN......................................... 23

Description of Characterization............................................... 23

Basis for Error Calculations...................................................... 23

Device Calibration ..................................................................... 24

Adjusting Accuracy Through Choice of Calibration Points......24

Temperature Compensation Adjustment................................ 25

Altering the Slope....................................................................... 26

Channel Isolation....................................................................... 26

Output Filtering.......................................................................... 27

Package Considerations............................................................. 27

Operation Above 8 GHz............................................................ 27

Applications Information.............................................................. 28

Measurement Mode ................................................................... 28

Controller Mode......................................................................... 28

Automatic Gain Control............................................................ 30

Gain-Stable Transmitter/Receiver............................................ 32

Measuring VSWR....................................................................... 34

Evaluation Board............................................................................ 36

Configuration Options.............................................................. 36

Evaluation Board Schematic and Artwork............................. 37

Outline Dimensions....................................................................... 39

Ordering Guide .......................................................................... 39

REVISION HISTORY

1/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 40

ADL5519

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SPECIFICATIONS

Supply voltage, VP = VPSR = VPSA = VPSB = 5 V, C Table 1.

Parameter Conditions Min Typ Max Unit

SIGNAL INPUT INTERFACE INHA, INHB (Pin 25, Pin 32)

Specified Frequency Range 0.001 10 GHz DC Common-Mode Voltage VP − 0.7 V

MEASUREMENT MODE,

100 MHz OPERATION

ADJA (Pin 21) = 0.65 V, ADJB (Pin 4) = 0.7 V; OUTA, OUTB (Pin 15, Pin 10) shorted to VSTA, VSTB (Pin 17, Pin 8); OUTP, OUTN (Pin 13, Pin 12) shorted to FBKA, FBKB (Pin 14, Pin 11), respectively; sinusoidal input signal; error referred to best-fit line using linear regression

between P Input Impedance 1670||0.47 Ω||pF OUTA, OUTB ± 1 dB Dynamic Range 51 dB

−40°C < TA < +85°C 42 dB OUTA, OUTB Maximum Input Level ±1 dB error −1 dBm OUTA, OUTB Minimum Input Level ±1 dB error −52 dBm OUTA, OUTB, OUTP, OUTN Slope OUTA, OUTB Intercept

−22 mV/dB

22 dBm Output Voltage (High Power In) OUTA, OUTB @ P Output Voltage (Low Power In) OUTA, OUTB @ P OUTP, OUTN Dynamic Gain Range ±1 dB error 50 dB

−40°C < TA < +85°C 44 dB Temperature Sensitivity Deviation from OUTA, OUTB @ 25°C

−40°C < TA < +85°C, P 25°C < TA < 85°C, P

−40°C < TA < +25°C, P Distribution of OUTP, OUTN from 25°C

25°C < T

typical error = −0.09 dB

−40°C < T

typical error = 0.25 dB

25°C < TA < 85°C, P

typical error = 0.05 dB

−40°C < T

typical error = −0.23 dB Input A-to-Input B Isolation 80 dB Input A-to-OUTB Isolation

Input B-to-OUTA Isolation

MEASUREMENT MODE,

900 MHz OPERATION

Frequency separation = 1 kHz, P

INHA

Frequency separation = 1 kHz, P

INHB

ADJA = 0.6 V, ADJB = 0.65 V; OUTA, OUTB shorted to

VSTA, VSTB; OUTP, OUTN shorted to FBKA, FBKB, respectively;

sinusoidal input signal; error referred to best fit line using

linear regression between P Input Impedance 925||0.54 Ω||pF OUTA, OUTB ± 1 dB Dynamic Range 54 dB

−40°C < TA < +85°C 49 dB OUTA, OUTB Maximum Input Level ±1 dB error −2 dBm OUTA, OUTB Minimum Input Level ±1 dB error −56 dBm OUTA, OUTB, OUTP, OUTN Slope OUTA, OUTB Intercept

−22 mV/dB

20.3 dBm Output Voltage (High Power In) OUTA, OUTB @ P Output Voltage (Low Power In) OUTA, OUTB @ P

= 1000 pF, TA = 25°C, 50 Ω termination resistor at INHA, INHB, unless otherwise noted.

LPF

, P

= −40 dBm and −10 dBm

INHB

, P

INHA

= −16 dBm 0.7 V

INHB

, P

= −40 dBm 1.37 V

INHB

, P

INHA

, P

INHA

= −16 dBm, P

INHA

= −40 dBm, P

INHA

= −16 dBm ±0.25 dB

INHB

= −40 dBm +0.16 dB

INHB

, P

= −40 dBm −0.6 dB

INHB

= −30 dBm,

INHB

= −16 dBm, P

= −40 dBm, P

INHB

= −30 dBm, B

INHB

= −50 dBm,

INHA

when OUTB/Slope = 1 dB

= −50 dBm,

INHB

when OUTA/Slope = 1 dB

= −30 dBm,

±0.25 dB

±0.4 dB

±0.25 dB

±0.45 dB

60 dB

– P

INHA

< 85°C, P

< +25°C, P

INHB

INHA

, P

= −40 dBm and −10 dBm B

INHA

INHB

, P

INHA

= −10 dBm 0.67 V

INHB

, P

= −40 dBm 1.34 V

INHB

Rev. 0 | Page 3 of 40

ADL5519

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Parameter Conditions Min Typ Max Unit

OUTP, OUTN Dynamic Gain Range ±1 dB error 55 dB

−40°C < TA < +85°C 48 dB Temperature Sensitivity Deviation from OUTA, OUTB @ 25°C

−40°C < TA < +85°C, P 25°C < TA < 85°C, P

−40°C < TA < +25°C, P

Distribution OUTP, OUTN from 25°C

25°C < T

< 85°C, P

typical error = −0.08 dB

−40°C < TA < +25°C, P typical error = 0.3 dB 25°C < T

< 85°C, P

typical error = 0.17 dB

−40°C < T

< +25°C, P

typical error = −0.19 dB

Input A-to-Input B Isolation 75 dB Input A-to-OUTB Isolation

Input B-to-OUTA Isolation

MEASUREMENT MODE,

1.9 GHz OPERATION

Frequency separation = 1 kHz, P

– P

INHA

when OUTB/Slope = 1 dB

INHB

Frequency separation = 1 kHz, P

– P

INHB

when OUTA/Slope = 1 dB

INHA

ADJA = 0.5 V, ADJB = 0.55 V; OUTA, OUTB shorted to VSTA, VSTB; OUTP, OUTN shorted to FBKA, FBKB, respectively; sinusoidal input signal; error referred to best fit line using linear regression between P

Input Impedance 525||0.36 Ω||pF OUTA, OUTB ± 1 dB Dynamic Range 55 dB

−40°C < TA < +85°C 49 dB

OUTA, OUTB Maximum Input Level ±1 dB error −4 dBm OUTA, OUTB Minimum Input Level ±1 dB error −59 dBm OUTA, OUTB, OUTP, OUTN Slope OUTA, OUTB Intercept

Output Voltage (High Power In) OUTA, OUTB @ P Output Voltage (Low Power In) OUTA, OUTB @ P

−22 mV/dB 18 dBm

INHA

OUTP, OUTN Dynamic Gain Range ±1 dB error 55 dB

−40°C < TA < +85°C 48 dB

Temperature Sensitivity Deviation from OUTA, OUTB @ 25°C

−40°C < TA < +85°C, P 25°C < TA < 85°C, P

−40°C < TA < +25°C, P

Distribution of OUTP, OUTN from 25°C

25°C < T

< 85°C, P

typical error = −0.07 dB

−40°C < T

< +25°C, P

typical error = 0.23 dB

25°C < TA < 85°C, P

typical error = 0.16 dB

−40°C < TA < +25°C, P typical error = −0.22 dB

Input A-to-Input B Isolation 65 dB Input A-to-OUTB Isolation

Input B-to-OUTA Isolation

Frequency separation = 1 kHz, P

– P

INHA

when OUTB/Slope = 1 dB

INHB

Frequency separation = 1 kHz, P

– P

INHB

when OUTA/Slope = 1 dB

INHA

, P

INHA

, P

INHA

= −16 dBm, P

INHA

= −40 dBm, P

INHA

= −16 dBm ±0.25 dB

INHB

= −40 dBm +0.25 dB

INHB

, P

= −40 dBm −0.5 dB

INHB

±0.25 dB

±0.4 dB

±0.25 dB

±0.4 dB

50 dB

= −16 dBm, P

INHB

= −40 dBm, P

INHA

= −50 dBm,

INHB

= −30 dBm,

INHB

= −30 dBm

INHB

= −30 dBm,

INHB

= −50 dBm,

, P

= −40 dBm and −10 dBm B

INHA

INHB

, P

= −10 dBm 0.62 V

INHB

, P

= −40 dBm 1.28 V

INHB

, P

INHA

, P

INHA

= −16 dBm, P

INHA

= −40 dBm, P

INHA

= −16 dBm ±0.2 dB

INHB

= −40 dBm +0.25 dB

INHB

, P

= −40 dBm −0.5 dB

INHB

±0.3 dB

±0.4 dB

±0.3 dB

±0.4 dB

46 dB

= −16 dBm, P

INHB

= −40 dBm, P

INHA

= −50 dBm,

INHB

= −30 dBm,

INHB

= −30 dBm,

INHB

= −30 dBm, B

INHB

= −50 dBm,

Rev. 0 | Page 4 of 40

ADL5519

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Parameter Conditions Min Typ Max Unit

MEASUREMENT MODE,

2.2 GHz OPERATION

ADJA = 0.48 V, ADJB = 0.6 V; OUTA, OUTB shorted to VSTA, VSTB; OUTP, OUTN shorted to FBKA, FBKB, respectively; sinusoidal input signal; error referred to best fit line using linear regression between P

INHA

, P

INHB

= −40 dBm and −10 dBm B Input Impedance 408||0.34 Ω||pF OUTA, OUTB ± 1 dB Dynamic Range 55 dB

−40°C < TA < +85°C 50 dB OUTA, OUTB Maximum Input Level ±1 dB error −5 dBm OUTA, OUTB Minimum Input Level ±1 dB error −60 dBm OUTA, OUTB, OUTP, OUTN Slope OUTA, OUTB Intercept

Output Voltage (High Power In) OUTA, OUTB @ P Output Voltage (Low Power In) OUTA, OUTB @ P

−22 mV/dB

16.9 dBm , P

INHA

= −10 dBm 0.6 V

INHB

, P

= −40 dBm 1.26 V

INHB

OUTP, OUTN Dynamic Gain Range ±1 dB error 56 dB

−40°C < TA < +85°C 40 dB Temperature Sensitivity Deviation from OUTA, OUTB @ 25°C

−40°C < TA < +85°C, P 25°C < TA < 85°C, P

−40°C < TA < +25°C, P

INHA

, P

INHA

, P

INHA

= −16 dBm ±0.28 dB

INHB

= −40 dBm +0.3 dB

INHB

, P

= −40 dBm −0.5 dB

INHB

Distribution of OUTP, OUTN from 25°C

25°C < T

< 85°C, P

= −16 dBm, P

INHA

= −30 dBm,

INHB

typical error = −0.07 dB

−40°C < T

< +25°C, P

= −16 dBm, P

INHA

= −30 dBm,

INHB

typical error = 0.25 dB 25°C < T

< 85°C, P

= −40 dBm, P

INHA

= −30 dBm,

INHB

typical error = 0.17 dB

−40°C < T

< +25°C, P

= −40 dBm, P

INHA

= −30 dBm

INHB

typical error = −0.22dB Input A-to-Input B Isolation 60 dB Input A-to-OUTB Isolation

Input B-to-OUTA Isolation

MEASUREMENT MODE,

3.6 GHz OPERATION

Frequency separation = 1 kHz, P

– P

INHA

when OUTB/Slope = 1 dB

INHB

Frequency separation = 1 kHz, P

– P

INHB

when OUTA/Slope = 1 dB

INHA

ADJA = 0.35 V ADJB = 0.42; OUTA, OUTB shorted to

VSTA, VSTB; OUTP, OUTN shorted to FBKA, FBKB, respectively;

= −50 dBm,

INHA

= −50 dBm,

INHB

sinusoidal input signal; error referred to best fit line using

linear regression between P

INHA

, P

INHB

= −40 dBm and −10 dBm B Input Impedance 187||0.66 Ω||pF OUTA, OUTB ± 1 dB Dynamic Range 54 dB

−40°C < TA < +85°C 44 dB OUTA, OUTB Maximum Input Level ±1 dB error −4 dBm OUTA, OUTB Minimum Input Level ±1 dB error −58 dBm OUTA, OUTB, OUTP, OUTN Slope OUTA, OUTB Intercept

Output Voltage (High Power In) OUTA, OUTB @ P Output Voltage (Low Power In) OUTA, OUTB @ P

−22.5 mV/dB 17 dBm

, P

INHA

= −10 dBm 0.62 V

INHB

, P

= −40 dBm 1.31 V

INHB

OUTP, OUTN Dynamic Gain Range ±1 dB error 52 dB

−40°C < TA < +85°C 42 dB

±0.25 dB

±0.4 dB

±0.25 dB

±0.4 dB

46 dB

Rev. 0 | Page 5 of 40

ADL5519

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Parameter Conditions Min Typ Max Unit

Temperature Sensitivity Deviation from OUTA, OUTB @ 25°C

−40°C < TA < +85°C, P 25°C < TA < 85°C, P

−40°C < TA < +25°C, P Distribution of OUTP, OUTN from 25°C

25°C < T

< 85°C, P

typical error = −0.07 dB

−40°C < T

< +25°C, P

typical error = 0.27 dB 25°C < T

< 85°C, P

typical error = 0.31 dB

−40°C < T

< +25°C, P

typical error = −0.14 dB Input A-to-Input B Isolation 40 dB Input A-to-OUTB Isolation

Input B-to-OUTA Isolation

MEASUREMENT MODE,

5.8 GHz OPERATION

Frequency separation = 1 kHz, P

– P

INHA

when OUTB/Slope = 1 dB

INHB

Frequency separation = 1 kHz, P

– P

INHB

when OUTA/Slope = 1 dB

INHA

ADJA = 0.58 V, ADJB = 0.7 V; OUTA, OUTB shorted to

VSTA, VSTB; OUTP, OUTN shorted to FBKA, FBKB respectively;

sinusoidal input signal; error referred to best fit line using

linear regression between P Input Impedance 28||1.19 Ω||pF OUTA, OUTB ± 1 dB Dynamic Range 53 dB

−40°C < TA < +85°C 45 dB OUTA, OUTB Maximum Input Level ±1 dB error −2 dBm OUTA, OUTB Minimum Input Level ±1 dB error −55 dBm OUTA, OUTB, OUTP, OUTN Slope OUTA, OUTB Intercept

Output Voltage (High Power In) OUTA, OUTB @ P Output Voltage (Low Power In) OUTA, OUTB @ P

−22.5 mV/dB

20 dBm

INHA

OUTP, OUTN Dynamic Gain Range ±1 dB error 53 dB

−40°C < TA < +85°C 46 dB Temperature Sensitivity Deviation from OUTA, OUTB @ 25°C

−40°C < TA < +85°C, P 25°C < TA < 85°C, P

−40°C < TA < +25°C, P Distribution of OUTP, OUTN from 25°C

25°C < T

< 85°C, P

typical error = 0.02 dB

−40°C < T

< +25°C, P

typical error = 0.25 dB

25°C < T

< 85°C, P

typical error = 0.13 dB

−40°C < T

< +25°C, P

typical error = 0.06 dB Input A-to-Input B Isolation 45 dB Input A-to-OUTB Isolation

Input B-to-OUTA Isolation

Frequency separation = 1 kHz, P

– P

INHA

when OUTB/Slope = 1 dB

INHB

Frequency separation = 1 kHz, P

– P

INHB

when OUTA/Slope = 1 dB

INHA

, P

INHA

, P

INHA

= −16 dBm, P

INHA

= −40 dBm, P

INHA

= −16 dBm ±0.4 dB

INHB

= −40 dBm +0.6 dB

INHB

, P

= −40 dBm −0.45 dB

INHB

±0.25 dB

±0.45 dB

±0.3 dB

±0.5 dB

20 dB

= −16 dBm, P

INHB

= −40 dBm, P

INHA

= −50 dBm,

INHB

= −30 dBm,

INHB

= −30 dBm,

INHB

= −30 dBm,

INHB

= −50 dBm,

, P

= −40 dBm and −20 dBm B

INHA

INHB

, P

= −10 dBm 0.68 V

INHB

, P

= −40 dBm 1.37 V

INHB

, P

INHA

, P

INHA

= −16 dBm, P

INHA

= −40 dBm, P

INHA

= −16dBm ±0.25 dB

INHB

= −40 dBm +0.25 dB

INHB

, P

= −40 dBm −0.4 dB

INHB

±0.3 dB

±0.4 dB

±0.3 dB

±0.5 dB

48 dB

= −16 dBm, P

INHB

= −40 dBm, P

INHA

= −50 dBm,

INHB

= −30 dBm,

INHB

= −30 dBm,

INHB

= −30 dBm,

INHB

= −50 dBm,

Rev. 0 | Page 6 of 40

ADL5519

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Parameter Conditions Min Typ Max Unit

MEASUREMENT MODE,

8 GHz OPERATION

ADJA = 0.72 V, ADJB = 0.82 V to GND; OUTA, OUTB shorted to VSTA, VSTB; OUTP, OUTN shorted to FBKA, FBKB, respectively; sinusoidal input signal; error referred to best fit line using linear regression between P

INHA

, P

INHB

= −40 dBm and −20 dBm B Input Impedance +10||−1.92 Ω||pF OUTA, OUTB ± 1 dB Dynamic Range 48 dB

−40°C < TA < +85°C 38 dB OUTA, OUTB Maximum Input Level ±1 dB error 0 dBm OUTA, OUTB Minimum Input Level ±1 dB error −48 dBm OUTA, OUTB, OUTP, OUTN Slope OUTA, OUTB Intercept

Output Voltage (High Power In) OUTA, OUTB @ P Output Voltage (Low Power In) OUTA, OUTB @ P

−22 mV/dB 26 dBm

, P

INHA

= −10 dBm 0.81 V

INHB

, P

= −40 dBm 1.48 V

INHB

OUTP, OUTN Dynamic Gain Range ±1 dB error 50 dB

−40°C < TA < +85°C 42 dB Temperature Sensitivity Deviation from OUTA, OUTB @ 25°C

−40°C < TA < +85°C, P 25°C < TA < 85°C, P

−40°C < TA < +25°C, P

INHA

, P

INHA

, P

INHA

= −16 dBm ±0.4 dB

INHB

= −40 dBm −0.1 dB

INHB

, P

= −40 dBm +0.5 dB

INHB

Distribution of OUTP, OUTN from 25°C

25°C < T

< 85°C, P

= −16 dBm, P

INHA

= −30 dBm,

INHB

typical error = 0.2dB

−40°C < T

< +25°C, P

= −16 dBm, P

INHA

= −30 dBm,

INHB

typical error = 0.09dB 25°C < T

< 85°C, P

= −40 dBm, P

INHA

= −30 dBm,

INHB

typical error = −0.07dB

−40°C < T

< +25°C, P

= −40 dBm, P

INHA

= −30 dBm,

INHB

typical error = 0.17 dB Input A-to-Input B Isolation 45 dB Input A-to-OUTB Isolation

Input B-to-OUTA Isolation

Frequency separation = 1 kHz, P

– P

INHA

when OUTB/Slope = 1 dB

INHB

Frequency separation = 1 kHz, P

– P

INHB

when OUTA/Slope = 1 dB

INHA

= −50 dBm,

INHA

= −50 dBm,

INHB

OUTPUT INTERFACE OUTA, OUTB; OUTP, OUTN

OUTA, OUTB Voltage Range VSTA, VSTB = 1.7 V, RF in = open 0.3 V VSTA, VSTB = 0 V, RF in = open VP − 0.4 V OUTP, OUTN Voltage Range FBKA, FBKB = open and OUTA < OUTB, RL ≥ 240 Ω to ground 0.09 V FBKA, FBKB = open and OUTA > OUTB, RL ≥ 240 Ω to ground VP − 0.15 V Source/Sink Current Output held at 1 V to 1% change 10 mA Capacitance Drive 1 nF Output Noise

INHA, INHB = 2.2 GHz, −10 dBm, f

= 100 kHz,

NOISE

CLPA, CLPB = open Fall Time

Input level = no signal to −10 dBm, 80% to 20%,

CLPA, CLPB = 10 pF

Input level = no signal to −10 dBm, 80% to 20%,

CLPA, CLPB = open Rise Time

Input level = −10 dBm to no signal, 20% to 80%,

CLPA, CLPB = 10 pF

Input level = −10 dBm to no signal, 20% to 80%,

CLPA, CLPB = open Video Bandwidth

10 MHz

(or Envelope Bandwidth)

SETPOINT INTERFACE VSTA, VSTB

Nominal Input Range Input level = 0 dBm, measurement mode 0.38 V Input level = –50 dBm, measurement mode 1.6 V Input Resistance Controller mode, sourcing 50 μA 40 kΩ

Rev. 0 | Page 7 of 40

±0.3 dB

±0.5 dB

±0.3 dB

±0.5 dB

30 dB

10 nV/√Hz

12 ns

6 ns

16 ns

8 ns

ADL5519

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Parameter Conditions Min Typ Max Unit

DIFFERENCE LEVEL ADJUST VLVL (Pin 6)

Input Voltage OUTP, OUTN = FBKA, FBKB VP − 1 V Input Resistance OUTP, OUTN = FBKA, FBKB 100 kΩ

TEMPERATURE COMPENSATION ADJA, ADJB

Input Resistance ADJA, ADJB = 0.9 V, sourcing 50 μA 13 kΩ Disable Threshold Voltage ADJA, ADJB = open VP − 0.4 V

VOLTAGE REFERENCE VREF (Pin 5)

Output Voltage 1.15 V Temperature Sensitivity −40°C < TA < +25°C; relative TA = 25°C +26 μV/°C 25°C < TA < 85°C; relative TA = 25°C −26 μV/°C Current Limit Source/Sink 3/3 mA

TEMPERATURE REFERENCE TEMP (Pin 19)

Output Voltage 1.36 V Temperature Sensitivity −40°C < TA < +125°C 4.5 mV/°C Current Limit Source/Sink 4/50 mA/μA

POWER-DOWN INTERFACE PWDN (Pin 28)

Logic Level to Enable Logic low enables 0 V Logic Level to Disable Logic high disables VP − 0.2 V Input Current Logic high PWDN = 5 V 2 μA Logic low PWDN = 0 V 20 μA Enable Time

Disable Time

POWER INTERFACE VPSA, VPSB, VPSR

Supply Voltage 3.3 5.5 V Quiescent Current 60 mA

vs. Temperature −40°C ≤ TA ≤ +85°C 147 μA/°C

Disable Current ADJA, ADJB = PWDN = VP <1 mA

Slope and intercept are determined by calculating the best-fit line between the power levels of −40 dBm and −10 dBm at the specified input frequency.

PWDN low to OUTA, OUTB at 100% final value, CLPA, CLPB = open, RF in = −10 dBm

PWDN high to OUTA, OUTB at 10% final value, CLPA, CLPB = open, RF in = 0 dBm

0.4 μs

0.25 μs

Rev. 0 | Page 8 of 40

ADL5519

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage: VPSA, VPSB, VPSR 5.7 V V

Voltage: VSTA, VSTB 0 to V

SET

Input Power (Single-Ended, Re: 50 Ω)

INHA, INLA, INHB, INLB

Internal Power Dissipation 420 mW θ

Maximum Junction Temperature 142°C Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering, 60 sec) 260°C

12 dBm

42°C/W

Stresses above those listed under Absolute Maximum Ratings

y ca

use permanent damage to the device. This is a stress

ma rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. 0 | Page 9 of 40

ADL5519

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OMR

INHB

COMR

INLA

INLB

INHA

NC = NO CONNECT

1COMR 2COMR 3VPSB 4ADJB 5VREF 6VLVL 7CLPB 8VSTB

PIN 1 INDICATO R

ADL5519

TOP VIEW

(Not to Scale)

FBKB

OUTB

OUTN

OUTP

24 COMR 23 COMR 22 VPSA 21 ADJA 20 VPSR 19 TEMP 18 CLPA 17 VSTA

FBKA

OUTA

06198-002

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 COMR Connect via low impedance to common. 2 COMR Connect via low impedance to common. 3 VPSB Positive Supply for Channel B. Apply 3.3 V to 5.5 V supply voltage. 4 ADJB Dual-Function Pin: Temperature Adjust Pin for Channel B and Power-Down Interface for OUTB. 5 VREF Voltage Reference (1.15 V). 6 VLVL DC Common-Mode Adjust for Difference Output. 7 CLPB Loop Filter Pin for Channel B. 8 VSTB Setpoint Control Input for Channel B. 9 NC No Connect. 10 OUTB Output Voltage for Channel B. 11 FBKB Difference Op Amp Feedback Pin for OUTN Op Amp. 12 OUTN Difference Output (OUTB − OUTA + VLVL). 13 OUTP Difference Output (OUTA − OUTB + VLVL). 14 FBKA Difference Op Amp Feedback Pin for OUTP Op Amp. 15 OUTA Output Voltage for Channel A. 16 NC No Connect. 17 VSTA Setpoint Control Input for Channel A. 18 CLPA Loop Filter Pin for Channel A. 19 TEMP Temperature Sensor Output (1.3 V with 4.5 mV/°C Slope). 20 VPSR Positive Supply for Difference Outputs and Temperature Sensor. Apply 3.3 V to 5.5 V supply voltage. 21 ADJA Dual-Function Pin: Temperature Adjust Pin for Channel A and Power-Down Interface for OUTA. 22 VPSA Positive Supply for Channel A. Apply 3.3 V to 5.5 V supply voltage. 23 COMR Connect via low impedance to common. 24 COMR Connect via low impedance to common. 25 INHA AC-Coupled RF Input for Channel A. 26 INLA AC-Coupled RF Common for Channel A. 27 COMR Connect via low impedance to common. 28 PWDN Power-Down for Difference Output and Temperature Sensor. 29 COMR Connect via low impedance to common. 30 COMR Connect via low impedance to common. 31 INLB AC-Coupled RF Common for Channel B. 32 INHB AC-Coupled RF Input for Channel B. Paddle Internally connected to COMR.

Rev. 0 | Page 10 of 40

ADL5519

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TYPICAL PERFORMANCE CHARACTERISTICS

VP = 5 V; TA = +25°C, −40°C, +85°C; CLPA, CLPB = 1 µF. Colors: +25°C black, −40°C blue, +85°C red.

2.00

2.0

1.75

1.50

1.25

1.00

0.75

OUTPUT VOLTAGE (V)

0.50

0.25

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

Figure 3. OUTA, OUTB Voltage and Log Conformance vs. Input Amplitude

at 10

0 MHz, Typical Device, ADJA, ADJB = 0.65 V, 0.7 V, Sine Wave,

Single-Ended Drive

2.0

1.5

1.0

0.5

ERROR (dB)

–0.5

–1.0

–1.5

OUTP

1.5

1.0

ERROR (dB)

0.5

OUTP, OUTN OUTPUT VOLTAGE (V)

–60 –50 –40 –30 –20 –10 0 10

06198-003

PIN (dBm)

OUTN

1.0

–1.0

–2.0

ERROR (dB)

06198-006

Figu re 6. OUTP, OUTN Gain Error and Voltage vs . Input Amplitude at 100 MHz,

Typ

ical Device, ADJA, ADJB = 0.65 V, 0.7, Sine Wave, Single-Ended Drive,

1.5

1.0

0.5

–0.5

–1.0

–1.5

OUTP – OUTN OUTPUT VOLTAGE (V)

= −30 dBm, Channel A Swept B

INHB

2.0

1.0

ERROR (dB)

–1.0

–2.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

06198-004

Figu re 4. Distribution of OUTA, OUTB Error over Temperature A fter Ambient

Normalization v

s. Input Amplitude for 45 Devices, Frequency = 100 MHz,

ADJA, ADJB = 0.65 V, 0.7 V, Sine Wave, Single-Ended Drive

2.0

1.5

1.0

0.5

–0.5

OUTA – OUTB (V)

–1.0

–1.5

–2.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

06198-005

Figure 5. Distribution of [OUTA − OUTB] Voltage Difference over Temperature

for

45 Devices from a Nominal Lot, Frequency = 100 MHz,

ADJA, ADJB = 0.65 V, 0.7 V, Sine W ave, Si ngle-E nded D rive

Rev. 0 | Page 11 of 40

–2.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

Figu re 7. Distribution of [OU TP − OUTN] Gain Error and Volta

–2.0

ge vs. Input

Amplitude over Temperature, After Ambient Normalization for 45 Devices from

a Nominal Lot, Frequency = 100 MHz, ADJA, ADJB = 0.65 V, 0.7 V , Sine Wave,

Single-Ended Drive, P

2.00

1.75

1.50

1.25

1.00

0.75

OUTPUT VOLTAGE (V)

0.50

0.25

–60 –50 –40 –30 –20 –10 0 10

= −30 dBm, Channel A Swept B

INHB

PIN (dBm)

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

ERROR (dB)

Figure 8. OUTA, OUTB Voltage and Log Conformance vs. Input Amplitude

at 90

0 MHz, Typical Device, ADJA, ADJB = 0.6 V, 0.65 V, Sine Wave,

Single-Ended Drive

06198-007

06198-008

ADL5519

www.BDTIC.com/ADI

2.0

1.5

2.0

1.0

ERROR (dB)

–1.0

–2.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

Figure 9. Distribution of OUTA, OUTB Error over Temperature After A mbient

Normal

ization vs. Input Amplitude for 45 Devices, Frequency = 900 MHz, ADJA, ADJB = 0.6 V, 0.65 V, Sine Wave, Single-Ended Drive

0.20

0.15

0.10

0.05

–0.05

OUTA – OUTB (V)

–0.10

1.0

0.5

–0.5

–1.0

OUTP – OUTN OUTPUT VOLTAGE (V)

–1.5

–2.0

–60 –50 –40 –30 –20 –10 0 10

06198-009

PIN (dBm)

1.0

ERROR (dB)

–1.0

–2.0

06198-012

Figure 12. Distribution of [OUTP − OUTN] Gain Error and Voltage vs. Input Amplitude over Temperature, After Ambient Normalization for 45 Devices

from a Nom inal L ot, Frequency = 900 MHz, ADJA, ADJB = 0.6 V, 0. 65 V, Sine

Wave, Single-Ended Drive, P

2.0

1.5

1.0

OUTPUT VOLTAGE (V)

0.5

= −30 dBm, Channel A Swept

INHB

2.0

1.0

ERROR (dB)

–1.0

–0.15

–0.20

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

Figure 10. Distribution of [OUTA − OUTB] Voltage Difference over

Tem

perature for 45 Devices from a Nominal Lot, Frequency = 900 MHz,

ADJA, ADJB = 0.6 V, 0.65 V, Sine Wave, Single-Ended Drive

2.0

OUTP

1.5

1.0

0.5

OUTP, OUTN OUTPUT VOLTAGE (V)

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

OUTN

Figure 11. OUTP, OUTN Gain Error and Voltage vs. Input Amplitude at

900 MH

z, Typical Device, ADJA, ADJB = 0.6 V, 0.65 V, Sine Wave,

Single-Ended Drive; P

= −30 dBm, Channel A Swept

INHB

2.0

1.0

–1.0

–2.0

–60 –50 –40 –30 –20 –10 0 10

06198-010

PIN (dBm)

–2.0

06198-013

Figure 13. OUTA, OUTB Voltage and Log Conformance vs. Input Amplitude at

1.9 GHz, Typical Device, ADJA, ADJB = 0.5 V, 0.55 V, Sine Wave, Single-Ended Drive

2.0

1.0

ERROR (dB)

06198-011

ERROR (dB)

–1.0

–2.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

06198-014

Figure 14. Distribution of OUTA, OUTB Error over Temperature After Ambient

Normalization vs. Input Amplitude for 45 Devices, Frequency = 1.9 GHz,

ADJA, ADJB = 0.5 V, 0.55 V, Sine Wave, Single-Ended Drive

Rev. 0 | Page 12 of 40

ADL5519

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0.20

0.15

2.0

0.10

0.05

–0.05

OUTA – OUTB (V)

–0.10

–0.15

–0.20

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

Figure 15. Distribution of [OUTA – OUTB] Voltage Difference over

Tem

peratur e for 45 Devices from a Nominal Lot, Frequency = 1.9 GHz,

ADJA, ADJB = 0.5 V, 0.55 V, Si ne Wav e, Sing le-End ed Dri ve

2.0

1.5

1.0

0.5

OUTP, OUTN OUTPUT VOLTAGE (V)

OUTP

OUTN

1.5

1.0

OUTPUT VOLTAGE (V)

0.5

–60 –50 –40 –30 –20 –10 0 10

06198-015

PIN (dBm)

1.0

–1.0

–2.0

ERROR (dB)

06198-018

Figure 18. OUTA, OUTB Voltage and Log Conformance vs. Input Amplitude at

2.2 GHz, Ty

pical Device, ADJA, ADJB = 0.48 V, 0.6 V, Sine Wave,

Single-Ended Drive

2.0

1.0

ERROR (dB)

–1.0

2.0

1.0

ERROR (dB)

–1.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

–2.0

Figure 16. OUTP, OUTN Gain Error and Voltage vs. Input Amplitude at

1.9 GHz, wi

th B Input Held at −30 dBm and A Input Swept, Typical Device,

ADJA, ADJB = 0.5 V, 0.55 V, Sine Wave, Single-Ended Drive,

= −30 dBm, Channel A Swept B

INHB

2.0

1.5

1.0

0.5

–0.5

–1.0

OUTP – OUTN OUTPUT VOLTAGE (V)

–1.5

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

2.0

1.0

–1.0

–2.0

Figure 17. Distribution of [OUTP − OUTN] Gain Error and Voltage vs. Input Ampl

itude over Temperature, After Ambient Normalization for 45 Devices

from a Nominal Lot, Frequency = 1.9 GHz, ADJA, ADJB = 0.5 V, 0.55 V,

= −30 dBm, Channel A Swept

Sine Wave, Single-Ended Drive, P

INHB

–2.0

–60 –50 –40 –30 –20 –10 0 10

06198-016

PIN (dBm)

06198-019

Figu re 19. Dis tribution of OUTA, OUTB Error over Temperature After Ambient

Normalization v

s. Input Amplitude for at Least 45 Devices from a Nominal Lot,

Frequency = 2.2 GHz, ADJA, ADJB = 0.48 V, 0.6 V, Sine Wave, Single-Ended Drive

0.20

0.15

0.10

0.05

ERROR (dB)

06198-017

–0.05

OUTA – OUTB (V)

–0.10

–0.15

–0.20

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

06198-020

Figure 20. Distribution of [OUTA – OUTB] Voltage Difference over

Tem

peratur e for 45 Devices from a Nominal Lot, Frequency = 2.2 GHz,

ADJA, ADJB = 0.48 V, 0.6 V, Si ne Wave , Sing le-End ed Dri ve

Rev. 0 | Page 13 of 40

ADL5519

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2.0

1.5

1.0

0.5

OUTP, OUTN OUTPUT VOLTAGE (V)

–60 –50 –40 –30 –20 –10 0 10

OUTP

PIN (dBm)

OUTN

1.0

ERROR (dB)

–1.0

–2.0

Figu re 21. OUTP, OUTN Gain Error and Voltage vs. Input Amplitude at 2.2 GHz,

Typical Devi

–0.5

–1.0

OUTP – OUTN OUTPUT VOLTAGE (V)

ce, ADJA, ADJB = 0.48 V, 0.6 V, Sine Wave, Single-Ended Drive,

= −30 dBm, Channel A Swept B

INHB

2.0

1.5

1.0

0.5

2.0

1.0

–1.0

1.0

ERROR (dB)

–1.0

–2.0

–60 –50 –40 –30 –20 –10 0 10

06198-021

PIN (dBm)

06198-024

Figure 24. Distribution of OUTA, OUTB Error over Temperature After Ambient

Normal

ization vs. Input Amplitude for 45 Devices from a Nominal Lot,

Frequency = 3.6 GHz, ADJA, ADJB = 0.35 V, 0.42 V, Sine Wave,

Single-Ended Drive

0.20

0.15

0.10

0.05

ERROR (dB)

OUTA – OUTB (V)

–0.05

–0.10

–0.15

–1.5

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

–2.0

Figure 22. Distribution of [OUTP − OUTN] Gain Error and Voltage vs. Input Ampl

itude over Temperature, After Ambient Normalization for 45 Devices

from a Nominal Lot, Frequency = 2.2 GHz, ADJA, ADJB = 0.48 V, 0.6 V,

Sine Wave, Single-Ended Drive, P

2.0

1.5

1.0

OUTPUT VOLTAGE (V)

0.5

–60 –50 –40 –30 –20 –10 0 10

INHB

PIN (dBm)

= −30 dBm, Channel A Swept B

2.0

1.0

ERROR (dB)

–1.0

–2.0

Figure 23. OUTA, OUTB Voltage and Log Conformance vs. Input Amplitude

at 3.

6 GHz, Typical Device, ADJA, ADJB = 0.35 V, 0.42 V, Sine Wave,

Single-Ended Drive

–0.20

–60 –50 –40 –30 –20 –10 0 10

06198-022

PIN (dBm)

06198-025

Figure 25. Distribution of [OUTA – OUTB] Voltage Difference over

Tem

peratur e for 45 Devices from a Nominal Lot, Frequency = 3.6 GHz, ADJA, ADJB = 0.35 V, 0.42 V, Si ne Wav e, Sing le-End ed Dri ve

2.0

1.5

1.0

0.5

OUTP, OUTN OUTPUT VOLTAGE (V)

–60 –50 –40 –30 –20 –10 0 10

06198-023

OUTP

PIN (dBm)

OUTN

2.0

1.0

–1.0

–2.0

ERROR (dB)

06198-026

Figure 26. OUTP, OUTN Gain Error and Voltage vs. Input Amplitude at

3.6 GHz, Ty

pical Device, ADJA, ADJB = 0.35 V, 0.42 V, Sine Wave,

Single-Ended Drive; P

= −30 dBm, Channel A Swept

INHB

Rev. 0 | Page 14 of 40

ADL5519

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1.5

2.0

0.20

1.0

0.5

–0.5

–1.0

OUTP – OUTN OUTPUT VOLTAGE (V)

–1.5

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

–1.0

–2.0

Figure 27. Distribution of [OUTP − OUTN] Gain Error and Voltage vs. Input Ampl

itude over Temperature, After Ambient Normalization for 45 Devices

from a Nominal Lot, Frequency = 3.6 GHz, ADJA, ADJB = 0.35 V, 0.42 V,

Sine Wave, Single-Ended Drive, P

2.00

1.75

1.50

1.25

1.00

0.75

OUTPUT VOLTAGE (V)

0.50

0.25

INHB

= −30 dBm, Channel A Swept B

2.0

1.5

1.0

0.5

ERROR (dB)

–0.5

–1.0

–1.5

0.15

0.10

0.05

ERROR (dB)

06198-027

–0.05

OUTA – OUTB (V)

–0.10

–0.15

–0.20

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

06198-130

Figure 30. Distribution of [OUTA – OUTB] Voltage Difference over

Tem

perature for 45 Devices from a Nominal Lot, Frequency = 5.8 GHz,

ADJA, ADJB = 0.58 V, 0.7 V, Sine Wave, Single-Ended Drive

2.00

1.75

1.50

1.25

1.00

0.75

0.50

OUTP, OUTN OUTPUT VOLTAGE (V)

0.25

OUTP

OUTN

2.0

1.5

1.0

0.5

ERROR (dB)

–0.5

–1.0

–1.5

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

–2.0

Figure 28. OUTA, OUTB Voltage and Log Conformance vs. Input Amplitude at

5.8 GHz, Ty

pical Device, ADJA, ADJB = 0.58 V, 0.7 V, Sine Wave,

Single-Ended Drive

2.0

1.0

ERROR (dB)

–1.0

–2.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

06198-101

Figure 29. Distribution of OUTA, OUTB Error over Temperature After Ambient

Normal

ization vs. Input Amplitude for at Least 15 Devices from Multiple Lots,

Frequency = 5.8 GHz, ADJA, ADJB = 0.58 V, 0.7 V,

Sine Wave, Single-Ended Drive

–60 –50 –40 –30 –20 –10 0 10

06198-102

PIN (dBm)

–2.0

06198-131

Figure 31. OUTP, OUTN Gain Error and Voltage vs. Input Amplitude at

5.8 GHz, Ty

2.0

1.5

1.0

0.5

–0.5

–1.0

OUTP – OUTN OUTPUT VOLTAGE (V)

–1.5

–2.0

–60 –50 –40 –30 –20 –10 0 10

pical Device, ADJA, ADJB = 0.58 V, 0.7 V, Sine Wave,

Single-Ended Drive, P

= −30 dBm, Channel A Swept

INHB

PIN (dBm)

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

ERROR (dB)

06198-105

Figure 32. Distribution of [OUTP − OUTN] Gain Error and Voltage vs. Input Ampl

itude over Temperature, After Ambient Normalization for 45 Devices

from a Nominal Lot, Frequency = 5.8 GHz, ADJA, ADJB = 0.58 V, 0.7 V,

Sine Wave, Single-Ended Drive, P

INHB

= −30 dBm, Channel A Swept B

Rev. 0 | Page 15 of 40

ADL5519

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2.00

2.0

2.00

2.0

1.75

1.50

1.25

1.00

0.75

OUTPUT VOLTAGE (V)

0.50

0.25

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

ERROR (dB)

Figure 33. OUTA, OUTB Voltage and Log Conformance vs. Input Amplitude at

8 GHz, Ty

pical Device, ADJA, ADJB = 0.72 V, 0.82 V, Sine Wave,

Single-Ended Drive

2.0

1.5

1.0

0.5

ERROR (dB)

–0.5

–1.0

–1.5

1.75

1.50

1.25

1.00

0.75

0.50

OUTP, OUTN OUTPUT VOLTAGE (V)

0.25

–60 –50 –40 –30 –20 –10 0 10

06198-107

OUTP

PIN (dBm)

OUTN

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

ERROR (dB)

06198-136

Figure 36. OUTP, OUTN Gain Error and Voltage vs. Input Amplitude at 8 GHz,

Typical

Device, ADJA, ADJB = 0.72 V, 0.82 V, Sine Wave, Single-Ended Drive,

1.5

1.0

0.5

–0.5

–1.0

–1.5

OUTP – OUTN OUTPUT VOLTAGE (V)

= −30 dBm, Channel A Swept B

INHB

2.0

1.0

ERROR (dB)

–1.0

–2.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

06198-106

Figure 34. Distribution of OUTA, OUTB Error over Temperature After Ambient

Normal

ization vs. Input Amplitude for 45 Devices from a Nominal Lot,

Frequency = 8 GHz, ADJA, ADJB = 0.72 V, 0.82 V, Sine Wave,

Single-Ended Drive

0.20

0.15

0.10

0.05

–0.05

OUTA – OUTB (V)

–0.10

–0.15

–0.20

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

06198-135

Figure 35. Distribution of [OUTA − OUTB] Voltage Difference over

Tem

perature for 45 Devices from a Nominal Lot, Frequency = 8 GHz, ADJA, ADJB = 0.72 V, 0.82 V, Sine Wave, Single-Ended Drive

–2.0

–60 –50 –40 –30 –20 –10 0 10

PIN (dBm)

–2.0

Figure 37. Distribution of [OUTP − OUTN] Gain Error and Voltage vs. Input Ampl

itude over Temperature, After Ambient Normalization for 45 Devices

from a Nominal Lot, Frequency = 8 GHz, ADJA, ADJB = 0.72 V, 0.82 V,

–j1

INHB

= −30 dBm, Channel A Swept B

3600MHz

210.50.2

1900MHz

2200MHz

100MHz

900MHz

–j2

06198-138

= 50 Ω

Sine Wave, Single-Ended Drive, P

j0.5

j0.2

–j0.2

3600MHz

–j0.5

Figure 38. Single-Ended Input Impedance (S11) vs. Frequency; Z

06198-110

Rev. 0 | Page 16 of 40

ADL5519

www.BDTIC.com/ADI

10µ

1200

1000

800

MEAN: 1.14986

1µ

INHA = 0dBm INHB = 0dBm INHA = –20dBm INHB = –20dBm

INHA = –40dBm INHB = –40dBm INHA = OFF INHB = OFF

600

COUNT

400

200

1.12 1.14 1. 16 1.18

VREF (V)

Figure 39. Distribution of VREF Pin Voltage for 4000 Devices

MEAN: 1.36332

COUNT

1200

1000

800

600

400

200

1.321.30 1.34 1.36 1.401.38 1.42

TEMP (V)

Figure 40. Distribution of TEMP Pin Voltage for 4000 Devices

1.170

1.165

1.160

1.155

1.150

(V)

1.145

REF

1.140

1.135

1.130

1.125

1.120 –40 –15 10 35 60 85

TEMPERATURE (°C)

Figure 41. Change in VREF Pin Voltage vs. Temperature for 45 Devices

100n

OUTPUT NOI SE (V/ Hz)

10n

1k 10k 100k 1M 10M 100M

06198-029

Figure 42. Noise Spectral Density of OUTA, OUTB; CLPA,

10µ

100n

OUTPUT NOI SE (V/ Hz)

10n

06198-030

OUTN, INHA = 0dBm OUTP, INHA = 0dBm OUTN, INHA = –20dBm OUTP, I NHA = –20dBm

1µ

1k 10k 100k 1M 10M 100M

FREQUENCY (Hz)

OUTN, INHA = –40dBm OUTP, I NHA = –40dBm OUTN, INHA = O FF OUTP, INHA = OFF

FREQUENCY (Hz)

CLPB = Open

06198-142

06198-143

Figure 43. Noise Spectral Density of OUTP, OUTN; CLPA, CLPB = 0.1 μF,

Freq

uency = 2140 MHz

10µ

INHA = 0dBm INHB = 0dBm INHA = –20dBm INHB = –20dBm

1µ

100n

OUTPUT NOI SE (V/ Hz)

10n

1k 10k 100k 1M 10M 10 0M

06198-141

Figure 44. Noise Spectral Density of OUTA, OUTB; CLPA,

INHA = –40dBm INHB = –40dBm INHA = OFF INHB = OFF

FREQUENCY (Hz)

CLPB = 0.1 μF,

06198-144

Frequency = 2140 MHz

Rev. 0 | Page 17 of 40

ADL5519

www.BDTIC.com/ADI

2.00

1.75

1.50

1.25

1.00

0.75

OUTPUT VOLTAGE OUTA, OUTB (V)

0.50

0.25

–6.0

–5.4

–4.8

INHA, INHB = –40d Bm

INHA, INHB = –30d Bm

INHA, INHB = –20d Bm

INHA, INHB = –10d Bm

–4.2

–3.6

–3.0

–2.4

–1.8

–1.2

–0.6

TIME (ns)

0.6

1.2

1.8

2.4

3.0

3.6

4.2

4.8

5.4

Figure 45. Output Response to RF Burst Input for Various RF Input Levels,

Carrier Fr

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

OUTPUT VOLTAGE OUTA, OUTB (V)

0.2

–5–3–1

equency = 900 MHz, CLPA = Open

INHA, INHB = –40d Bm

IINHA, INHB = –30dBm

INHA, INHB = –20d Bm

INHA, INHB = –10d Bm

11131517192123

TIME (µs)

Figure 46. Output Response to RF Burst Input for Various RF Input Levels,

Carrier Frequency = 900 MHz, CLPA = 0.1 μF

2.5

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

OUTPUT VOLTAGE OUTA, OUTB (V)

–2.0

–2.5

–0.4

0.2

–0.2

RF OFF INHA, INHB = –40d Bm INHA, INHB = –30d Bm INHA, INHB = –20d Bm INHA, INHB = –10d Bm INHA, INHB = 0d Bm PWDN PULSE

0.4

0.6

0.8

1.0

TIME (µs)

1.2

1.4

1.6

1.8

2.0

2.2

2.6

2.8

2.4

Figure 47. Output Response Using Power-Down Mode for Various

RF Input Levels, Carrier Frequency = 900 MHz, CLPA = Open

22.5

20.0

17.5

15.0

12.5

10.0

7.5

5.0

2.5

–2.5

3.0

6.0

06198-145

06198-146

INPUT VOLTAGE PWDN PULSE (V)

06198-147

2.5

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

OUTPUT VOL TAGE OUTA, OUTB ( V)

–2.0

–2.5

–0.4

–0.2

INHA, INHB = –40dBm INHA, INHB = –30dBm INHA, INHB = –20dBm INHA, INHB = –10dBm INHA, INHB = 0dBm PWDN PULSE

0.2

0.4

0.6

0.8

1.0

1.2

TIME (µs)

1.4

1.6

1.8

2.0

2.2

Figure 48. Output Response Using Power-Down Mode for Various

RF Input Levels, C

0.06

0.05

0.04

0.03

0.02

SUPPLY CURRENT (A)

0.01

3.03.23.43.63.84.04.24.44.64.85.0

Figure 49. Supply Current vs. V

arrier Frequency = 900 MHz, CLPA = 0.1 μF

INCREASING

DECREASING

PWDN, ADJA, ADJB VO LTAGE ( V)

, V

ADJA

, V

PWDN

2.4

ADJB

22.5

20.0

17.5

15.0

12.5

10.0

7.5

5.0

2.5

INPUT VOLTAGE PWDN PULSE (V)

–2.5

2.6

2.8

3.0

06198-148

06198-150

Rev. 0 | Page 18 of 40

ADL5519

www.BDTIC.com/ADI

THEORY OF OPERATION

The ADL5519 is a dual-channel, six-stage demodulating logarithmic amplifier that is specifically designed for use in RF measurement and power control applications at frequencies up to 10 GHz. The ADL5519 is a derivative of the logari

thmic detector/controller core. The ADL5519 maintains

AD8317

tight intercept variability vs. temperature over a 50 dB range. Each measurement channel offers performance equivalent to that of the shown in Fi

INHA

INLA

COMR

PWDN

COMR

INLB

INHB

AD8317. The complete circuit block diagram is

gure 50.

COM

24 23 22 21 20 19 18 17

ADL5519

CHANNEL A

LOG DETECTOR

OUTA OUTB

CHANNEL B

LOG DETECTOR

1 2 3 4 5 6 7 8

COMR

VPSA

VPSB

ADJA

TEMP

BIAS

ADJB

Figure 50. Block Diagram

VPSR

VREF

TEMP

VLVL

VSTA

CLPA

VSTB

CLPB

OUTA

FBKA

OUTP

OUTN

FBKB

OUTB

Each measurement channel is a full differential design using a proprietary, high speed SiGe process that extends high frequency performance. signal pa

Figure 51 shows the basic diagram of the Channel A

th; its functionality is identical to that of the Channel B

signal path.

DET DET DET DET

INHA

INLA

Figure 51. Single Channel Block Diagram

VSTA

OUTA

CLPA

06198-041

06198-042

The maximum input with ±1 dB log conformance error is typically

−5 dBm (re: 50 Ω). The noise spectral density referred to the input is 1.15 nV/√Hz, which is equivalent to a voltage of 118 µV rms in a 10.5 GHz bandwidth or a noise power of −66 dBm (re: 50 Ω). This noise spectral density sets the lower limit of the dynamic range. However, the low end accuracy of the ADL5519 is enhanced by specially shaping the demodulating transfer characteristic to partially compensate for errors due to internal noise. The common pins provide a quality, low impedance connection to the printed circuit board (PCB) ground. The package paddle, which is internally connected to the COMR pins, should also be grounded to the PCB to reduce thermal impedance from the die to the PCB.

The logarithmic function is approximated in a piecewise fashion by six cas tion of the logarithm approximation, refer to the sheet

caded gain stages. For a more comprehensive explana-

AD8307 data

. The cells have a nominal voltage gain of 9 dB each, with a 3 dB bandwidth of 10.5 GHz. Using precision biasing, the gain is stabilized over temperature and supply variations. The overall dc gain is high because of the cascaded nature of the gain stages. An offset compensation loop is included to correct for offsets within the cascaded cells. At the output of each gain stage, a square-law detector cell is used to rectify the signal.

The RF signal voltages are converted to a fluctuating differential cur

rent, having an average value that increases with signal level. Along with the six gain stages and detector cells, an additional detector is included at the input of each measurement channel, providing a 54 dB dynamic range in total. After the detector currents are summed and filtered, the following function is formed at the summing node:

× log10(VIN/V

) (1)

INTERCEPT

where:

is the internally set detector current.

is the input signal voltage.

is the intercept voltage (that is, when VIN = V

INTERCEPT

the output voltage would be 0 V, if it were capable of going to 0 V).

Rev. 0 | Page 19 of 40

ADL5519

www.BDTIC.com/ADI

USING THE ADL5519

BASIC CONNECTIONS

The ADL5519 is specified for operation up to 10 GHz. As a result, low impedance supply pins with adequate isolation between functions are essential. A power supply voltage between 3.3 V and 5.5 V should be applied to VPSA, VPSB, and VPSR. Power supply decoupling capacitors of 100 pF and 0.1 µF should be connected close to these power supply pins (see

Figure 53).

The paddle of the LFCSP package is internally connected to COMR. F

or optimum thermal and electrical performance, the

paddle should be soldered to a low impedance ground plane.

INPUT SIGNAL COUPLING

The ADL5519 inputs are differential but were characterized and are generally used single ended. When using the ADL5519 in single-ended mode, the INHA, INHB pins must be ac-coupled, and INLA, INLB must be ac-coupled to ground. Suggested coupling capacitors are 47 nF, ceramic 0402-style capacitors for input frequencies of 1 MHz to 10 GHz. The coupling capacitors should be mounted close to the INHA, INHB and INLA, INLB pins. The coupling capacitor values can be increased to lower the input stage high-pass cutoff frequency.

The high-pass corner is set by the input coupling capacitors and the inter

nal 10 pF high-pass capacitor. The dc voltage on INHA, INHB and INLA, INLB is approximately one diode voltage drop below the supply voltage.

Although the input can be reactively matched, in general this reactive matching is not necessary. An external 52.3 Ω shunt resistor (connected on the signal side of the input coupling capacitors, as shown in input

The coupling time constant, 50 × C with a 3 dB attenuation at f C2 = C3 = C4 = C pass corner is ~68 kHz. In high frequency applications, f be as large as possible to minimize the coupling of unwanted low frequency signals. In low frequency applications, a simple RC network forming a low-pass filter should be added at the input for similar reasons. This low-pass filter should generally be placed at the generator side of the coupling capacitors, thereby lowering the required capacitance value for a given high-pass corner frequency.

VPSA

5pF 5pF

18.7kΩ 18.7kΩ

INHA

INLA

Figure 52. Single-Channel Input Interface

CURRENT

STAGE

2kΩ

FIRST

GAIN

STAGE

A = 9dB

OFFSET COMP

6198-044

Figure 53) combines with the relatively high

impedance to give an adequate broadband match of 50 Ω.

/2, forms a high-pass corner

= 1/(2π × 50 × CC ), where C1 =

. Using the typical value of 47 nF, this high-

should

Rev. 0 | Page 20 of 40

ADL5519

VPSR

www.BDTIC.com/ADI

C15

0.1µF

TEMP SENSOR

C9 100pF

VSTA

CLPATEMPVPSRADJA

OUTA

FBKA

OUTP

OUTPUT VOLTAGE B

SETPOINT VOLTAGE B

DIFF OUT+

INHA

PWDN

VPSA

52.3Ω

ADJA

C12

0.1µF

47nF

100pF

24 23

COMR

INHA

INLA

COMR

PWDN

22 21 20 19 18 17

VPSA

C8 100pF

ADL5519ACPZ

C10 100pF

VSTB

OUTN

FBKB

OUTB

VPOS

DIFF OUT–

OUTPUT VOLTAGE B

SETPOINT VOLTAGE B

VPSA

VPSB

VPSR

06198-043

INHB

52.3Ω

COMR

47nF

INLB

INHB

COMR

1 2

C16

100pF

C11

0.1µF

EXPOSED PADDLE

3 4 5 6 7 8

0.1µF

VPSB

VREFADJB

CLPBVLVLVREFADJBVPSB

VLVL

Figure 53. Basic Connections for Operation in Measurement Mode

Rev. 0 | Page 21 of 40

ADL5519

VPSR

www.BDTIC.com/ADI

TEMPERATURE SENSOR INTERFACE

The ADL5519 provides a temperature sensor output capable of driving 4 mA. The temperature scaling factor of the output voltage is ~4.48 mV/°C. The typical absolute voltage at 27°C is approximately 1.36 V.

INTERNAL

VPTAT

12kΩ

4kΩ

COMR

Figure 54. TEMP Interface Simplified Schematic

TEM

06198-045

VREF INTERFACE

The VREF pin provides a highly stable voltage reference. The voltage on the VREF pin is 1.15 V, which is capable of driving 3 mA. An equivalent internal resistance is connected from VREF to COMR for 3 mA sink capability.

POWER-DOWN INTERFACE

The operating and stand-by currents for the ADL5519 at 27°C are approximately 60 mA and less than 1 mA, respectively. To completely power down the ADL5519, the PWDN and ADJA, ADJB pins must be pulled within 200 mV of the supply voltage. When powered on, the output reaches to within 0.1 dB of its steady-state value in about 0.5 μs; the reference voltage is available to full accuracy in a much shorter time.

This wake-up response time varies, depending on the input coupling network and the capacitance at the CLPA, CLPB pins. PWDN disables the OUTP, OUTN, VREF, and TEMP pins. The power-down pin, PWDN, is a high impedance pin.

The ADJA and ADJB pins, when pulled within 200 mV of the supply voltage, disable OUTA and OUTB, respectively.

SETPOINT INTERFACE—VSTA, VSTB

The VSTA, VSTB inputs are high impedance (40 kΩ) pins that drive inputs of internal op amps. The V the internal 1.5 kΩ resistor to generate a current, I portion of V

−I = V

If V

SET

is applied to VSTA, VSTB, the feedback loop forces

OUT

× log10(VIN/V

/2x, then I

OUT

INTERCEPT

= V

SET

) = I

OUT

voltage appears across

SET

. When a

SET

(2)

SET

/(2x × 1.5 kΩ).

The result is

= (−ID × 1.5 kΩ × 2x) × log10(VIN/V

OUT

20kΩ

SET

1.5kΩ

SET

Figure 55. VSTA, VSTB Interface Simplified Schematic

COMMCOMM

INTERCEPT

SET

)

06198-048

The slope is given by −ID × 2x × 1.5 kΩ = −22 mV/dB × x. For example, if a resistor divider to ground is used to generate a V voltage of V

/2, then x = 2. The slope is set to −880 V/decade

OUT

SET

or −44 mV/dB. See the Altering the Slope section for additional information.

OUTPUT INTERFACE—OUTA, OUTB

The OUTA, OUTB pins are driven by a push-pull output stage. The rise time of the output is limited mainly by the slew on CLPA, CLPB. The fall time is an RC-limited slew given by the load capacitance and the pull-down resistance at OUTA, OUTB. There is an internal pull-down resistor of 1.6 kΩ The resistive load at OUTA, OUTB can be placed in parallel with the internal pulldown resistor to reduce the discharge time. OUTA, OUTB can source greater than 10 mA.

PSA, VPSB

Rev. 0 | Page 22 of 40

CLPA,

CLPB

1.2kΩ

400Ω

COMR

Figure 56. OUTA, OUTB Interface Simplified Schematic

OUTA, OUTB

06198-049

ADL5519

www.BDTIC.com/ADI

DIFFERENCE OUTPUT—OUTP, OUTN

The ADL5519 incorporates two operational amplifiers with rail-torail output capability to provide a channel difference output.

As in the case of the output drivers for OUTA, OUTB, the output stages have the capability of driving greater than 10 mA. OUTA and OUTB are internally connected through 1 kΩ resistors to the inputs of each op amp. The VLVL pin is connected to the positive terminal of both op amps through 1 kΩ resistors to provide level shifting. The negative feedback terminal is also made available through a 1 kΩ resistor. The input impedance of VLVL is 1 kΩ, and the input impedance of FBKA, FBKB is 1 kΩ. See Figure 57 for the connections of these pins.

PSR

LVL

1kΩ

OUTA

OUTB

OUTA

Figure 57. OUTP, OUTN Interface Simplified Schematic

If OUTP is connected to FBKA, OUTP is given as

OUTP = OUTA − OUTB + VLVL (3)

If OUTN is connected to FBKB, OUTN is given as

OUTN = OUTB − OUTA + VLVL (4)

OUTA OUTB

Figure 58. Op Amp Connections (All Resistors Are 1 kΩ ± 20%)

1kΩ

FBKA COMR

1kΩ

FBKB COMR

1kΩ

OUTP

VPSRVLVL

OUTN

06198-050

FBKA

OUTP

OUTN

FBKB

06198-051

DESCRIPTION OF CHARACTERIZATION

The general hardware configuration used for most of the ADL5519 characterization is shown in Figure 59. The signal sources used in this example are the E8251A from Agilent Technologies. The INHA, INHB input pins are driven by Agilent signal sources, and the output voltages are measured using a voltmeter.

SIGNAL

SOURCE

SIGNAL

SOURCE

–3dB

INA

ADL5519

CHARACTERIZATI ON

BOARD

INB

COMPUTER

CONTROLL ER

Figure 59. General Characterization Configuration

OUTA OUTB OUTP OUTN

VREF

TEMP

AGILENT

34970A METER/

SWITCHING

6198-052

BASIS FOR ERROR CALCULATIONS

The input power and output voltage are used to calculate the slope and intercept values. The slope and intercept are calculated using linear regression over the input range from −40 dBm to

−10 dBm. The slope and intercept terms are used to generate an

ideal line. The error is the difference in measured output voltage compared to the ideal output line. This is a measure of the linearity of the device. Refer to the Device Calibration section for more information on calculating slope, intercept, and error.

Error from the linear response to the CW waveform is not a measure of absolute accuracy because it is calculated using the slope and intercept of each device. However, error verifies the linearity and the effects of modulation on device response. Similarly, at temperature extremes, error represents the output voltage variations from the 25°C ideal line performance. Data presented in the graphs is the typical error distribution observed during characterization of the ADL5519.

Pulse response of the ADL5519 is 6 ns/8 ns rise/fall times. For the fastest response time, the capacitance on OUTA, OUTB should be kept to a minimum. Any capacitance on the output pins should be counterbalanced with an equal capacitance on the CLPA, CLPB pins to prevent ringing on the output.

In this configuration, all four measurements, OUTA, OUTB, OUTP, and OUTN, are available simultaneously. A differential output can be taken from OUTP − OUTN, and VLVL can be used to adjust the common-mode level for an ADC connection. This is convenient not only for driving a differential ADC but also for removing any temperature variation on VLVL.

Rev. 0 | Page 23 of 40

ADL5519

www.BDTIC.com/ADI

DEVICE CALIBRATION

The measured transfer function of the ADL5519 at 2.2 GHz is shown in Figure 60. The figure shows plots of both output voltage

t power and calculated error vs. input power. As the input

vs. inpu power varies from −60 dBm to −5 dBm, the output voltage varies from 1.7 V to about 0.5 V.

2.00

1.75

1.50

1.25

OUT1

1.00

0.75

OUT2

OUTPUT VOLTAGE (V)

0.50

0.25

–60 –50 –40 –30 –20 0 10

Figure 60. Transfer Function at 2.2 GHz with Calibration Points

PIN (dBm)

IN1

–10

IN2

Because slope and intercept vary from device to device, boardlevel calibration must be performed to achieve the highest accuracy. The equation for output voltage can be written as

= Slope × (PIN − Intercept) (6)

OUT

where:

Slop

input power, P

e change in output voltage divided by the change in

e is t

, expressed in decibels (dB).

Intercept is the calculated power at which the output voltage would be 0 V. Note that an output voltage of 0 V can never be achieved.

In general, calibration is performed by applying two known signal leve

ls to the ADL5519 input and measuring the corresponding output voltages. The calibration points are generally chosen to be within the linear-in-dB operating range of the device (see the

Specifications section for more details).

Calculation of the slope and intercept is accomplished using the

wing equations:

follo

− V

)/(P

− P

Slope = (V

OUT1

Intercept = P

IN1

− (V

OUT2

IN1

/Slope) (8)

OUT1

) (7)

IN2

Once slope and intercept are calculated, an equation can be wri

tten that calculates the input power based on the output

voltage of the detector.

(Unknown) = (V

OUT1(MEASURED)

/Slope) + Intercept (9)

The log conformance error of the calculated power is given by

Error (dB) = (V

OUT(MEASURED)

− V

OUT(IDEAL)

)/Slope (10)

Figure 60 includes a plot of the error at 25°C, the temperature

ich the log amp is calibrated. Note that the error is not 0 dB

at wh over the full dynamic range. This is because the log amp does

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

not perfectly follow the ideal V its operating region. The error at the calibration points of −35 dBm and −11 dBm is equal to 0 dB, by definition.

Figure 60 also shows error plots for the output voltage at

−40°C and +85°C. Th

ese error plots are calculated using the slope and intercept at 25°C. This is consistent with calibration in a mass-production environment, where calibration over temperature is not practical.

ADJUSTING ACCURACY THROUGH CHOICE OF CALIBRATION POINTS

In some applications, very high accuracy is required at one power level or over a reduced input range. For example, in a wireless transmitter, the accuracy of the high power amplifier

ERROR (dB)

06198-053

(HPA) is most critical at or close to full power. In applications like AGC control loops, good linearity and

temp

erature performance are necessary over a large input power range. The temperature crossover point (the power level at which there is no drift in performance from −40°C to −80°C) can be shifted from high power levels to midpower levels using the method shown in the

tion. This shift equalizes the temperature performance over

sec

Temperature Compensation Adjustment

the complete power range. The linearity of the transfer function can be equalized by changing the calibration points.

Figure 61 demonstrates this equalization by changing the calibra

tion points used in Figure 60 to −46 dBm and −22 dBm. This

adju

stment of the calibration points changes the linearity to greater than ±0.25 dB over a 50 dB dynamic range at the expense of a slight decrease in linearity at power levels between −40 dBm and −25 dBm.

Calibration points should be chosen to suit the application at hand. In ge

neral, however, do not choose calibration points in the

nonlinear portion of the log amp transfer function (greater than

−10 dBm or less than −40 dBm, in this example).

2.00

1.75

1.50

OUT1

1.25

1.00

OUT2

0.75

OUTPUT VOLTAGE (V)

0.50

0.25

–60 –50 –40 –30 –20 0 10

IN1

Figure 61. Dynamic Range Extension by Choosing C

Are Close to the End of the Linear Range, 2.14 GHz

vs. PIN equation, even within

OUT

PIN (dBm)

–10

IN2

alibration Points That

2.0

1.5

1.0

0.5

–0.5

–1.0

–1.5

–2.0

ERROR (dB)

06198-055

Rev. 0 | Page 24 of 40

ADL5519

www.BDTIC.com/ADI

Another way of presenting the error function of a log amp detector is shown in Figure 62. In this example, the decibel (dB) error at hot and cold

temperatures is calculated with respect to the output voltage at ambient. This is a key difference when compared to the previous plots, in which all errors have been calculated with respect to the ideal transfer function at ambient.

2.00

1.75

1.50

2.0

1.5

1.0

Compensating the device for temperature drift by using ADJA,

B allows for great flexibility. To determine the optimal adjust

ADJ voltage, sweep ADJA, ADJB at ambient and at the desired temperature extremes for a couple of power levels while monitoring the output voltage. The point of intersection determines the best adjust voltage. Some additional minor tweaking may be required to achieve the highest level of temperature stability. With appropriate values, a temperature drift error of typically ±0.5 dB over the entire rated temperature range can be achieved.

1.25

1.00

0.75

OUTPUT VOLTAGE (V)

0.50

0.25

–60 –50 –40 –30 –20 –10 0 10

Figure 62. Error vs. Temperature with Respect to Output

2.14 GHz (Removes Transfer Function Nonlinearities at 25°C)

PIN (dBm)

0.5

–0.5

–1.0

–1.5

–2.0

Voltage at 25°C,

With this alternative technique, the error at ambient becomes, by definition, equal to 0 (see Figure 62). This value would be valid i

f the device transfer function perfectly followed the ideal

of the V

= Slope × (PIN − Intercept) equation.

OUT

However, because an rms amp, in practice, never perfectly follows this e

quation (especially outside of its linear operating range), this plot tends to artificially improve linearity and extend the dynamic range, unless enough calibration points are taken to remove the error.

Figure 62 is a useful tool for estimating temperature drift at

ticular power level with respect to the (nonideal) output

a par voltage at ambient.

Table 4. Recommended ADJA, ADJB Voltage Levels

Frequency Recommended ADJA, ADJB Voltage (V)

ERROR (dB)

100 MHz 0.65, 0.7 900 MHz 0.6, 0.65

1.9 GHz 0.5, 0.55

2.2 GHz 0.48, 0.6

3.6 GHz 0.35, 0.42

5.8 GHz 0.58, 0.7

06198-056

8 GHz 0.72, 0.82

Proprietary techniques are used to compensate for the temperature drift. The absolute value of compensation varies with frequency and circuit board material.

ADJA, ADJB are high impedance pins. The applied ADJA, ADJB

s can be supplied from VREF through a resistor divider.

voltage Figure 63 shows a simplified schematic representation of the

, ADJB interface.

ADJA

REF

COMP

TADJ

ADL5519

ADJA, ADJB

TEMPERATURE COMPENSATION ADJUSTMENT

The ADL5519 temperature performance has been optimized to ensure that the output voltage has minimum temperature drift at −10 dBm input power. The applied voltage for the ADJA and ADJB pins for some specified frequencies is listed in

ver, not all frequencies are represented in Table 4, and

Howe exper

imentation may be required.

Table 4.

Rev. 0 | Page 25 of 40

Figure 63.

COMR

ADJA, ADJB Interface Simplified Schematic

06198-057

ADL5519

www.BDTIC.com/ADI

ALTERING THE SLOPE

As discussed in the Setpoint Interface—VSTA, VSTB section, the slope can readily be increased by scaling the amount of output voltage at OUTA, OUTB that is fed back to the setpoint interface, VSTA, VSTB. When the full signal from OUTA, OUTB is applied to VSTA, VSTB, the slope has a nominal value of

−22 mV/dB. This value can be increased by including a voltage divider between the OUTA, OUTB and VSTA, VSTB pins, as shown in Figure 64.

ADL5519

OUTA, OUTB

VSTA, VSTB

Figure 64. External Network to Raise Slope

OUT

06198-058

The approximate input resistance for VSTA, VSTB is 40 kΩ. Scaling resistor values should be carefully selected to minimize errors. Keep in mind that these resistors also load the output pins and reduce the load-driving capabilities.

Equation 11 can be used to calculate the resistor values.

⎛

R2'R1 (11)

= 1

⎜ ⎝

⎞

−

⎟

−

⎠

where:

is the desired slope, expressed in millivolts/decibels (mV/dB).

R2' is the value of R2 in parallel with 40 kΩ.

For example, using R1 = 1.65 kΩ and R2 = 1.69 kΩ (R2' = 1.62 kΩ), the nominal slope is increased to −44 mV/dB.

When the slope is increased, the loop capacitor, CLPA, CLPB, may need to be raised to ensure stability and to preserve a chosen averaging time. The slope can be lowered by placing a voltage divider after the output pin, following standard practices.

CHANNEL ISOLATION

Isolation must be considered when using both channels of the ADL5519 at the same time. The two isolation requirements that should be considered are the isolation from one RF channel input to the other RF channel input and the isolation from one RF channel input to the other channel output. When using both channels of the ADL5519, care should be taken in the layout to isolate the RF inputs, INHA and INHB, from each other. Coupling on the PC board affects both types of isolation.

In most applications, the designer has the ability to adjust the power going into the ADL5519 through the use of temperaturestable couplers and accurate temperature-stable attenuators of different values. When isolation is a concern, it is useful to adjust the input power so the lowest expected detectable power is not far from the lowest detectable power of the ADL5519 at the frequency of operation.

The lowest detectable power point of the ADL5519 has little variation from part to part. This equalizes the signals on both channels at their lowest possible power level, which reduces the overall isolation requirements and possibly adds attenuators to the RF inputs of the device, reducing the RF channel input isolation requirements.

Measuring the RF channel input to the other RF channel input isolation is straightforward and is done by measuring the loss on a network analyzer from one input to the other input. The outcome is shown in the Specifications section of the data sheet. Note that adding an attenuator in series with the RF signal increases the channel input-to-input isolation by the value of the attenuator.

The isolation between one RF channel input and the other channel output is a little more complicated. The easiest approach (which was used in this datasheet) to measuring this isolation is to have one channel set to the lowest power level it is expected to have on its input (approximately −50 dBm in this data sheet) and then increasing the power level on the other channel input until the output of the low power channel changes by 22 mV. Because

−50 dBm is in the linear region of the detector, 22 mV equates to a 1 dB change in the output.

If the inputs to both RF channels are at the same frequency, the isolation also depends on the phase shift between the RF signals put into the ADL5519. This relationship can be demonstrated by placing a high power signal on one RF channel input and a low power signal slightly offset in frequency to the other RF channel.

If the output of the low power channel is observed with an oscilloscope, it has a ripple that looks similar to a full-wave rectified sine wave with a frequency equal to the frequency difference between the two channels, that is, a beat tone. The magnitude of the ripple reflects the isolation at a specific phase offset (note that two signals of slightly different frequencies act like two signals with a constantly changing phase), and the frequency of that ripple is directly related to the frequency offset.

The data shown in the Specifications section assumes worst-case amplitude and phase offset. If the RF signals on Channel A and Channel B are at significantly different frequencies, the input-tooutput isolation increases, depending on the capacitors placed on CLPA, CLPB and the frequency offset of the two signals, due to the response roll-off within the ADL5519.

Rev. 0 | Page 26 of 40

ADL5519

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OUTPUT FILTERING PACKAGE CONSIDERATIONS

Accurate power detection for signals with RF bursts is achieved when the ADL5519 is able to respond quickly to the change in RF power. For applications in which maximum video bandwidth and, consequently, fast rise time are desired, it is essential that the CLPA, CLPB pins have very little capacitance on them (some capacitance reduces the ringing).

The nominal output video bandwidth of 10 MHz can be reduced

nnecting a ground-referenced capacitor (C

by co

) to the CLPA,

FLT

CLPB pins, as shown in Figure 65. This is generally done to

uce output ripple (at twice the input frequency for a

red symmetric input waveform, such as a sinusoidal signal).

3.5pF

×Ω×π

ADL5519

BandwidthVideo

OUTA, OUTB

CLPA, CLPB

FLT

−

6198-059

(12)

pF5.3

LOGA,

LOGB

1.5kΩ

Figure 65. Lowering the Post Demodulation Bandwidth

is selected using the following equation:

FLT

()

k5.1

The video bandwidth should typically be set to a frequency less than

or equal to approximately 1/10 the minimum input frequency. There are no problems with putting large capacitor values on the CLPA, CLPB pins. These large capacitor values ensure that the output ripple of the demodulated log output, which is at twice the input frequency, is well filtered. Signals with modulation may need additional filtering (a larger C

capacitance) to

FLT

remove modulation bleedthrough.

The ADL5519 uses a compact, 32-lead LFCSP. A large exposed paddle on the bottom of the device provides both a thermal benefit and a low inductance path to ground for the circuit. To make proper use of this packaging feature, the PCB RF/dc common-ground reference needs to make contact with the paddle with as many vias as possible to lower inductance and thermal impedance.

OPERATION ABOVE 8 GHz

The ADL5519 is specified for operation up to 8 GHz, but it provides useful measurement accuracy over a reduced dynamic range of up to 10 GHz. Figure 66 shows the performance of the ADL5519 o high frequency performance is achieved using the configuration shown in Figure 53. The dynamic range shown is reduced from the typical de measurement range with less than 3 dB of linearity error.

Implementing an impedance match for frequencies greater than 8 GHz can improve the sensitivity of the ADL5519 and its measurement range.

OUTPUT VOLTAGE (V)

Figure 66. V

ver temperature for a input frequency of 10 GHz. This

vice performance, but the ADL5519 can provide 30 dB of

2.00

1.75

1.50

1.25

1.00

0.75

0.50

0.25

–40 –35 –30 –25 –20 –15 –10 –5 0

and Log Conformance vs. Input Amplitude at 10 GHz,

OUT

Over Temperature, ADJA, ADJB = 1.8 V, 1.8 V

PIN (dBm)

4.0

3.0

2.0

1.0

–1.0

–2.0

–3.0

–4.0

ERROR (dB)

06198-169

Rev. 0 | Page 27 of 40

ADL5519

www.BDTIC.com/ADI

APPLICATIONS INFORMATION

MEASUREMENT MODE

The ADL5519 is placed in measurement mode by connecting OUTA, OUTB to VSTA, VSTB, respectively. The part has an offset voltage, a negative slope, and a V

OUTA, VOUTB

cept at the high end of its input signal range. The output voltage vs. input signal voltage of the ADL5519 is

-in-dB over a multidecade range. The equation for this

linear function is of the following form:

OUT

x × V

= x × V

× 20 × log10(VIN/V

SLOPE/dB

SLOPE/DEC

× log10(VIN/V

INTERCEPT

where:

x is the fe V V

the V

edback factor in V

is nominally −440 mV/decade or −22 mV/dB.

SLOPE/DEC

is the x-axis intercept of the linear-in-dB portion of

INTERCEPT

vs. VIN curve.

OUT

is 2 dBV for a sinusoidal input signal.

INTERCEPT

An offset voltage, V

OFFSET

= V

SET

OUT

, of 0.45 V is internally added to the detector signal so that the minimum value for V x × V

. If x = 1, the minimum V

OFFSET

The slope is very stable vs. process and temperature variation. When

Base-10 logarithms are used, V

volts/decade. A decade corresponds to 20 dB; V

SLOPE/dB

represents the slope in V/dB. B

V As noted in Equation 13 and Equation 14, the V

a negative slope. This is also the correct slope polarity to control the gain of many VGAs in a negative feedback configuration. Because both the slope and intercept vary slightly with frequency, see the Specifications section for application-specific values for

pe and intercept.

slo Although demodulating log amps respond to input signal

tage and not input signal power, it is customary to discuss

vol the amplitude of high frequency signals in terms of power. In this case, the characteristic impedance of the system, Z be known to convert voltages to their corresponding power levels. The following equations are used to perform this conversion:

P (dBm) = 10 × log P (dBV) = 20 × log P (dBm) = P (dBV) − 10 × log

For example, P

, for a sinusoidal input signal expressed

INTERCEPT

/(Z0 × 1 mW)) (15)

10(Vrms

/1 V

10(Vrms

rms

10(Z0

in terms of dBm (decibels referred to 1 mW), in a 50 Ω system is

P P

2 dBV − 10 × log

(dBm) =

INTERCEPT

(dBV) − 10 × log10(Z0 × 1 mW/1 V

INTERCEPT

(50 × 10−3) = 15 dBm

measurement inter-

) = (13)

INTERCEPT

) (14)

/x.

OUT

value is 0.45 V.

OUT

represents the

SLOPE/DEC

/20 =

SLOPE/DEC

voltage has

OUT

, must

) (16)

rms

) =

rms

) (17)

× 1 mW/1 V

For a square wave input signal in a 200 Ω system

INTERCEPT

(dBm) =

[(200 Ω × 1 mW/1V

)] = +6 dBm

rms

−1 dBV − 10 × log

More information about the intercept variation dependence upon

form can be found in the AD8313 and AD8307 data sheets.

wave As the input signals to Channel A and Channel B are swept over

ir nominal input dynamic range of −5 dBm to −55 dBm, the

the output swings from 0.5 V to 1.6 V. The voltages of OUTA, OUTB are also internally applied to a difference amplifier with a gain of 1. When the input power is swept, OUTP swings from approximately 0.5 V to 1.75 V, and OUTN swings from 1.75 V to 0.5 V. The VLVL pin sets the common-mode voltage for OUTP, OUTN. An output common-mode voltage of ≤1.15 V can be set using a resistor divider between the VREF and VLVL pins. Measurement of large differences between INHA, INHB can be affected by on-chip signal leakage.

CONTROLLER MODE

In addition to being a measurement device, the ADL5519 can also be configured to set and control signal levels. Each of the two log detectors can be separately configured to set and control the output power level of a VGA or variable voltage attenuator (VVA). See the Controller Mode section of the AD8317 datasheet for more

ation on running a single channel in controller mode.

inform Alternatively, the two log detectors can be configured to measure

trol the gain of an amplifier or signal chain. The channel

and con difference outputs can be used to control a feedback loop to the ADL5519 RF inputs. A capacitor connected between FBKA and OUTP forms an integrator, keeping in mind that the on-chip 1 kΩ feedback resistor forms a 0. (The value of the on-chip resistors can vary as much as ±20% with manufacturing process variation.) If Channel A is driven and Channel B has a feedback loop from OUTP through a VGA, OUTP integrates to a voltage value such that

OUTB = (OUTA +

e output value from OUTN may or may not be useful. It is

T give

n by

OUTN = 0 V (19) for VLVL < OUTA/3. Otherwise,

OUTN = (3 × VLVL − OUTA)/2 (20)

VLVL)/2 (18)

Rev. 0 | Page 28 of 40

ADL5519

www.BDTIC.com/ADI

If VLVL is connected to the OUTA pin, OUTB is forced to equal OUTA through the feedback loop. This flexibility provides the capability to measure one channel operating at a given power level and frequency while forcing the other channel to a desired power level at another frequency. The voltages applied to the ADJA, ADJB pins should be selected carefully to minimize temperature drift of the output voltage. The temperature drift is the statistical sum of the drift from Channel A and Channel B. As stated previously, VLVL can be used to force the slaved channel to operate at a different power from the other channel.

If the two channels are forced to operate at different power levels, som

e static offset occurs due to voltage drops across metal wiring

in the IC.

If an inversion is necessary in the feedback loop, OUTN can be

used as

the integrator by placing a capacitor between OUTN,

OUTP. This changes the output equation for OUTB and OUTP to

OUTB = 2 × OUT

For VLVL < OUTA/2,

OUTN = 0 V (22)

Otherwise,

OUTN = 2 × VLVL − OUTA (23)

uation 18 to Equation 23 are valid when Channel A is driven

Channel B is slaved through a feedback loop. When Channel B

and

is driven and Channel A is slaved, these equations can be altered

by changing OUTB to OUTA and OUTN to OUTP.

A − VLVL (21)

Rev. 0 | Page 29 of 40

ADL5519

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AUTOMATIC GAIN CONTROL

Figure 67 shows how the ADL5519 can be connected to provide automatic gain control to an amplifier or signal chain. Additional pins are omitted for clarity. In this configuration, both detectors are connected in measurement mode with appropriate filtering being used on CLPA, CLPB to provide adequate filtering of the demodulated log output. OUTA, however, is also connected to the VLVL pin of the on-board difference amplifier. In addition, the OUTP output of the difference amplifier drives a variable gain element (either VVA or VGA) and is connected back to the FBKA input via a capacitor so that it is operating as an integrator.

Assume that OUTA is much bigger than OUTB. Because OUTA

drives VLVL, this voltage is also present on the noninverting

also input of the op amp driving OUTP. This results in a current flow from OUTP through the integrating capacitor into the FBKA input. This results in the voltage on OUTP increasing. If the gain control transfer function of the VGA/VVA is positive, this increases the gain, which in turn increases the input signal to INHA. The output voltage on the integrator continues to increase until the power on the two input channels is equal, resulting in a signal chain gain of unity.

If a gain other than 0 dB is required, an attenuator can be used in one of the RF paths, as shown in Figure 67. Alternatively,

er splitters or directional couplers of different coupling

pow factors can be used. Another convenient option is to apply a voltage on VLVL other than OUTA. Refer to Equation 18 and

Controller Mode section for more detail.

the If the VGA/VVA has a negative gain control sense, the OUTN

out

put of the difference amplifier can be used with the integrating capacitor tied back to FBKB. Alternatively, the inputs could be swapped.

The choice of the integrating capacitor affects the response time of t

he AGC loop. Small values give a faster response time but may result in instability, whereas larger values reduce the response time. Capacitors that are too large can also cause oscillations due to the capacitive drive capability of the op amp. In automatic gain control, the capacitors on CLPA and CLPB, which perform the filtering of the demodulated log output, must still be used and also affect loop response time.

Rev. 0 | Page 30 of 40

ADL5519

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DIRECTIONAL

POWER SPLITTER

VGA/VVA

CLPA

ADL5519

DIRECTIONAL

POWER SPLITTER

VSTA

OUTA

FBKA

OUTP

OUTN

FBKB

OUTB

VSTB

INT

DIFF OUT +

ATTE NUATO R

6198-063

50Ω

0.1µF

INHA

INLA

INLB

INHB

CHANNEL A

LOG DETECTOR

CHANNEL B

LOG DETECTOR

VLVL

CLPB

Figure 67. Operation in Controller Mode for Automatic Gain Control

Rev. 0 | Page 31 of 40

ADL5519

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GAIN-STABLE TRANSMITTER/RECEIVER

There are many applications for a transmitter or receiver with a highly accurate temperature-stable gain. For example, a multicarrier, base station high power amplifier (HPA) using digital predistortion can have a power detector and an auxiliary receiver. The power detector and all parts associated with it can be removed if the auxiliary receiver has a highly accurate temperature-stable gain. With a set gain receiver, the ADC on the auxiliary receiver can determine not only the overall power being transmitted but also the power in each carrier for a multicarrier HPA. Without the use of a detector, the auxiliary receiver is very difficult to calibrate accurately over temperature due to the part-to-part variation of the components in the auxiliary receiver.

In controller mode, the ADL5519 can be used to hold the receiver gain constant over a broad input power/temperature range. In this application, the difference outputs are used to hold the receiver gain constant. Figure 69 shows an example of how this can be done.

The RF input is connected to INHB, using a 19 dB coupler, and the down-converted output from the signal chain is connected to INHA, using a 19 dB coupler. A 100 pF capacitor is connected between FBKA and OUTP, forming an integrator. OUTA is connected to VLVL, forcing OUTP to adjust the VGA so that OUTB is equal to OUTA. The circuit gain is set by the difference in the coupling values of the input and output couplers and the differences in path losses to the detector. Because they are operating at different frequencies, the appropriate voltages on the ADJA, ADJB pins must be supplied. ADJA is set to 0.6 V and ADJB is set to 0.65 V to set the −40 center of the input power range. Using the suggested ADJA value for 80 MHz would put the crossover point at a higher power level.

C/+85oC crossover point toward the

Figure 68 shows the results of the circuit in Figure 69. The input power is swept from −47 dBm to +8 dBm. The output power is measured, and the gain is calculated at +25°C, −40°C and +85°C. With equal valued couplers used on the input and output, the expected gain is about 0 dB. Due to path loss differences and differences due to using two separate frequencies, the average gain is about 2.5 dB. In this configuration, approximately 50 dB of control range with 0.2 dB drift over temperature is obtained. For an auxiliary receiver, less than 5 dB of variation is expected over temperature. If the power levels are chosen to coincide with the temperature crossover point, approximately 0.1 dB of temperature variation can be expected. Most of the gain change over input power level is caused by performance differences at different frequencies.

4.0

3.5

3.0

2.5

2.0

GAIN (dB)

1.5

1.0

0.5

–50 –40 –30 –20 –10 0 10

Figure 68. Performance of Gain-Stable Receiver

PIN (dBm)

GAIN +85°C GAIN +25°C GAIN –40°C

06198-171

Rev. 0 | Page 32 of 40

ADL5519

www.BDTIC.com/ADI

REF

C16

0.1UF

RFIN

900MHz

0.65V

C11

100PF

0Ω 0Ω

C10

0.1 UF

454Ω

19dB COUPLING

R30

52.3

MODE SEL 0V TO 1. 2V

47NF

VPSB

ADJB

VREF

VLVL

CLPB

VSTB

ADL5330

INHB

101911

47NF

INLB

EXPOSED PADDLE

OUTB

FBKB

AD8342

820MHZ

POWE R DOWN

COMR

ADL5519

OUTN

0Ω 0Ω

90MHz

LPF

0.1 UF

R31

52.3

100PF

INHA

47NF

28293132

2730

FBKA

INLA

VPSA

ADJA

VPSR

TEMP

CLPA

VSTA

OUTA

151412 13

169

PWDN

OUTP

IFOUT 80MHz

454Ω

19dB COUPLI NG

C7 100PF

0.6V

C15

0.1UF

C12

0.1UF

TEMPERATURE

SENSOR OUT

100 PF

B CHANNEL OUT

DIFF OUT–

06198-172

Figure 69. Gain-Stable Receiver Circuit

Rev. 0 | Page 33 of 40

ADL5519

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MEASURING VSWR

Measurement of reflected power in wireless transmitters is a critical auxiliary function that is often overlooked. The power reflected back from an antenna is specified using either the voltage standing wave ratio (VSWR) or the reflection coefficient (also referred to as the return loss). Poor VSWR can cause shadowing in a TV broadcast system because the signal reflected off the antenna reflects again off the power amplifier and is then rebroadcast. In wireless communications systems, shadowing produces multipathlike phenomena. Poor VSWR can degrade transmission quality; the catastrophic VSWR that results from damage to a co-axial cable or to an antenna can, at its worst, destroy the transmitter.

The ADL5519 delivers an output voltage proportional to the log of the input signal over a large dynamic range. A log-responding device offers a key advantage in VSWR measurement applications. To compute gain or reflection loss, the ratio of the two signal powers (either OUTPUT/INPUT or REVERSE/FORWARD) must be calculated. An analog divider must be used to perform this calculation with a linear-responding diode detector, but only simple subtraction is required when using a log-responding detector (because log(A/B) = log(A) − log(B)).

A dual RF detector has an additional advantage compared to a discrete implementation. There is a natural tendency for two devices (RF detectors, in this case) to behave similarly when they are fabricated on a single piece of silicon, with both devices having similar temperature drift characteristics, for example. At the summing node, this drift cancels to yield a result that is more temperature stable.

In Figure 71, two directional couplers are used, one to measure forward power and one to measure reverse power. Additional attenuation is required before applying these signals to the detectors. The ADL5519 dual detector has a measurement range of 50 dB in each detector. Care must be taken in setting the attenuation levels so the reflection coefficient can be measured over the desired output power range.

The level planning used in this example is graphically depicted in Figure 70. In this example, the expected output power range from the HPA is 30 dB, from 20 dBm to 50 dBm. Over this power range, the ADL5519 can accurately measure reflection coefficients from 0 dB (short, open, or load) to −20 dB.

Each ADL5519 detector has a nominal input range from −5 dBm to −55 dBm. In this example, the maximum forward power of +50 dBm is attenuated to −10 dBm at the detector input (this attenuation is achieved through the combined coupling factor of the directional coupler and the subsequent attenuation). This puts the maximum power at the detector comfortably within its linear operating range. Also, when the HPA is transmitting at its lowest power level of +20 dBm, the detector input power is

−40 dBm, which is still within its input operating range.

50dBm 40dBm 30dBm 20dBm 10dBm

–10dBm –20dBm –30dBm –40dBm –50dBm –60dBm

0dBm

FORWARD

POWER

RANGE

55dB

ATTENUATION

DECTOR A/B

60dB

ATTENUATION

POWER

AT INPUT A

Figure 70. ADL5519 VSWR Level Planning

INPUT RANG E

REVERSE

POWER RANGE

POWR

AT INPUT B

6198-075

Careful level planning should be used to match the input power levels in a dual detector and to place these power levels within the linear operating range of the detectors. The power from the reverse path is attenuated by 55 dB, which means that the detector is capable of measuring reflected power up to 0 dB. In most applications, the system is designed to shut down when the reflection coefficient degrades below a certain minimum (for example, 10 dB). Full reflection is allowed when using the ADL5519 because of its large dynamic range. In the case of very little reflection (a return loss of 20 dB) and the HPA is transmitting +20 dBm, the reverse path detector has an input power of −55 dBm.

The application circuit in Figure 71 provides a direct reading of return loss, forward power, and reverse power. If the forward and reverse phase difference (phase angle) is needed to optimize the power delivered to the antenna, the AD8302 should be used. It provides one output that represents the return loss and one output that represents the phase difference between the two signals. However, the AD8302 does not provide the absolute forward or reverse power.

Rev. 0 | Page 34 of 40

ADL5519

www.BDTIC.com/ADI

HPA

= 20dBm TO 50dB

OUT

20dB20dB

40dB35dB

52.3Ω

= –10dBm TO

–40dBm

52.3Ω

PIN = –5dBm TO

–55dBm

0.1µF

INHA

0.1µF

INHB

Figure 71.

VSTA

BIAS

TEMP

OUTA

FBKA

OUTP

OUTN

FBKB

OUTB

VSTB

RETURN

LOSS

ADL5519

CHANNEL A

LOG DETECTOR

OUTA OUTB

CHANNEL B

LOG DETECTOR

ADL5519 Configuration for Measuring Reflection Coefficients

FORWARD

POWER

ADC

REVERSE

POWER

MICROPROCESSOR/

DSP

06198-074

Rev. 0 | Page 35 of 40

ADL5519

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EVALUATION BOARD

CONFIGURATION OPTIONS

Table 5. Evaluation Board (Rev. A) Configuration Options

Component Description Default Conditions

VPOS, VPSB, VPSR, GND, GND1, GND3

R0A, R0B, R5, R6, R30, R31, C1, C2, C3, C4

R14

R13, R17, R18, R19, R27, R28, R29

R8, R12, R15, R16, R20, R21, R22, R23, C13, C14

R8, R12, R22, R23

R3, R4, R11, R24, R25, R26, C7, C8, C11, C12, C15, C16

R1, R2, R9, R10 Output Interface, Difference.

C9, C10

R7, C6 VLVL Interface.

Supply and Ground Connections. VPOS, VPSB, and VPSR are internally connected.

GND, GND1, and GND3 are internally connected. Input Interface.

The 52.3 Ω resistors in the R30 and R31 positions combine with the ADL5519 internal input impedance to give a broadband input impedance of about 50 Ω. C1, C2, C3, and C4 are dc-blocking capacitors. A reactive impedance match can be implemented by replacing R5, R6, R30, and R31 with an inductor and by replacing C1, R0A and C4, R0B with appropriately valued capacitors.

Temperature Sensor Interface. Tempera R14 can be used as a pull-down resistor.

Temperature Compensation Interface. A voltage source at ADJA, ADJB can be used to optimize the temperature performance for various input frequencies. The pads for R27/R28 or R27/R29 can be used for voltage dividers from the VREF node to set the ADJA, ADJB voltages at different frequencies. The individual log channels can be disabled by installing 0 Ω resistors at R18 and R19.

Output Interface, Measurement Mode. In measurement mode, a portion of the output voltage is fed back to VSTA, VSTB via R8, R12. The magnitude of the slope of the OUTA, OUTB output voltage response can be increased by reducing the portion of V VSTB. The slope can be decreased by implementing a voltage divider by using R20 and R16 or R21 and R15. R20 and R21 can also be used as a back-terminating resistor or as part of a single-pole, low-pass filter.

Output Interface, Controller Mode. In thi controller mode, the ADL5519 can control the gain of an external component. A setpoint voltage is applied to VSTA, VSTB, the value of which corresponds to the desired RF input signal level applied to the corresponding ADL5519 RF input. A sample of the RF output signal from this variable-gain component is selected, typically via a directional coupler, and applied to ADL5519 RF input. The voltage at OUTA, OUTB is applied to the gain control of the variable gain element. A control voltage is applied to VSTA, VSTB. The magnitude of the control voltage can optionally be attenuated via the voltage divider comprising R8, R12 and R22, R23; or a capacitor can be installed in the R22, R23 position to form a low-pass filter along with R8, R12.

Power Supply Decoupling. The nominal supply decoupling consists of a 100 pF filter capacitor placed physically close to the ADL5519 and a 0.1 μF capacitor placed nearer to each power supply input pin.

R9 and R10 can be replaced with a capacitor to form an integrator for constant gain con

Filter Capacitor. The lo lowered by placing a capacitor between CLPA, CLPB and ground. Increasing this capacitor increases the overall rise/fall time of the ADL5519 for pulsed input signals. See the Output Filtering section for more details.

VREF can be used to drive VLVL through a voltage divider formed using R7 and C6.

ture sensor output voltage is available at the test point labeled TEMP.

s mode, the 0 Ω resistors must be removed, leaving R8 and R12 open. In

troller mode

w-pass corner frequency of the circuit that drives OUTA, OUTB can be

OUTA

, V

that is fed back to VSTA,

OUTB

Not applicable

R30, R31 = 52.3 Ω (Size 0402), C1 to C4 = 47 nF (Size 0402)

R0A, R0B = 0 Ω R5, R6 = open

R14 = open (Size 0603)

R13, R17, R18, R19, R28, R29 = open (Size 0603)

R27 = 0 Ω (Size 0603)

R8, R12, R20, R21 = 0 Ω (Size 0603) R15, R16, R22, R23 = open (Size 0603) C13, C14 = open (Size 0603)

R8, R12, R22, R23 = open (Size 0603)

R3, R4, R11, R24, R25, R26 = 0 Ω (Size 0603) C7, C8, C11 = 100 pF (Size 0603) C12, C15, C16 = 0.1 μF (Size 0603)

R1, R2, R9, R10 = 0 Ω (Size 0603)

C9, C10 = 1000 pF (Size 0603)

R7 = open (Size 0603) C6 = open (Size 0603)

Rev. 0 | Page 36 of 40

ADL5519

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EVALUATION BOARD SCHEMATIC AND ARTWORK

INHA

INHB

VPSB

VPSR

VPSA

RED

TESTLOOP

VPSB

R24

RED

TESTLOOP

R25

R0603

RED

TESTLOOP

VPSR

R0603

R26

R0603

VPOS

R0402

INHA

Open

AGNDAGND

R0A

C0402

0 Ohm

C0402

C3C2

AGNDAGND

47NF

PWDN

C0402

47NF

R0B

C0402

0 Ohm

R0402

Open

SMASMT

PWDN

INHB

SMASMT

ADJA

SMASMT

VPSA

ADJA

R0402

R13

Open

C0402

C12

R0402

R31

C0402

47NF

AGND

C0402

47NF

R30

C11

AGND

C0402

100PF 0.1UF

R0402

Open

R18

R0402

52.3

AGND

INHA

INLA

2730 28293132

PWDN

COMR

INLB

INHB

R0402

52.3

AGND

R0402

Open

R19

100PF0.1UF

C0402

TESTLOOP

VPSR

C15

C0402

R0402

C0402

100PF 0.1UF

AGND

RED

TESTLOOP

TEMP

AGND

TEMP

R0603

Open

R14

AGND

VST

SMASMT

VSTA

R23

AGND

C0603

1000PF

R0603

ADJA

VPSA

VPSR

191120

169

VSTA

CLPA

TEMP

OUTA

151412 13

FBKA

R21

R0603

OUTP

ADL5519

32LFCSP5X5

ADJB

VPSB

VREF

VLVL

OUTN

FBKB

OUTB

VSTB

CLPB

R0603

R12

R0603

R10

R0603

R20

BLACK

TESTLOOP

BLACK

AGND

GND2 GND3

TESTLOOP

BLACK

GND1

HTA_CSP5X5_GND

R0603

Open

AGND

Open

C13C14

C0603

R0603

Open

AGND

OUTA

SMASMT

R0603

AGNDAGND AGND

R0603

R16 R15

Open

C0603

Open

SMASMT

OUTP

OUTN

SMASMT

OUTB

06198-068

OUTA

OUTP

OUTN

OUTB

R0402

R11

C16

ADJBADJA

R28

R0603

OPEN

R0603

R27

VREF

R29

R0603

OPEN

VPSB

AGND

C0402

AGND

R0402

Open

R17

ADJB

SMASMT

TESTLOOP

VREF

DJB

Figure 72. Evaluation Board Schematic

Rev. 0 | Page 37 of 40

RED

C0603

1000PF

C10

AGND

R0603

OPEN

0.1 uF

C0603

AGND

VSTB

Open

C0603

AGND

R0603

Open

R22

VREF

VLVL

RED

TESTLOOP

VLVL

SMASMT

VSTB

ADL5519

www.BDTIC.com/ADI

06198-069

Figure 73. Top Side Layout Figure 75. Bottom Side Layout

06198-071

06198-070

Figure 74. Top Side Silkscreen

Rev. 0 | Page 38 of 40

Figure 76. Bottom Side Silkscreen

06198-072

ADL5519

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

INDICATOR

1.00

0.85

0.80

SEATING

PLANE

PIN 1

12° MAX

5.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.25

0.18

4.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

0.60 MAX

0.50

BSC

0.50

0.40

0.30

COPLANARITY

0.08

0.60 MAX

EXPOSED

(BOT TOM VIEW)

3.50 REF

PAD

PIN 1

INDICATOR

2.85

2.70 SQ

2.55

0.20 MIN

COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2

032807-A

Figure 77. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

5 mm × 5 mm Body, Very Thin Quad Lead

(CP-32-8)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

ADL5519ACPZ-R71 −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-8 ADL5519ACPZ-R21 −40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-8 ADL5519ACPZ-WP ADL5519-EVALZ1 Evaluation Board

Z = RoHS Compliant Part.

WP = waffle pack.

1, 2

−40°C to +125°C 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-32-8

Rev. 0 | Page 39 of 40

ADL5519

www.BDTIC.com/ADI

NOTES

Rev. 0 | Page 40 of 40

Datasheet ADL5519 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

THEORY OF OPERATION

USING THE ADL5519

BASIC CONNECTIONS

INPUT SIGNAL COUPLING

TEMPERATURE SENSOR INTERFACE

VREF INTERFACE

POWER-DOWN INTERFACE

SETPOINT INTERFACE—VSTA, VSTB

OUTPUT INTERFACE—OUTA, OUTB

DIFFERENCE OUTPUT—OUTP, OUTN

DESCRIPTION OF CHARACTERIZATION

BASIS FOR ERROR CALCULATIONS

DEVICE CALIBRATION

ADJUSTING ACCURACY THROUGH CHOICE OF CALIBRATION POINTS

TEMPERATURE COMPENSATION ADJUSTMENT

ALTERING THE SLOPE

CHANNEL ISOLATION

OUTPUT FILTERING PACKAGE CONSIDERATIONS

OPERATION ABOVE 8 GHz

APPLICATIONS INFORMATION

MEASUREMENT MODE

CONTROLLER MODE

AUTOMATIC GAIN CONTROL

GAIN-STABLE TRANSMITTER/RECEIVER

MEASURING VSWR

EVALUATION BOARD

CONFIGURATION OPTIONS

EVALUATION BOARD SCHEMATIC AND ARTWORK

OUTLINE DIMENSIONS

ORDERING GUIDE