ANALOG DEVICES ADL5391 Service Manual

DC to 2.0 GHz

FEATURES

Ultrafast symmetric multiplier

Function: V

Unique design ensures absolute XY-symmetry

Identical X and Y amplitude/timing responses
Adjustable gain scaling, α
DC-coupled throughout, 3 dB bandwidth of 2 GHz
Fully differential inputs, may be used single ended
Low noise, high linearity
Accurate, temperature stable gain scaling
Single-supply operation (4.5 V to 5.5 V @ 130 mA)
Low current power-down mode
16-lead LFCSP

APPLICATIONS

Wideband multiplication and summing
High frequency analog modulation
Adaptive antennas (diversity/phased array)
Square-law detectors and true rms detectors
Accurate polynomial function synthesis
DC capable VGA with very fast control

GENERAL DESCRIPTION

The ADL5391 draws on three decades of experience in
advanced analog multiplier products. It provides the same
general mathematical function that has been field proven to
provide an exceptional degree of versatility in function synthesis.

VW = α × (VX × VY)/ 1 V + V

The most significant advance in the ADL5391 is the use of a
new multiplier core architecture, which differs markedly from
the conventional form that has been in use since 1970. The
conventional structure that employs a current mode, translinear
core is fundamentally asymmetric with respect to the X and Y
inputs, leading to relative amplitude and timing misalignments
that are problematic at high frequencies. The new multiplier
core eliminates these misalignments by offering symmetric
signal paths for both X and Y inputs. The Z input allows a signal
to be added directly to the output. This can be used to cancel a
carrier or to apply a static offset voltage.

The fully differential X, Y, and Z input interfaces are operational
over a ±2 V range, and they can be used in single-ended fashion.
The user can apply a common mode at these inputs to vary
from the internally set V

= α × (VX × VY)/1 V + VZ

W

Z

/2 down to ground. If these inputs

POS

Multiplier

ADL5391

FUNCTIONAL BLOCK DIAGRAM

YMNS YPLS GADJ

XPLS

XMNS

ENBL

VMID

COMM VPOS

ADL5391

W = αXY/1V+Z

Figure 1.

are ac-coupled, their nominal voltage will be V
interfaces each present a differential 500 Ω input impedance up to
approximately 700 MHz, decreasing to 50 Ω at 2 GHz. The gain
scaling input, GADJ, can be used for fine adjustment of the gain
scaling constant (α) about unity.

The differential output can swing ±2 V about the V
common-mode and can be taken in a single-ended fashion as
well. The output common mode is designed to interface directly
to the inputs of another ADL5391. Light dc loads can be ground
referenced; however, ac-coupling of the outputs is recommended
for heavy loads.

The ENBL pin allows the ADL5391 to be disabled quickly to a
standby mode. It operates off supply voltages from 4.5 V to

5.5 V while consuming approximately 130 mA.

The ADL5391 is fabricated on Analog Devices proprietary, high
performance, 65 GHz, SOI complementary, SiGe bipolar IC
process. It is available in a 16-lead, Pb-free, LFCSP and operates
over a −40°C to +85°C temperature range. Evaluation boards
are available.

ZMNS

ZPLS

WPLS

WMNS

06059-001

/2. These input

POS

/2

POS

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2006 Analog Devices, Inc. All rights reserved.

ADL5391

TABLE OF CONTENTS

Features .............................................................................................. 1

Typical Perf or m an c e Charac t e r istics ..............................................7

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

REVISION HISTORY

7/06—Revision 0: Initial Version

General Description....................................................................... 10

Basic Theory ............................................................................... 10

Basic Connections...................................................................... 10

Evaluation Board ............................................................................ 13

Outline Dimensions ....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

ADL5391

SPECIFICATIONS

V

= 5 V, TA = 25°C, ZL = 50 Ω differential, ZPLS = ZMNS = open, GADJ = open, unless otherwise noted. Transfer function: W =

POS

XY/1 V + Z, common mode internally set to 2.5 V nominal.

Table 1.

Parameter Conditions Min Typ Max Unit

MULTIPLICAND INPUTS (X, Y) XPLS, XMNS, YPLS, YMNS

Differential Voltage Range Differential, common mode = 2.5 V 2 V p-p
Common-Mode Range For full differential range 0 2.5 V
Input Offset Voltage DC 20 mV

vs. Temperature −40°C to +85°C ±20 mV
Differential Input Impedance f = dc 500 Ω
f = 2 GHz 150 Ω
Fundamental Feedthrough, X or Y

f = 1 GHz −35 dB
Gain X = 50 MHz and 0 dBm, Y = 1 V 0.5 dB
X = 1 GHz and 0 dBm, Y = 1 V −1.33 dB
DC Linearity X to output, Y = 1 V 1 % FS
Scale Factor X = Y = 1 V 1 V/V
CMRR ±1 V p-p, Y = 1 V, f = 50 MHz 42.1 dB

SUMMING INPUT (Z) ZPLS, ZMNS

Differential Voltage Range Common mode from 2.5 V down to COMM 2 V p-p
Common-Mode Range For full differential range 0 2.5 V
Gain From Z to W, f ≤ 10 MHz, 0 dBm, X = Y = 1 V 0.1 dB
Differential Input Impedance f = dc 500 Ω
f = 2 GHz 150 Ω

OUTPUTS (W) WPLS, WMNS

Differential Voltage Range No external common mode ±2 V
Common-Mode Output V
Output Noise Floor X = Y = 1 V dc
f = 1 MHz −133 dBm/Hz
f = 1 GHz −133 dBm/Hz
X = Y = 0
f = 1 MHz −138 dBm/Hz
f = 1 GHz −138 dBm/Hz
Output Noise Voltage Spectral Density X = Y = 0, f = 1 MHz 26.7 nV/√Hz
Output Offset Voltage Z = 0 V differential

vs. Temperature ±19 mV
Differential Output Impedance f = dc 0 Ω
f = 200 MHz 75 Ω
f = 2 GHz 500 Ω

DYNAMIC CHARACTERISTICS

Frequency Range X, Y, Z to W 0 2 GHz
Slew Rate W from −2.0 V to +2.0 V, 150 Ω 8800 V/μs
Settling Time X stepped from −1 V to +1 V, Z = 0 V, 150 Ω 2.1 ns
Second Harmonic Distortion X (Y) = 0 dBm, Y (X) = 1 V, fund = 10 MHz −60 dBc
Fund = 200 MHz −51 dBc
Third Harmonic Distortion X (Y) = 0 dBm, Y (X) = 1 V, fund = 10 MHz −61.5 dBc
Fund = 200 MHz −51.6 dBc

f = 50 MHz, X (Y) = 0 V, Y (X) = 0 dBm, relative to
condition where X (Y) = 1 V

−42 dB

− 2.5 V

POS

19 mV

Rev. 0 | Page 3 of 16

ADL5391

Parameter Conditions Min Typ Max Unit

OIP3

f1= 49 MHz, f = 50 MHz 26.5 dBm
f1 = 999 MHz, f2 = 1 GHz 14 dBm
OIP2 f1 = 49 MHz, f = 50 MHz 45.5 dBm
f1 = 999 MHz, f2 = 1 GHz 28 dBm
Output 1 dB Compression Point X (Y) to W, Y (X) = 1 V, 50 MHz 15.1 dBm
1 GHz 13.2 dBm
Group Delay 200 MHz 0.5 ns
1 GHz 0.7 ns
Differential Gain Error, X/Y f = 3.58 MHz 2.7 %
Differential Phase Error, X/Y f = 3.58 MHz 0.23 Degrees

GAIN TRIMMING (α) GADJ

Nominal Bias Unconnected 1.12 V
Input Range 0 2 V
Gain Adjust Range Input 0 V to 2 V 9.5 dB

REFERENCE VOLTAGE VMID V

Source Current Common-mode for X, Y, Z = 2.5 V 50 mA

POWER AND ENABLE V

Supply Voltage Range 4.5 5.5 V
Total Supply Current Common-mode for X, Y, Z = 2.5 V 135 mA
Disable Current ENBL = 0 V 7.5 mA
Disable Threshold High to Low 1.5 V
Enable Response Time

Disable Response Time

Two-tone IP3 test; X (Y) = 100 mV p-p/tone
(−10 dBm into 50 Ω), Y (X) = 1

, COMM, ENBL

POS

Delay following high-to-low transition until device
meets full specifications

Delay following low-to-high transition until device
produces full attenuation

/2 V

POS

150 ns

50 ns

Rev. 0 | Page 4 of 16

ADL5391

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage V
ENBL 5.5 V
XPLS, XMNS, YPLS, YMNS, ZPLS, ZMNS V
GADJ V
Internal Power Dissipation 800 mW
θJA (With Pad Soldered to Board) 73°C/W
Maximum Junction Temperature 150°C
Operating Temperature Range −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering 60 sec) 300°C

5.5 V

POS

POS

POS

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. 0 | Page 5 of 16