ANALOG DEVICES ADL5382 Service Manual

Quadrature Demodulator

ADL5382

Rev. A

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BIAS

GEN

ADL5382

0°

90°

CMRF CMRF

RFIP RFIN CMRF VPX

CML

VPA

COM

BIAS

VPL

VPB

QHI

QLO

IHI

ILO

LOIP LOIN CML CML COM

23 22 21 20 19

7 8 9 10 11 12

07208-001

Data Sheet

FEATURES

Operating RF and LO frequency: 700 MHz to 2.7 GHz Input IP3

33.5 dBm @ 900 MHz

30.5 dBm @1900 MHz Input IP2: >70 dBm @ 900 MHz Input P1dB: 14.7 dBm @ 900 MHz Noise figure (NF)

14.0 dB @ 900 MHz

15.6 dB @ 1900 MHz Voltage conversion gain: ~4 dB Quadrature demodulation accuracy

Phase accuracy: ~0.2°

Amplitude balance: ~0.05 dB Demodulation bandwidth: ~370 MHz Baseband I/Q drive: 2 V p-p into 200 Ω Single 5 V supply

700 MHz to 2.7 GHz

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

APPLICATIONS

Cellular W-CDMA/CDMA/CDMA2000/GSM Microwave point-to-(multi)point radios Broadband wireless and WiMAX

GENERAL DESCRIPTION

The ADL5382 is a broadband quadrature I-Q demodulator that covers an RF input frequency range from 700 MHz to 2.7 GHz. With a NF = 14 dB, IP1dB = 14.7 dBm, and IIP3 = 33.5 dBm at 900 MHz, the ADL5382 demodulator offers outstanding dynamic range suitable for the demanding infrastructure direct-conversion requirements. The differential RF inputs provide a well-behaved broadband input impedance of 50 Ω and are best driven from a 1:1 balun for optimum performance.

Excellent demodulation accuracy is achieved with amplitude and phase balances ~0.05 dB and ~0.2°, respectively. The demodulated in-phase (I) and quadrature (Q) differential outputs are fully buffered and provide a voltage conversion gain of ~4 dB. The buffered baseband outputs are capable of driving a 2 V p-p differential signal into 200 Ω.

The fully balanced design minimizes effects from second-order distortion. The leakage from the LO port to the RF port is <−65 dBc. Differential dc offsets at the I and Q outputs are typically <10 mV. Both of these factors contribute to the excellent IIP2 specifications which is >60 dBm.

The ADL5382 operates off a single 4.75 V to 5.25 V supply. The supply current is adjustable with an external resistor from the BIAS pin to ground.

The ADL5382 is fabricated using the Analog Devices, Inc., advanced Silicon-Germanium bipolar process and is available in a 24-lead exposed paddle LFCSP.

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

ADL5382 Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Absolute Maximum Ratings ............................................................ 5

ESD Caution .................................................................................. 5

Pin Configuration and Function Descriptions ............................. 6

Typical Performance Characteristics ............................................. 7

Distributions for fRF = 900 MHz ............................................... 10

Distributions for fRF = 1900 MHz ............................................. 11

Distributions for fRF = 2700 MHz ............................................. 12

Circuit Description ......................................................................... 13

LO Interface................................................................................. 13

V-to-I Converter ......................................................................... 13

Mixers........................................................................................... 13

Emitter Follower Buffers ........................................................... 13

Bias Circuit .................................................................................. 13

Applications Information .............................................................. 14

Basic Connections ...................................................................... 14

Power Supply ............................................................................... 14

Local Oscillator (LO) Input ...................................................... 14

RF Input ....................................................................................... 15

Baseband Outputs ...................................................................... 15

Error Vector Magnitude (EVM) Performance ........................... 16

Low IF Image Rejection ............................................................. 17

Example Baseband Interface ..................................................... 17

Characterization Setups ................................................................. 21

Evaluation Board ............................................................................ 23

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

5/12—Rev. 0 to Rev. A

Added θ

Added EPAD Note to Figure 2 ........................................................ 6

Updated Outline Dimensions ....................................................... 27

3/08—Revision 0: Initial Version

= 3°C/W to Table 2......................................................... 5

Rev. A | Page 2 of 28

Data Sheet ADL5382

OPERATING CONDITIONS

Quadrature Phase Error

At 900 MHz

0.2 Degrees

Output Swing

Differential 200 Ω load

V p-p

DYNAMIC PERFORMANCE at RF = 900 MHz

Input P1dB

14.4 dBm

SPECIFICATIONS

VS = 5 V, TA = 25°C, fLO = 900 MHz, fIF = 4.5 MHz, PLO = 0 dBm, BIAS pin open, ZO = 50 Ω, unless otherwise noted. Baseband outputs differentially loaded with 450 Ω. Loss of the balun used to drive the RF port was de-embedded from these measurements.

Table 1.

Parameter Condition Min Typ Max Unit

LO and RF Frequency Range 0.7 2.7 GHz

LO INPUT LOIP, LOIN

Input Return Loss LO driven differentially through a balun at 900 MHz −11 dB LO Input Level −6 0 +6 dBm

I/Q BASEBAND OUTPUTS QHI, QLO, IHI, ILO

Voltage Conversion Gain 450 Ω differential load on I and Q outputs at 900 MHz 3.9 dB 200 Ω differential load on I and Q outputs at 900 MHz 3.0 dB Demodulation Bandwidth 1 V p-p signal, 3 dB bandwidth 370 MHz

I/Q Amplitude Imbalance 0.05 dB Output DC Offset (Differential) 0 dBm LO input at 900 MHz ±5 mV Output Common Mode VPOS − 2.8 V

0.1 dB Gain Flatness 50 MHz

Peak Output Current Each pin 12 mA

POWER SUPPLIES VPA, VPL, VPB, VPX

Voltage 4.75 5.25 V Current BIAS pin open 220 mA

Conversion Gain 3.9 dB Input P1dB 14.7 dBm Second-Order Input Intercept (IIP2) −5 dBm each input tone 73 dBm Third-Order Input Intercept (IIP3) −5 dBm each input tone 33.5 dBm LO to RF RFIN, RFIP terminated in 50 Ω −92 dBm RF to LO LOIN, LOIP terminated in 50 Ω −89 dBc IQ Magnitude Imbalance 0.05 dB IQ Phase Imbalance 0.2 Degrees LO to IQ RFIN, RFIP terminated in 50 Ω −43 dBm Noise Figure 14.0 dB Noise Figure under Blocking Conditions With a −5 dBm interferer 5 MHz away 19.9 dB

DYNAMIC PERFORMANCE at RF = 1900 MHz

Conversion Gain 3.9 dB

Second-Order Input Intercept (IIP2) −5 dBm each input tone 65 dBm Third-Order Input Intercept (IIP3) −5 dBm each input tone 30.5 dBm LO to RF RFIN, RFIP terminated in 50 Ω −71 dBm RF to LO LOIN, LOIP terminated in 50 Ω −78 dBc IQ Magnitude Imbalance 0.05 dB IQ Phase Imbalance 0.2 Degrees LO to IQ RFIN, RFIP terminated in 50 Ω −41 dBm Noise Figure 15.6 dB Noise Figure under Blocking Conditions With a −5 dBm interferer 5 MHz away 20.5 dB

= 4 kΩ 196 mA

BIAS

Rev. A | Page 3 of 28

ADL5382 Data Sheet

Third-Order Input Intercept (IIP3)

−5 dBm each input tone

28.3 dBm

Parameter Condition Min Typ Max Unit

DYNAMIC PERFORMANCE at RF = 2700 MHz RFIP, RFIN

Conversion Gain 3.3 dB Input P1dB 14.5 dBm Second-Order Input Intercept (IIP2) −5 dBm each input tone 52 dBm

LO to RF RFIN, RFIP terminated in 50 Ω, 1xLO appearing at RF port −70 dBm RF to LO LOIN, LOIP terminated in 50 Ω −55 dBc IQ Magnitude Imbalance 0.16 dB IQ Phase Imbalance 0.1 Degrees LO to IQ RFIN, RFIP terminated in 50 Ω, 1xLO appearing at BB port −42 dBm Noise Figure 17.6 dB

Rev. A | Page 4 of 28

Data Sheet ADL5382

Operating Temperature Range

−40°C to +85°C

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage (VPA, VPL, VPB, VPX) 5.5 V LO Input Power 13 dBm (re: 50 Ω) RF Input Power 15 dBm (re: 50 Ω) Internal Maximum Power Dissipation 1230 mW θJA 54°C/W θJC 3°C/W Maximum Junction Temperature 150°C

Storage Temperature Range −65°C to +125°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 5 of 28

ADL5382 Data Sheet

CMRF CMRF RFIP

ADL5382

TOP VIEW

(Not to S cale)

RFIN CMRF VPX

CML

VPA

COM

BIAS

VPL

VPB

QHI

QLO

IHI

ILO

LOIP LOIN CML CML COM

23 22 21 20 19

7 8 9 10 11 12

07208-002

NOTES

1. CONNECT THE E X P OSED PAD TO A LOW IMP E DANCE THERMAL AND ELECTRICAL GROUND PLANE.

1, 4 to 6,

VPA, VPL, VPB, VPX

Supply. Positive supply for LO, IF, biasing, and baseband sections. These pins should be decoupled

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 2. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

17 to 19 2, 7, 10 to 12,

COM, CML, CMRF Ground. Connect to a low impedance ground plane.

to the board ground using appropriate-sized capacitors.

20, 23, 24 3 BIAS Bias Control. A resistor (R

) can be connected between BIAS and COM to reduce the mixer core

BIAS

current. The default setting for this pin is open.

8, 9 LOIP, LOIN Local Oscillator Input. Pins must be ac-coupled. A differential drive through a balun (recommended

balun is the M/A-COM ETC1-1-13) is necessary to achieve optimal performance.

13 to 16 ILO, IHI, QLO, QHI I Channel and Q Channel Mixer Baseband Outputs. These outputs have a 50 Ω differential output

impedance (25 Ω per pin). The bias level on these pins is equal to VPOS − 2.8 V. Each output pair can swing 2 V p-p (differential) into a load of 200 Ω. Output 3 dB bandwidth is 370 MHz.

21, 22 RFIN, RFIP RF Input. A single-ended 50 Ω signal can be applied to the RF inputs through a 1:1 balun (recommended

balun is the M/A-COM ETC1-1-13). Ground-referenced inductors must also be connected to RFIP and RFIN (recommended values = 33 nH).

EP Exposed Paddle. Connect to a low impedance thermal and electrical ground plane.

Rev. A | Page 6 of 28

Data Sheet ADL5382

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

GAIN

INPUT P1d B

07208-003

RF FREQUE NCY ( M Hz )

GAIN (dB) , IP1dB (d Bm)

TA = –40°C T

= +25°C

= +85°C

INPUT IP 3 ( I AND Q CHANNELS)

I CHANNEL Q CHANNEL

INPUT IP2

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-004

RF FREQUE NCY ( M Hz )

IIP3, IIP2 (dBm)

= –40°C

= +25°C

= +85°C

–2.0

–1.5

–1.0

–0.5

0.5

1.0

1.5

2.0

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-005

RF FREQUE NCY ( M Hz )

GAIN MIS M ATCH (dB)

= –40°C

= +25°C

= +85°C

–8

–7

–6

–5

–4

–3

–2

–1

10 100 1000

07208-006

BASEBAND FREQUE NCY ( M Hz )

BASEBAND RESPONS E ( dB)

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-007

RF FREQUE NCY ( M Hz )

NOISE FIGURE (dB)

TA = –40°C T

= +25°C

= +85°C

–4

–3

–2

–1

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-008

RF FREQUE NCY ( M Hz )

QUADRATURE PHASE E RROR (Degrees)

TA = –40°C T

= +25°C

= +85°C

TYPICAL PERFORMANCE CHARACTERISTICS

VS = 5 V, TA = 25°C, LO drive level = 0 dBm, R

= open, RF input balun loss is de-embedded, unless otherwise noted.

BIAS

Figure 3. Conversion Gain and Input IP1 dB Compression Point (IP1dB) vs.

RF Frequency

Figure 4. Input Third-Order Intercept (IIP3) and

Input Second-Order Intercept Point (IIP2) vs. RF Frequency

Figure 6. Normalized IQ Baseband Frequency Response

Figure 7. Noise Figure vs. RF Frequency

Figure 5. IQ Gain Mismatch vs. RF Frequency

Figure 8. IQ Quadrature Phase Error vs. RF Frequency

Rev. A | Page 7 of 28

ADL5382 Data Sheet

–6 –5 –4

–3 –2 –1 0 1 2 3 4 5 6

IIP3, IIP2 (dBm)

GAIN

IIP3

NOISE FIGURE

IP1dB

IIP2, I CHANNEL

IIP2, Q CHANNEL

07208-009

LO LEVEL (dBm)

GAIN (dB), IP1dB (dBm), NOISE FIGURE (dB)

INPUT IP3

NOISE FIGURE

SUPPLY CURRENT

1 10 100

160

170

180

190

200

210

220

230

240

250

SUPPLY CURRENT (mA)

07208-010

BIAS

(kΩ)

IIP3 (d Bm) AND NOISE FI GURE (dB)

= –40°C

= +25°C

= +85°C

–30 –25 –20 –15 –10 –5 0 5

07208-011

RF BLOCKER INPUT POW E R ( dBm)

NOISE FIGURE (dB)

900MHz

1900MHz

–6 –5 –4 –3 –2 –1 0 1 2 3 4 5 6

IIP3, IIP2 (dBm)

GAIN

IIP3

NOISE FIGURE

IIP2, I CHANNEL

IIP2, Q CHANNEL

07208-012

LO LEVEL (dBm)

GAIN (dB), IP1dB (dBm), NOISE FIGURE (dB)

IP1dB

INPUT IP3

NOISE FIGURE

1 10 100

07208-013

BIAS

(kΩ)

IIP3 (d Bm) AND NOISE FI GURE (dB)

TA = –40°C T

= +25°C

= +85°C

1 10 100

07208-014

BIAS

(kΩ)

GAIN (dB) , IP1dB (d Bm) ,

IIP2 I AND Q CHANNEL (dBm)

900MHz: GAIN 900MHz: IP1d B 900MHz: IIP 2, I CHANNEL 900MHz: IIP 2, Q CHANNEL 1900MHz: GAIN 1900MHz: IP1d B 1900MHz: IIP 2, I CHANNEL 1900MHz: IIP 2, Q CHANNEL

Figure 9. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs.

LO Level, f

Figure 10. IIP3, Noise Figure, and Supply Current vs. R

= 900 MHz

, fRF = 900 MHz

BIAS

Figure 12. Conversion Gain, IP1dB, Noise Figure, IIP3, and IIP2 vs.

LO Level, f

Figure 13. IIP3 and Noise Figure vs. R

= 1900 MHz

, fRF = 1900 MHz

BIAS

Figure 11. Noise Figure vs. Input Blocker Level, f

(RF Blocker 5 MHz Offset)

= 900 MHz, 1900 MHz

Rev. A | Page 8 of 28

Figure 14. Conversion Gain, IP1dB, IIP2_I, and IIP2_Q vs.

, fRF = 900 MHz, 1900MHz

BIAS

Data Sheet ADL5382

IIP2, I AND Q CHANNELS (dBm)

07208-015

BASEBAND FREQUE NCY ( M Hz )

IP1dB, IIP3 (dBm)

0 10 20 30 40 50

IIP2

IIP3

I CHANNEL Q CHANNEL

IP1dB

TA = –40°C T

= +25°C

= +85°C

–80

–70

–60

–50

–40

–30

–20

–10

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-016

LO FREQUENCY (MHz)

LEAKAGE (dBm)

–50

–45

–40

–35

–30

–25

–20

–15

–10

–5

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-017

RF FREQUE NCY ( M Hz )

RETURN LOS S ( dB)

–100

–90

–80

–70

–60

–50

–40

–30

–20

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-018

LO FREQUENCY (MHz)

LEAKAGE (dBm)

–100

–90

–80

–70

–60

–50

–40

–30

–20

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-019

RF FREQUE NCY ( M Hz )

LEAKAGE (dBc)

–30

–25

–20

–15

–10

–5

700 900 1100 1300 1500 1700 1900 2100 2300 2500 2700

07208-020

LO FREQUENCY (MHz)

RETURN LOS S ( dB)

Figure 15. IP1dB, IIP3, and IIP2 vs. Baseband Frequency

Figure 16. LO-to-BB Leakage vs. LO Frequency

Figure 18. LO-to-RF Leakage vs. LO Frequency

Figure 19. RF-to-LO Leakage vs. RF Frequency

Figure 17. RF Port Return L oss vs. RF Frequency Measured on a Characterization

Board through an ETC1-1-13 Balun with 33 nH Bias Inductors

Figure 20. LO Port Return Loss vs. LO Frequency Measured on

Characterization Board through an ETC1-1-13 Balun

Rev. A | Page 9 of 28

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